Section
Page
Description
Edition
20.2.3 AC
Characteristics
(
1
)
Clock Timing
Table 20.18 Clock
Timing
522
12.5 MHz added and description amended
12.5 MHz
20 MHz
Item
Symbol
Min
Max
Min
Max
Unit
Figures
EXTAL input high level
pulse width
t
EXH
22
—
15
—
ns
20.45
EXTAL input low level
pulse width
t
EXL
22
—
15
—
ns
EXTAL input rise time
t
EXr
—
10
—
5
ns
EXTAL input fall time
t
EXf
—
10
—
5
ns
Clock cycle time
t
cyc
80
500
50
250
ns
20.45, 20.46
Clock high pulse width
t
CH
30
—
20
—
ns
20.46
Clock low pulse width
t
CL
30
—
20
—
ns
Clock rise time
t
Cr
—
10
—
5
ns
Clock fall time
t
Cf
—
10
—
5
ns
Reset oscillation settling
time
t
OSC1
10
—
10
—
ms
20.47
Software standby
oscillation settling time
t
OSC2
10
—
10
—
ms
6
(
2
)
Control Signal
Timing
Table 20.19 Control
Signal Timing
524
12.5 MHz added and description amended
12.5 MHz
20 MHz
Item
Symbol
Min
Max
Min
Max
Unit
Figure
RES
setup time
t
RESS
320
—
200
—
ns
20.48
RES
pulse width
t
RESW
20
—
20
—
t
cyc
NMI reset setup time
t
NMIRS
320
—
200
—
ns
NMI reset hold time
t
NMIRH
320
—
200
—
ns
NMI setup time
t
NMIS
160
—
100
—
ns
20.49
NMI hold time
t
NMIH
80
—
50
—
ns
IRQ0
–
IRQ7
setup time
(edge detection)
t
IRQES
160
—
100
—
ns
IRQ0
–
IRQ7
setup time
(level detection)
t
IRQLS
160
—
100
—
ns
IRQ0
–
IRQ7
hold time
t
IRQEH
80
—
50
—
ns
IRQOUT
output delay
time
t
IRQOD
—
80
—
50
ns
20.50
Bus request setup time
t
BRQS
80
—
50
—
ns
20.51
Bus acknowledge delay
time 1
t
BACD1
—
80
—
50
ns
Bus acknowledge delay
time 2
t
BACD2
—
80
—
50
ns
Bus 3-state delay time
t
BZD
—
80
—
50
ns
6
(
3
)
Bus Timing
Table 20.20 Bus
Timing (1)
528
Description amended
Read data access time 2
*
6
t
ACC2
t
cyc
×
(n+2) –
30
*
3
—
ns
20.53, 20.54, 20.57–20.59
6
(
3
)
Bus Timing
Table 20.20 Bus
Timing (2)
530 to
532
Newly added
6
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