Section 12. Power-Down State
12.1 Overview
The H8/329 Series has a power-down state that greatly reduces power consumption by stopping
some or all of the chip functions. The power-down state includes three modes:
(1) Sleep mode – a software-triggered mode in which the CPU halts but the rest of the chip
remains active
(2) Software standby mode – a software-triggered mode in which the entire chip is inactive
(3) Hardware standby mode – a hardware-triggered mode in which the entire chip is inactive
Table 12-1 lists the conditions for entering and leaving the power-down modes. It also indicates the
status of the CPU, on-chip supporting modules, etc. in each power-down mode.
Table 12-1. Power-Down State
Entering
CPU
Sup.
I/O
Exiting
Mode
procedure
Clock
CPU
Reg’s.
Mod.
RAM
ports
methods
Sleep Execute
Run
Halt
Held
Run
Held
Held
• Interrupt
mode
SLEEP
• RES
instruction
• STBY
Soft-
Set SSBY bit
Halt
Halt
Held
Halt
Held
Held
• NMI
ware
in SYSCR to
and
• IRQ
0
– IRQ
2
standby
“1,” then
initial-
• STBY
mode
execute SLEEP
ized
• RES
instruction
Hard-
Set STBY
Halt
Halt
Not
Halt
Held
High
• STBY High,
ware
pin to Low
held
and
impe-
then RES
standby
level
initialized
dance
Low
→
High
mode
state
Notes: 1. SYSCR: System control register
2. SSBY:
Software standby bit
239
Содержание H8/326 Series
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