Hitachi H8/326 Series, Руководство по оборудованию

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Section 4. Exception Handling
4.1 Overview
The H8/329 Series recognizes only two kinds of exceptions: interrupts and the reset. Table 4-1
indicates their priority and the timing of their hardware exception-handling sequences.
Table 4-1. Hardware Exception-Handling Sequences and Priority
Type of
Priority exception Timing of exception-handling sequence
High Reset The hardware exception-handling sequence begins as soon as RES
changes from Low to High.
Interrupt When an interrupt is requested, the hardware exception-handling
sequence begins at the end of the current instruction, or at the end of
Low the current hardware exception-handling sequence.
4.2 Reset
4.2.1 Overview
A reset has the highest exception-handling priority. When the RES pin goes Low, all current
processing stops and the chip enters the reset state. The internal state of the CPU and the registers
of the on-chip supporting modules are initialized. When RES returns from Low to High, the reset
exception-handling sequence starts.
4.2.2 Reset Sequence
The reset state begins when RES goes Low. To ensure correct resetting, at power-on the RES pin
should be held Low for at least 20ms. In a reset during operation, the RES pin should be held Low
for at least 10 system clock cycles. For the pin states during a reset, see appendix C, “Pin States.”
When RES returns from Low to High, hardware carries out the following reset exception-handling
sequence.
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