Bit 0—Counter Clear A (CCLRA): This bit selects whether to clear the FRC at compare-match
A (when the FRC and OCRA values match).
6.2.6 Timer Control Register (TCR)—H'FF96
The TCR is an 8-bit readable/writable register that selects the rising or falling edge of the input
capture signals, enables the input capture buffer mode, and selects the FRC clock source.
The TCR is initialized to H'00 at a reset and in the standby modes.
Bit 7—Input Edge Select A (IEDGA): This bit causes input capture A events to be recognized on
the selected edge of the input capture A signal (FTIA).
Bit 6—Input Edge Select B (IEDGB): This bit causes input capture B events to be recognized on
the selected edge of the input capture B signal (FTIB).
Bit 0
CCLRA
Description
0
The FRC is not cleared.
(Initial value)
1
The FRC is cleared at compare-match A.
Bit
7
6
5
4
3
2
1
0
IEDGA
IEDGB
IEDGC
IEDGD BUFEA BUFEB
CKS1
CKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 7
IEDGA
Description
0
Input capture A events are recognized on the falling edge of FTIA.
(Initial value)
1
Input capture A events are recognized on the rising edge of FTIA.
Bit 6
IEDGB
Description
0
Input capture B events are recognized on the falling edge of FTIB.
(Initial value)
1
Input capture B events are recognized on the rising edge of FTIB.
125
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