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2294854-100, R
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LOGIQ™ 9 P
ROPRIETARY
M
ANUAL
Chapter 7 Diagnostics/Troubleshooting
7-35
Section 7-8
Preferred Test Strategy for PCI 9054 Interface
NOTE:
This only applies to systems with the SCB, EQ and BMP boards configuration. This does not
apply to systems with EBM Boards.
Several LOGIQ™ 9 circuit boards utilize the PCI 9054
PCI Bus Master I/O Accelerator
chip. This section
defines a common testing strategy for a PCI interface implemented with the 9054. Deviation from this
strategy may be required or preferable in some circumstances. When this is the case, the diagnostic's
SDD must note the deviation.
Depending upon where in the diagnostic an error is found, the nature of the error can be determined.
The following are examples of messages that may be reported:
•
Bad C/BE# Line (give number)
•
Bad AD Line (give number)
•
Bad Serial EEPROM
7-8-1
General Strategy
Some degree of functionality is already tested when the system boots up and enumerates the PCI bus.
The idea here is to toggle all of the relevant PCI signals to determine if they are functioning (it's possible
that the PCI interface was detected and set up by the host, but only by luck due to some signal error).
The focus is on the C/BE# signals and the AD lines. Also, we want to know that the serial EEPROM is
communicating properly with the PCI 9054. For all practical purposes, the control lines on the PCI bus
will need to be functioning properly for all of the data transfers to occur correctly.
While this testing strategy is complete in terms of the signal lines, there is no explicit validation that
memory reads and writes will function properly, due, for instance, to some error in the PCI 9054 chip
(all of the interface accesses occur through the VPD functionality, as described below). Any 9054
memory access errors will be found during the board's memory test.
Also, this interface test does not test the DMA functionality on the 9054, since these DMA channels are
not utilized by most 9054 implementations in LOGIQ™ 9. Any DMA functionality that is used will be
tested via a board-level or system-level memory diagnostic (notably, TD Channel Memory transfers
from the SCB).
Lastly, PCI timing issues (e.g. wait states, delayed reads, etc.) are not tested. It is assumed that any
required timing functionality in the interface will be tested during the board's memory test.
7-8-1-1
Strategy for Testing the C/BE# Signals
By selectively asserting each of the byte enable bits for four successive reads, the validity of the C/BE#
signals can be verified. This will suffice for testing the various commands that can be issued over the
PCI bus. Testing the command modes explicitly would be significantly more difficult. Also, not all boards
support all commands, and the pre-fetching modes are hard to verify before the on-board memory itself,
is verified.
7-8-1-2
Strategy for Testing the AD Signals
Since the address and data are multiplexed on the PCI bus, we can utilize the data to validate the signal
lines.
7-8-1-3
Strategy for Testing the EEPROM Link
The VPD function of the PCI 9054 allows the host to write and read from the serial EEPROM. An Lword
location in the EEPROM is reserved for this purpose.
