GE M
EDICAL
S
YSTEMS
PROPRIETARY
TO
GE
D
IRECTION
2294854-100, R
EVISION
3
LOGIQ™ 9 P
ROPRIETARY
M
ANUAL
Chapter 5 Components and Functions (Theory)
5-11
5-3-3
Scan Control Board (SCB, SCB2)
The Scan Control Board combines onto one board the basic functionality of Image Port (IP), Front End
Control and Timing (FECT), Scan Sequencer (SS2) and the Scan Trigger (System Timing).
A PCI Slave provides communication to the Scan Control Board. The Scan Control Board only supports
64 MB of image memory. The IP2 section of the board serves as an interface for B- and M-Mode image
data, video data, and raw I/Q data to be ported to the PC for scan conversion or for further image
processing, as in the case of the I/Q data. The image data received from the BMP board will be in a
standard eight-bit grayscale format while the I/Q data is received in 16-bit multiplexed data format.
The data on each path will be converted to the PipeLink Format within the IP2 section of the board. The
FECT section of the board is the master source of timing generation for the entire system. Additionally,
it provides the address generation, MUX and interface control for the Time Delay (TD) board during Host
accesses and channel memory to RIGEL register transfer mode.
The SS2 section of the board performs vector scan control sequencing and interfaces the scan bus to
the rest of the system. Each of the four functional blocks will be described at a requirements and
functional specification level in future sections.
Figure 5-11 SCB Simplified Block Diagram
FEC INT:
TD_HVFAULT*
HVINT*
I2CINT*
PRBINT*
CWINT*
(From IP2 Block)
SCAN TIGGERS(2:0)
EQ_BE_RxSync
PA_SCB_ACFAIL(1:0)
QRS*
LOC_SCAN_BUS(17:0)
System Clocks
MFG Test Clocks
SCB_EQ_RxSync
VIDEO_DAT(4:0)
From BMP
BM_SCB_DAT(9:0)
From MEQ
IQ_SCB_DAT(31:0)
FE_SYTM_BUS(59:0)
FECB_CLK(10:0)
LOC_CLK
IP_CLK
IP_CLK
EQ_BE_RxSync
LOC_SCAN_BUS(13:0)
LOC_SLV_PCI_BUS(60:0)
To MEQ & BMP
GLOB_SEC_PCI(61:0)
IP_CLK
PCI 33MHz
VID_CLK
VP_DAT(7:0)
SCAN SEQUENCER BLOCK
Scan Sequencer
and
Peripherals
Scan Bus
I/F
VP_ADR(4:0)
VP_STB
SCAN I/F LE
To MEQ, BMP
SYS_SCAN_BUS(13:0)
SYSTEM TIMING BLOCK
FECT BLOCK
Front End Control
Board Block
System
Timing
Control
Clock
Generation
To TD Boards
FEC_TD_BUS(80:0)
LOC_CLK
DSP PCI & CTRL
PCI Slave
and
Decode
PCI Interface
IMAGE PORT 2 BLOCK
Image
Memory
IP
CONTROL
IP_CLK
IP_CLK
IP_CLK
Video
and
Pipelink
Input
IP CTRL
Local PCI Bus
Cable From PC
PRIM_PCI(52:0)
