GE M
EDICAL
S
YSTEMS
PROPRIETARY
TO
GE
D
IRECTION
2294854-100, R
EVISION
3
LOGIQ™ 9 P
ROPRIETARY
M
ANUAL
Chapter 7 Diagnostics/Troubleshooting
7-39
7-9-1-5
Strategy for Testing Multiple-Part RAM's
Special consideration must be paid to the data patterns written to a RAM that is implemented with more
than one parts. For example, consider a 32-bit wide RAM that is implemented with 8 4-bit wide parts.
For this RAM, the test data pattern width must be considered to be 4 bits wide and repeated on all eight
nibbles of the 32-bit Lword. For example, if we wanted to write 0x3 to test the data bits, we should write
0x33333333, such that each of the eight nibble-wide parts have the test data applied. Thus, the
maximum one-hot (one "1", all the rest "0") data value we would ever write to the local memory is 0x8,
which would be applied to the RAM as 0x88888888.
When implementing the Preferred Strategy for Testing Memory for a multiple-part RAM, simply consider
the data width to be as wide as a single part, repeating the data to fill the 32-bit Lword. The procedure
then still holds.
Additionally, this test must ensure that the individual RAM devices are all being accessed. To that end,
unique data must be written to each part. Thus, (continuing with the 8, 4-bit wide RAM example) we
have the additional need to apply test data such as 0x00000008, x00000090, 0x00000A00,
0x0000B000, 0x000C0000, 0x00D00000, 0x0E000000, and 0xF0000000 to eight different local RAM
addresses. When this data is read back and verified, we know that the data lines are not crossed or
corrupted.
The reasoning behind all of this is that if the data is incrementing from a small value, for instance, then
all zero data will be written to and read from devices that comprise the most significant data in the RAM
bank. Therefore, we can't be sure that these devices are being addressed properly (assuming the non-
targeted locations contain zeros too). Utilizing the bitwise inverse of the data in the address test
somewhat alleviates this problem; however, there is little overhead associated with the extra accesses
to ensure that individual RAM devices are all being accessed properly.
