Fujitsu M2488, Руководство по эксплуатации продукта

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M2488 PRODUCT GUIDE MAINTENANCE AND SERVICING
April 1997 CG00000-011503 REV. A 8-25
Tests may be aborted in this mode if the <ENTER> key is pressed while the test list is executing.
The current test list node will continue executing to completion (or until an error is encountered)
and the test list will be aborted prior to execution of the next node.
8-4.4.2 Off-Line Diagnostics
Off-Line diagnostics may be invoked through the RS-232 user interface by simultaneously press-
ing the START and UNLOAD keys on the operator control panel. Then select the main menu item
DIAGMODE by pressing START. The next level of menus begin with run. Press the UNLOAD
key once. The operator control panel should now display RS-232. Press the START key to select
the RS-232 menu item. At this point, the Operator Control Panel will flash the message “RS-232?”
and input will only be accepted from the RS-232 port by entering commands at the Off-Line diag-
nostic command prompt. All of the commands discussed in section will be available. Entering the
“Quit” command will return control to the Operator Control Panel keys.
8-4.4.3 In-line Diagnostics
The types of tests performed are determined by the Selftest bit of the SEND DIAGNOSTICS com-
mand. A selftest bit of 1 performs the default selftest, as described in paragraph a. A selftest bit of
0 directs the target to perform tests defined by the bytes in the parameter list, as described in para-
graph b.
a. Selftest
The default selftest consists of the tests described in Table 8-19.
Table 8-19. Selftest Description.
TEST DESCRIPTION
PCC Timers Timer 0-2 Tests Test each timer in PCC Function and verify that it operates at 5% of normal value.
CP Bus Tests
Parity checking: Force parity errors on the CP bus and verify that an interrupt is gener-
ated
Invalid Address Detection: Attempt to access an address beyond the known address space
and verify that an interrupt is generated.
PCC Tests
External Register Tests: Write/verify to all writable registers and read all readable regis-
ters. Verify RSVP counters and microcode timers in the PCC chip.
SDDP Tests
External Register Tests: Write/verify to all writable registers and read all readable regis-
ters.
Data buffer DRAM Verification: Write/verify entire SDDP data buffer DRAM (256 bytes
at a time).
Host Packet Processor: Verify that packet headers are built correctly for EDRC write and
read operations.
EDRC Tests Verify data compression capability with “canned” data patterns
Formatter Tests
Registers for RSVP Interface, Read, Write and Test Jump. Verify formatter counters and
interrupts.
Loop Write/Read LVL1 -
Digital Tests Data is written into the data buffer and passed from the data buffer to the MTU. The
MTU returns the data to the formatter through both the analog and digital check circuitry.
No tape motion is required.
Loop Write/Read LVL2 -
Analog Tests Data is written into the data buffer and passed from the data buffer through the formatter.