Fujitsu M2488, Руководство по эксплуатации продукта

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M2488 PRODUCT GUIDE DESIGN ARCHITECTURE
April 1997 CG00000-011503 REV. A 2-3
packet, to be built without requiring additional buffering. Data buffering increases overall perfor-
mance by allowing data streaming since the buffer can mask or eliminate some tape repositions.
The EDRC chip set consists of a compression engine (CE), a decompression engine (DE), and a data
control function (SG). The SG LSI is used twice in the design, once each for the CE and DE. The
complete chip set is designed to operate at the full data path rate of 20 MB/s. In addition, The com-
pression SG input FIFO is 64k bytes for compression data caching. If compression retries are ever
required, retries can automatically be performed without host intervention.
2-3.4 Microprocessor Control
A 20MHz MB68930 Sparc-lite MPU is the single Control Processor (CP) used for the controller
requirements. The controller CP communicates directly to the drive servo CP via dual-port RAM.
The RSVP (Read Signal Verification Processor) is a 10 Mhz, 24-bit, fixed instruction sequencer that
is embedded inside the PCC (Processor Companion Chip). It requires less than 4200 basic cells of the
22,800 cells in the PCC. The RSVP provides the dedicated formatter signal processing needed to
support the CP with the time critical formatter control. It allows the controller firmware architecture
to use event driven multi-tasking for the CP code and allow the RSVP to handle dedicated read signal
polling. The RSVP presents interrupts to the CP based on drive read interface signals which are pre-
processed; polled, monitored, filtered, and conditioned as required.
DATA BUFFER
WITH EDRC
FORMATTING
FORMATTER
MICROPROCESSOR
DRIVERS
RECEIVERS
PROCESSOR
COMPANION
CHIP
CP
B
U
S
SC
S
I B
U
S
Figure 2-2. DTC PCA Block Diagram
(RSVP Controller)
SN75LBC976
SCSI
PROTOCOL
CONTROLLER
MB86603
E
D
RC
CO
M
P
RE
S
S
IO
N
SCSI
SDDP
RS
DRAM
DRAM
NVRAM
PCC
MB86930
SPARC lite
RS232
DRV/RCV
4- 256K x 18
MB8486A
S
HAR
E
D
R
A
M
IN
T
E
R
F
A
C
E
9
9
WRITE
HEAD
SE
R
V
O
PR
O
C
E
SSO
R
FIFO SRAM
DE
SG
CE
SG
18
AXP
CP
RS
V
P
_
I/
F
CP
BU
S
CP
BU
S
RCTL
WFMT
DSKW
SRAM
LOGIC
READ
HEAD
LOGIC
32K x 16
(SGC)
(SGD)
FLASH
MASK-
ROM
2 x 512K x 8
2 - 256K x 18
(1 Mbyte CS)
8k x 8