Address Decoding
The CPU has a 64K byte address range of 0-FFFF. RAM, EPROM, and I/O ports share this space. The
address decoding circuit splits up this space and output enable lines to the RAM, EPROM, and I/O ports.
U30A generates the static RAMs active low enable signal, RAMEN. When address lines A13, A14, A15 are all
high, U30As output goes low, enabling the RAM. This occurs for the 8K address range of E000-FFFF.
U30B and U28 are used to generate the input port and output port active low enable signals EXINEN and
EXOUTEN. When address lines A15, A14, A11, and A10 are high, and A13 is low, U28 becomes enabled.
With U28 enabled, one of the 8 outputs is set low. The output to go low is selected by pins A, B and C. They
form a 3-bit binary number with pin C being the most significant bit. So when address line A12 is high, WR
active (low) and RD inactive (high), a binary 5 is produced on pins A, B, and C, forcing output Y5 (EXOUTEN)
low. This enables the output port for writing. When address line A12 is high, WR inactive and RD active, a
binary 3 is produced on pins A, B, and C, forcing output Y3 (EXINEN) low. Note that in both previous
conditions, A15, A14, A12, A11, and A10 are high and A13 is low.
The input port and the output port both share the same 1K byte address space of DC00-DFFF. When data are
written to the address, the output port enable signal EXOUTEN is activated. But when data are read from the
same address, EXINEN is activated. Because the CPU is configured to use a 16-bit bus, except for RAM, any
even address in the DC00-DFF range could be used for external port access. In other words, reading or writing
address DC00, DC02, DC04, etc., will all produce the same results. Due to the CPU configuration, the write
strobe WR (WRL pin), is only active for low-byte writes; therefore, both bytes of the external output port must
be written to at the same time. The upper byte of the output port cannot be written to alone, no write strobe and,
therefore, no EXOUTEN signal will be generated.
U30C generates the EPROMs active low enable signal, ROMEN. The active low signals RAMEN and
EXINEN are basically used as EPROM disable signals. When RAMEN or EXINEN or test point TP71 are low,
the output of U30C, ROMEN, is forced high, disabling the ROM. Therefore, the EPROM is disabled for the
range DC00-FFFF and enabled for the 55K byte address range of 0h-DBFF. TP71 is used during board testing
to disable the EPROM.
CPU Memory
The memory system external to the CPU consists of an 8K x 8 static RAM(U14) and a 64K x 16 EPROM
(U15). The EPROM is 16-bits wide to enhance CPU performance. Because RAM is infrequently accessed, it
is only 8 bits wide.
U14 is a standard 8K x 8 static RAM. Test point TP 43 is used during testing to disable the output.
The program that the CPU runs is stored in U15. U15 is a 16-bit wide output, one-time programmable (OTP)
EPROM. During 16-bit wide bus accesses, the CPU uses address line A0 for low/high byte selection; and is not
used as a normal address line. The CPU can only address 64K x 8 bytes or 32K x 16 bytes. Pin A15 of U15 is
tied low, always selecting the lower half of the EPROM. Signal ROMEN is then used to enable the EPROM for
the proper memory area.
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