When the power supply is first switched on by the power control circuit, the reset generation circuit holds the
CPU RESET pin low for at least 20 ms, then allows the internal pull-up resistor to bring it high; this assures a
good CPU reset.
An internal watchdog timer is enabled and runs continuously. The watchdog timer provides a means of
recovering from a software upset caused by ESD, EMI, etc. If the software does not clear the timer at least
every 64K state-times (13.1 ms), the CPU will drive RESET low, resetting the entire unit. The reset output by
the CPU is only 16 state-times long (3.2 µs). Q22 provides isolation from C65 so the CPU can drive a good
reset to the display control circuit.
The CPU has the ability to dynamically switch the data bus width–based on the BUSWIDTH input pin. A low
on BUSWIDTH tells the CPU to access memory only 8 bits at a time. When accessing the static RAM,
BUSWIDTH is low, automatically reading the 8-bit wide RAM. Since BUSWIDTH is connected to the active
low RAM enable line (RAMEN), all other memory and mapped I/O are read or written 16 bits at a time.
Eight analog inputs are measured by the CPU. Input from the SpO
2
analog section includes AC and DC signals
for the oximeter sensor red and infrared channels, and the sensor calibration resistor RSENS. Light,
temperature, and battery voltage are also measured.
The N-20P CPU is configured as follows:
•
Decoded AD0 and BHE generates separate WR write strobes for the low and high bytes of a word. The
signal WR (pin WRL) is the low-byte write strobe.
•
A standard address latch enable (ALE) is generated and used.
•
HSO pins 4 and 5 are configured as outputs. The HSO is used to generate stable timing control signals to
the SpO
2
analog section, display, and printer.
•
The timer-2 external control pins: T2CLK, T2RST, T2U-D, and T2CAPT are disabled via software and
used as standard I/O.
•
The HOLD, HLDA, and BREQ bus accessing is disabled via software and the pins are used as standard I/O.
•
Pins HS10 and EXTINT are configured for interrupt input. The CPU receives 2 external interrupts (signals
PR TACH and PHOTO1)
•
RXD and TXD are configured as a standard asynchronous serial transmitter and receiver for the serial
interface.
•
PWM0, PWM1, and PWM2 pins are configured as pulse width modulator outputs. They are used to control
gains within the SpO2 analog section.
Address Demultipleixing
U13 and U33 are transparent latches that latch the address portion of the AD bus data on the falling edge of
ALE; the outputs are always enabled. The outputs of U13 and U33 are always the address portion of the AD
bus.
12-14