DBS9900 User’s Manual
7-20
DBS9900 Clock
82-28993 Revision 01
Table 26 – DAC Codes
DAC Code
Analog Output
FF
+9.921875
81
+78.125mV
80
0V
7F
-78.125mV
01
-9.921875V
00
-10.0V
Table 27 - Clock B Threshold Register Map Base + 0x14
Base + 0X14
Clock B
Register Map
Default
Data Bus
Function
D[07]
CLKB_THRESH[7] , MSB
Set to 0
R/W
D[06]
CLKB_THRESH[6]
Set to 0
R/W
D[05]
CLKB_THRESH[5]
Set to 0
R/W
D[04]
CLKB_THRESH[4]
Set to 0
R/W
D[03]
CLKB_THRESH[3]
Set to 0
R/W
D[02]
CLKB_THRESH[2]
Set to 0
R/W
D[01]
CLKB_THRESH[1]
Set to 0
R/W
D[00]
CLKB_THRESH[0], LSB
Set to 0
R/W
Table 28 - Time Base Address Map Base + 0x18 (9h)
Base + 0X18
Time Base Address FUNCTION
Default
Data Bus
TB CONTROL
C=9h
D[03]
C[4]
Control bit, set to 1
Set to 0
R/W
D[02]
C[3]
Control bit, set to 0
Set to 0
R/W
D[01]
C[2]
Control bit, set to 0
Set to 0
R/W
D[00]
C[1]
Control bit, set to 1
Set to 0
R/W
7.13 Trigger A Threshold Register
The Trigger A Threshold Register
(0x14, Base + 0x18 = Ah)
R/W,
stores the bits needed to set
the Trigger A zero crossing thresholds. The byte,
D[07:00]
contains programming bits for Trigger
A. To access this register, the software driver writes to the control bits located in
Base +
0x18 =
Ah
of the VXI FPGA. This register instructs the FPGA that the next register writes the
Trigger A
Threshold Register
at
0x14
. The zero crossing of the Trigger threshold is set by programming
one of four DAC’s in a quad 8 bit DAC to a voltage from –10V to +9.921875V in 78.125mV steps.
The coding is offset binary and the code map is as follows:
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