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DBS9900 User’s Manual
DBS9900 Clock
7-13
82-28993 Revision 01
clocked with the divide by 8 output of the
HSDIV
counter. It runs at one-eighth of the PLL clock
frequency (
Fvco
), 12.5MHz to 25MHz. The
LSDIV
output then goes to a flip-flop to square up the
output. The
HSDIV
divider should be programmed to 7h when the low speed divider is being
used.
LSDIV
divides
Fvco
by the formula:
Ftb = Fvco / (16 * (LSDIV[15:0] + 2)
where 0
≤
LSDIV[15:0]
≤
65,535. The possible division
ratios available from
LSDIV
range from 32 to 1,048,592 in steps of 16.
The
LSDIV
Register
should be initialized to the following state:
•
All bits set low
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