DBS9900 User’s Manual
7-8
DBS9900 Clock
82-28993 Revision 01
N19
enables one of four
FastLock Modes
. This bit is not used, and should be set low.
The data latched into
N[18:6]
programs the
B-COUNTER
divider.
N18
is the MSB and
N6
is the
LSB. The count in
B
can take on values of 3
≤
B
≤
8191 where
A
≤
B.
The data latched into
N[5:4]
performs no function in the LMX2306.
Data latched into
N[3:1]
programs the
A-COUNTER
Divider.
N3
is the MSB and
N1
is the LSB.
The count in
A
can take on values of 0
≤
A
≤
7 where
A
≤
B
7.6.4
PLL FUNCTION LATCH
The
FUNCTION LATCH
(0x14, 0x16, Base + 0x18 = 2h or 3h) R/W
is a 21 bit control word that
is transmitted to the Mother Board VXI Interface FPGA in one 16-bit and one 5-bit write. The
software driver writes to the control bits located in
0x18 = 2h or 3h
of the VXI FPGA. This register
instructs the FPGA that the next two register writes
0x14
and
0x16
will be directed through a
parallel to serial shift register to the
FUNCTION LATCH
. The control word
C[4:1]
, is
concatenated to the end of the bit string, and controls the register inside the PLL that is to be
loaded upon completion of the serial transfer. The software driver writes the MSB’s of the
Function Latch to
BASE + 0x14
. The five LSB’s are transmitted to
BASE + 0x16
.
The 21-bit serial shift register is loaded MSB first, via the data input on the rising edge of the
clock when the Latch Enable (
PLL_LE
) goes low. Loading is complete after 21 rising edges of
the clock. The internal register is latched on the rising edge of
PLL_LE
. The Function Latch
configures the LMX2306 for various modes of operation.
The data format for the Function Latch is shown in the tables below.
F19
is used for Test Modes,
and should be set to 0.
The Function Latch should be initialized to the following state:
•
F[1]
should be set high, then low in two consecutive writes, in order to reset and re-
synchronize the internal counters.
•
FO_LD
MUX control should be set to
F[5:3] = 1h
so that
Digital Lock Detect
is available
at the
FO_LD
pin to detect when the PLL is in lock.
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