DBS9900 User’s Manual
8-2
DBS9900 Programming Examples
82-28993 Revision 01
7. Program N Register: Since N = Fvco / Fpd, N = [(P X B) + A]; where P = 8, N = 4000. From
the formula B = 500 and A = 0. See section
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for
restrictions on A, B and N.
Program PLL Registers:
Program R Register:
Write 0h to Addr 0x18
Write to R Register
Write 0019h to Addr 0x14
(200d = R => HEX(R) = c8h = R[14:1]) => D[15:0] = 0019h
Write 00h to Addr 0x16
Program N Register:
Write 1h to Addr 0x18
Set Address to N Register
Write 07D0h to Addr 0x14
(500d = B => HEX(B) = 1F4h = B[12:0]) => D[15:0] = 7D0h
Write 00h to Addr 0x16
(0d = A => HEX(A) = 0h = A[2:0]) => D[4:0] = 00h
Program F Register:
Write 3h to Addr 0x18
Set Address to F Register
Write 0h to Addr 0x14
((FO_LD=1h, Counter Reset=1h => F[3:1] = 5h) => 05h) => D[4:0] = 5h
Write 04h to Addr 0x16
((FO_LD=1h, Counter Reset=0h => F[3:1] = 4h) => 04h) => D[4:0] = 4h
Program Time Base Divider:
Program HSDIV Register:
Write 0007h to Addr 0x18
Set Address to HSDIV Register
Write 7h to Addr 0x14
(8 = HSDIV => HEX(HSDIV - 1) =7h = HSDIV[3:0]) => D[15:0] =0007h
Program LSDIV Register:
Write 5h to Addr 0x18
Set Address to HSDIV Register
Write 96b2h to Addr 0x14
(38,580 = LSDIV => HEX(LSDIV - 2) =96b2h = LSDIV[15:0]) => D[15:0] = 96b2h
Program Time Base Control Register:
Write 6h to Addr 0x18
Set Address to TBC Register
Write 3100h to Addr 0x14
(REFSEL = 0, PLL_EN = 1, INTREF = 1, FREQSEL[1:0] = 1) => D[15:0] = 3100h
Program CLK B Threshold Register:
Write 9h to Addr 0x18
Set Address to Clock Threshold Register
Write 0097h to Addr 0x14
(+1.8V = -10 + THRESH_A * .078125 => THRESH_A = 151d => 97h) => D[7:0] = 97h
Program Clock Control:
Write 4h to Addr 0x18
Set Address to CLK Control Register
Write 0017h to Addr 0x14
EXTCLK A_EN = 0, EXTCLK B_EN = 1, CHA_CLKSEL[1:0] = 1, CHB_CLKSEL[1:0] = 3 =>
D[15:0] = 0017h,
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