Abov MC96FR364B, Руководство пользователя

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112 November, 2018 Rev.1.4
11.7.3 Register Map
Name Address Dir Default Description
RMR E8
H
R/W 00
H
Remocon Mode Register
RMR2 2F56
H
R/W 00
H
Remocon Mode Register 2
RDCH BA
H
R 00
H
Remocon Data Counter High
CFRH BB
H
R/W FF
H
Carrier Frequency Register High
CFRL BC
H
R/W FF
H
Carrier Frequency Register Low
RDCL BD
H
R 00
H
Remocon Data Counter Low
RODR BE
H
R/W 00
H
Remocon Output Data Register
ROB BF
H
R/W 00
H
Remocon Output Buffer
RDBH C2
H
R/W FF
H
Remocon Data Buffer High
RDBL C3
H
R/W FF
H
Remocon Data Buffer Low
RDRH C4
H
R/W FF
H
Remocon Data Register High
RDRL C5
H
R/W FF
H
Remocon Data Register Low
Table 11-13 Register Map of Carrier Generator
11.7.4 Register Description
RMR (Remocon Mode Register) E8
H
7 6 5 4 3 2 1 0
RDIF CEN CCK1 CCK0 RDPE RDCK2 RDCK1 RDCK0
R R/W R/W R/W R/W R/W R/W R/W
Initial value : 00
H
RDIF Interrupt flag. This flag is cleared when the interrupt is serviced,
RDPE bit is cleared or software writes ‘0’ to this bit position. This
flag has nothing to do with CEN bit.
Writing ‘1’ to this bit sets the
interrupt flag.
RDCK[2:0] Selects clock source for 6-bit RDC counter. These bits are effective
only when RDPE=1.
NOTE
RDCK2 RDCK1 RDCK0
0 0 0 f
SCLK
/ 1
0 0 1 f
SCLK
/ 2
0 1 0 f
SCLK
/ 3
0 1 1 f
SCLK
/ 4
1 0 0 f
SCLK
/ 8
1 0 1 f
SCLK
/ 16
1 1 0 f
SCLK
/ 64
1 1 1 Carrier Signal(=CRF)
RDPE Remote Data Pulse Enable. Setting this bit enables RDC counter.
Interrupt can only be issued when this bit is set.
0 Disable RDC counter
1 Enable RDC counter
CCK[1:0] Select clock source for 8-bit CRC counter. These bits are effective
only when CEN=1.
NOTE
0 0 f
SCLK
/1
0 1 f
SCLK
/2
1 0 f
SCLK
/ 3
1 1 f
SCLK
/ 4