Abov MC96FR364B, Руководство пользователя

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November, 2018 Rev.1.4 89
T2L CF
H
R/W 00
H
Timer 2 Counter Low
T2DRL CF
H
W FF
H
Timer 2 Data Register Low
CDR2L CF
H
R 00
H
Timer 2 Capture Data Register Low
Table 11-7 Register Map of Timer 2
11.4.2.6 Register Description
CDR2H, T2DRH and T2H registers share peripheral address. Reading T2DRH gives CDR0 in
Capture Mode, T2H in Output Compare Mode. Writing T2DRH alters the contents of T2DRH in any
mode. This applies to the case of CDR2L, T2DRL and T2L registers.
T2CR (Timer 2 Mode Control Register) C6
H
7 6 5 4 3 2 1 0
EC2E T2_PE CAP2 T2CK2 T2CK1 T2CK0 T2CN T2ST
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value : 00
H
EC2E Enable event counter mode of Timer 2.
0
Timer 2 is a normal counter.
1 Timer 2 is an event counter clocked by EC2.
T2_PE
Controls whether to output Timer 2 output or not through I/O pin.
0
Timer 2 output does not come out through I/O pin
1 Timer 2 output overrides the normal port functionality of I/O pin
CAP2 Selects operating mode of Timer 2.
0
Timer/Counter mode
1 Capture mode
T2CK[2:0] Selects clock source of Timer 2.
NOTE
T2CK2 T2CK1 T2CK0 Timer 2 clock
0 0 0 f
SCLK
0 0 1 f
SCLK
/2^1
0 1 0 f
SCLK
/2^2
0 1 1 f
SCLK
/2^3
1 0 0 f
SCLK
/2^4
1 0 1 f
SCLK
/2^6
1 1 0 f
SCLK
/2^8
1 1 1 CRF (Carrier)
T2CN Decides whether to pause or continue counting.
0
Pause counting temporarily
1 Continue to count
T2ST
Decides whether to start or stop counter
0
Stops counting
1 Clears counter and starts up-counting
NOTE f
SCLK
is the frequency of internal operating clock, SCLK.
T2L (Timer 2 Counter Low, Read Case) CF
H
7 6 5 4 3 2 1 0