Abov MC96FR364B, Руководство пользователя

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November, 2018 Rev.1.4 133
When UCPHA=1, the slave begins to drive its MISO output when SS goes active low, but the data is
not defined until the first XCK edge. The first XCK edge shifts the first bit of data from the shifter onto
the MOSI output of the master and the MISO output of the slave. The next XCK edge causes both the
master and slave to sample the data bit value on their MISO and MOSI inputs, respectively. At the
third XCK edge, the USART shifts the second data bit value out to the MOSI and MISO output of the
master and slave respectively. When UCPHA=1, the slave’s SS input is not required to go to its
inactive high level between transfers.
Because the SPI logic reuses the USART resources, SPI mode of operation is similar to that of
synchronous or asynchronous operation. An SPI transfer is initiated by checking for the USART Data
Register Empty flag (UDRE=1) and then writing a byte of data to the UDATA Register.
Caution : In master mode of operation, even if transmission is not enabled (TXE=0), writing data to
the UDATA register is necessary because the clock XCK is generated from transmitter block.
11.9.11 Register Map
Name Address Dir Default Description
UCTRL01 E2
H
R/W 00
H
USART0 Control 1 Register
UCTRL02 E3
H
R/W 00
H
USART0 Control 2 Register
UCTRL03 E4
H
R/W 00
H
USART0 Control 3 Register
USTAT0 E5
H
R 80
H
USART0 Status Register
UBAUD0 E6
H
R/W FF
H
USART0 Baud Rate Generation Register
UDATA0 E7
H
R/W FF
H
USART0 Data Register
UCTRL11 FA
H
R/W 00
H
USART1 Control 1 Register
XCK
(UCPOL=1)
MISO
MOSI
XCK
(UCPOL=0)
/SS OUT
(MASTER)
BIT7
BIT0
/SS IN
(SLAVE)
BIT6
BIT1 …
… BIT2
BIT5 BIT0
BIT7 BIT1
BIT6
SAMPLE
MSB First
LSB First
Figure 11-43 SPI Clock Formats when UCPHA=1