92
November, 2018 Rev.1.4
11.4.3.3 16-bit Capture Mode
Capture Mode is enabled by setting CAP3 bit in T3CR register. The clock source is the same as in
output compare mode of operation. When T3H+T3L reaches to the value of T3DRH+T3DRL, an
interrupt is requested if enabled. When a compare-match occurs, the counter values T3H and T3L are
captured into the capture registers CDR3H and CDR3L respectively. At the same time, the counter is
cleared to 0000
H
and starts up-counting.
Bit 6 and 7 in EIEDGE(External Interrupt Edge Selection Register, AD
H
) register select the triggering
condition of external interrupt 3(INT3), a falling edge, a rising edge or both edge.
When Timer 3 operates in IR capture mode, the capture source becomes the output of IR AMP. And
the T3EDGE[1:0] bits in IRCC2 register select the triggering condition of Watch Timer output. In this
mode, Timer 3 detects the envelop of input carrier signal, and the T3IR bit in IRCC2 register should
be cleared to ‘0’
÷64
÷16
P
r
e
s
c
a
l
e
r
MUX
÷1
÷2
÷4
÷8
SCLK
[CE
H
]
T3IF
Timer3
Interrupt
16-bit Timer3 Counter
16-bit Timer3 Data Register
T3CN
Clear
[CC
H
]
Comparator
T3ST
T3H
(8-bit)
T3L
(8-bit)
T3DRH
(8-bit)
T3DRL
(8-bit)
[CB
H
]
[CD
H
]
T3REQ T2REQ T1REQ T0REQ
-
-
T3_PE
POL
T3CR2
X
X
X
X
-
-
X
X
ADDRESS : C9
H
INITIAL VALUE : 0000_--00
B
÷256
EC3E PWM3
E
CAP3 T3CK2 T3CK1 T3CK0 T3CN
T3ST
T3CR
X
0
0
X
X
X
X
X
ADDRESS : CA
H
INITIAL VALUE : 0000_0000
B
EC3 (or
IRSensor)
T3CK[2:0]
3
EC3E
1
CRF
Figure 11-19 Block Diagram of Timer 3 in Output Compare or Event Counter Mode
Содержание MC96FR364B
Страница 17: ...MC96FR364B November 2018 Rev 1 4 17 4 PACKAGE DIMENSION...
Страница 18: ...MC96FR364B 18 November 2018 Rev 1 4 Figure 4 1 PKG DIMENSION 28 TSSOP...
Страница 23: ...MC96FR364B November 2018 Rev 1 4 23 6 3 REMOUT Port Data PAD VDD Figure 6 3 REMOUT port...
Страница 69: ...November 2018 Rev 1 4 69 Initial value 00H BIT 7 0 BIT counter value...
