Abov MC96FR364B, Руководство пользователя

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MC96FR364B
8 November, 2018 Rev.1.4
Figure 11-54 Formats and States in the Slave Receiver Mode ........................................................... 152
Figure 12-1 Wake-up from SLEEP mode by an interrupt .................................................................. 158
Figure 12-2 SLEEP mode release by an external reset ....................................................................... 158
Figure 12-3 Wake-up from STOP mode by an interrupt .................................................................... 159
Figure 12-4 STOP mode release by an external reset ......................................................................... 159
Figure 12-5 Entry into STOP mode and Release sequence ................................................................ 160
Figure 12-6 Entry into BOD mode and Release sequence .................................................................. 161
Figure 13-1 Block Diagram of Reset Circuit ...................................................................................... 162
Figure 13-2 Noise Cancelling of External Reset Pin .......................................................................... 163
Figure 13-3 Reset Release Timing when Power is supplied (VDD Rises Rapidly) ........................... 163
Figure 13-4 Reset Release Timing when Power is supplied (VDD Rises Slowly) ............................. 164
Figure 13-5 Fuse Configuration Value Read Timing after Power On ................................................ 164
Figure 13-6 Operation according to Power Level ............................................................................... 165
Figure 13-7 Reset procedure due to external reset input ..................................................................... 166
Figure 13-8 Example of oscillation..................................................................................................... 166
Figure 13-9 Block Diagram of BOD .................................................................................................. 167
Figure 13-10 Configuration value read timing when BOD RESET is asserted .................................. 168
Figure 14-1 Block Diagram of On-Chip Debug System ..................................................................... 172
Figure 14-2 10-bit transmission packets ............................................................................................. 173
Figure 14-3 Data transfer on the twin bus........................................................................................... 173
Figure 14-4 Bit transfer on the serial bus ............................................................................................ 174
Figure 14-5 Start and stop condition ................................................................................................... 174
Figure 14-6 Acknowledge by receiver ................................................................................................ 174
Figure 14-7 Clock synchronization during wait procedure ................................................................. 175
Figure 14-8 Wire connection for serial communication ..................................................................... 175
Figure 15-1 Program Memory Address Space .................................................................................... 177
Figure 15-2 FLASH Memory Map ..................................................................................................... 184
Figure 15-3 FLASH Memory Address generation ............................................................................. 184