November, 2018 Rev.1.4
143
11.10.7 Synchronization / Arbitration
Clock synchronization is performed using the wired-AND connection of I
2
C interfaces to the SCL
line. This means that a HIGH to LOW transition on the SCL line will cause the devices concerned to
start counting off their LOW period and it will hold the SCL line in that state until the clock HIGH state
is reached. However the LOW to HIGH transition of this clock may not change the state of the SCL
line if another clock is still within its LOW period. In this way, a synchronized SCL clock is generated
with its LOW period determined by the device with the longest clock LOW period, and its HIGH period
determined by the one with the shortest clock HIGH period.
A master may start a transfer only if the bus is free. Two or more masters may generate a START
condition. Arbitration takes place on the SDA line, while the SCL line is at the HIGH level, in such a
way that the master which transmits a HIGH level, while another master is transmitting a LOW level
will switch off its DATA output state because the level on the bus doesn’t correspond to its own level.
Arbitration continues for many bits until a winning master gets the ownership of I
2
C bus. Its first stage
is comparison of the address bits.
High Counter
Reset
Fast Device
SCLOUT
Slow Device
SCLOUT
SCL
Wait High
Counting
Start High
Counting
Device1
DataOut
SCL on BUS
Device2
DataOut
SDA on BUS
S
Arbitration Process
not adaped
Device 1 loses
Arbitration
Device1 outputs
High
Figure 11-49 Clock Synchronization during Arbitration Procedure
Figure 11-50 Arbitration Procedure of Two Masters
Содержание MC96FR364B
Страница 17: ...MC96FR364B November 2018 Rev 1 4 17 4 PACKAGE DIMENSION...
Страница 18: ...MC96FR364B 18 November 2018 Rev 1 4 Figure 4 1 PKG DIMENSION 28 TSSOP...
Страница 23: ...MC96FR364B November 2018 Rev 1 4 23 6 3 REMOUT Port Data PAD VDD Figure 6 3 REMOUT port...
Страница 69: ...November 2018 Rev 1 4 69 Initial value 00H BIT 7 0 BIT counter value...
