Abov MC96FR364B, Руководство пользователя

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November, 2018 Rev.1.4 67
11.2 Basic Interval Timer (BIT)
11.2.1 Overview
BIT module is a 8-bit counter used to guarantee oscillator stabilization time when MC96FR364B is
reset or waken from STOP mode. The BIT counter is clocked by a clock divided from system
clock(SCLK) and the divide ratio is selected from BCK[2:0] bits in BCCR register, from 16 to 2048. At
reset, the BIT counter is clocked by a clock which is divided by 512 from SCLK. If BCLKS of SCCR is
set, BIT counter is clocked by a clock which is divided by 1024 from RING oscillator, regardless of
BCK[2:0].
BIT is a 8-bit binary counter and has the following features.
- Guarantees the oscillation stabilization time when a power-on or reset occurs
- Guarantees the oscillation stabilization time when this device wakes-from STOP mode
- Generates interval timer interrupt as a watch function
11.2.2 Block Diagram
÷ 1024
P
re
sc
ale
r
÷16
÷2048
÷32
. . .
3
BCK
BCLKS
BITR BITIF
Overflow
8-bit up-counter
BCCR
ACK
From CPU
Interal BUS line
BCLR
Read
BIT Interrupt
WDT Source Clock
0
1
[8B
H
]
[8C
H
]
SCLK
(System Clock)
RING
OSC
(4MHz)
11.2.3 Register Map
Name Address Dir Default Description
BCCR 8B
H
R/W 77
H
BIT Clock Control Register
BITR 8C
H
R 00
H
Basic Interval Timer Register
Table 11-2 Register Map of BIT
Figure 11-2 Block Diagram of BIT