November, 2018 Rev.1.4
57
IP1 registers. Other interrupts having lower group priority than INT0 cannot be serviced until INT0
service routine is finished even if the INT0 interrupt handler allows those interrupt requests.
Example)
Software Multi Interrupt
INT1 : MOV IE, #01H ;Enable INT0 only
MOV IE1, #00H ;Disable other interrupts
:
MOV IE, #0FFH ;Enable all Interrupts
MOV IE1, #0FFH
RETI
In short, an interrupt service routine may only be interrupted by an interrupt of higher priority than
being serviced. And when more than two interrupts are requested at the same time, the one of
highest priority is serviced first.
10.8 Interrupt Service Procedure
10.9 Generation of Branch Address to Interrupt Service Routine(ISR)
The following figure shows the relationship between the vector address of BIT interrupt and the
branch address to service routine.
Interrupt
Latched
Interrupt
goes
Active
System
Clock
Max. 4 Machine
Cycle
4 Machine
Cycle
Interrupt Processing
: LCALL & LJMP
Interrupt Routine
01
H
25
H
00B3
H
00B4
H
Vector Address for
BITinterrupt
0E
H
2E
H
0125
H
0126
H
Interrupt Service Routine
of BITInterrupt
Figure 10-7 Generating branch address to BIT interrupt service routine from vector table
Figure 10-6 Interrupt Request and Service Procedure
Содержание MC96FR364B
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