Abov MC96FR364B, Руководство пользователя

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November, 2018 Rev.1.4 101
11.5 Watch Timer with event capture function (WT)
11.5.1 Overview
The watch timer (WT) has the function for RTC (Real Time Clock) operation. This module consists of
the clock source select circuit, timer counter circuit, output select circuit and control registers. To
activate watch timer, determine the input clock source, output interval and then set WTEN bit in Watch
Timer Mode Register (WTMR). Control bits can be set individually or at a time. To stop or reset WT,
clear the WTEN bit in WTMR. To obtain high resolution, the counter of WT is composed of low 14-bit
binary counter(=WTIR) and high 7-bit counter(=WT_TMR), that makes the WT counter to become 21-
bit wide. The high and low counters are auto-cleared when each counter reaches to their pre-defined
data values. The WT Interrupt Interval is determined by writing to WTDRH, WTDR1 and WTDR0
registers. To read each WTDRH, WTDR1 and WTDR0 returns WT_TMR, high 6-bit of WTIR, and low
8-bit of WTIR counter value.
When Watch timer operates in IR capture mode, the WT is a simple 14-bit up counter and the counter
is auto-cleared by the rising edge of an incoming event source. In this mode of operation, the 7-bit
counter WT_TMR stops operation and the WTIR counter value is captured into WTCR0, WTCR1,
WTCR2 registers on detecting the rising or falling edge of input carrier signal. The capture sequence
is decided according to the setting of SINGLE and PHASE bits in IRCC1 register.
Note that the divide ratio of input clock applies in different manner whether WT is in normal WT mode
or in IR capture mode.
11.5.2 Block Diagram
÷ 128
f
SCLK
MUX
÷ 64
14-bit Up Counter
(=WTIR counter)
÷
256
f
WCK
/2
14
WTEN OVFDIS WTCL - - - WTCK1
WTMR
f
WCK
OVF = T
WCK
X 2
14
x WTDRH + T
WCK
x WTDR
INT_ACK
P
r
e
s
c
a
l
e
r
WTCK0
÷
32
7-bit Up Counter
(=WT_TMR counter)
WTDR1:WTDR0
WTDRH
D Q
CP
r
RESETB
WTIF
Write ‘ 0 ’ to WTSR
SCLK
T
WCK
= 1 / f
WCK
Figure 11-24 Block Diagram of Watch Timer in Normal mode