68
November, 2018 Rev.1.4
11.2.4 Register Description
BCCR (BIT Clock Control Register)
8B
H
7
6
5
4
3
2
1
0
BITF
BCK2
BCK1
BCK0
BCLR
PRD2
PRD1
PRD0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : 57
H
BITF
Reflects the state of BIT interrupt. To clear this flag, write ‘0’ to this bit
position. The BIT interrupt occurs when BIT counter reaches to the pre-
defined value. The interrupt interval is decided from BCK[2:0] and
PRD[2:0] bits.
0
BIT Interrupt not occurred
1
BIT Interrupt occurred
BCK[2:0]
BCK2
BCK1 BCK0 BIT Clock BIT Interrupt Period
NOTE
0
0
0
f
SYS
/2^4 1.024ms
0
0
1
f
SYS
/2^5 2.048ms
0
1
0
f
SYS
/2^6 4.096ms
0
1
1
f
SYS
/2^7 8.192ms
1
0
0
f
SYS
/2^8 16.384ms
1
0
1
f
SYS
/2^9 32.768ms (default)
1
1
0
f
SYS
/2^10 65.536ms
1
1
1
f
SYS
/2^11 131.072ms
BCLR
Clears BIT Counter. Writing ‘1’ to this bit resets BIT counter to 00
H
.
BCLR bit is auto cleared.
0
BIT counter free runs
1
BIT counter is cleared and counter re-starts
PRD[2:0]
Selects BIT interrupt interval. When BIT counter reaches to the value
listed below, an interrupt may be issued. The BIT interrupt period is
same as the clock period for WDT counter.
PRD2
PRD1 PRD0 Interrupt condition
0
0
0
When BITR[0] = 1
0
0
1
When BITR[1:0] = 11
0
1
0
When BITR[2:0] = 111
0
1
1
When BITR[3:0] = 1111
1
0
0
When BITR[4:0] = 11111
1
0
1
When BITR[5:0] = 111111
1
1
0
When BITR[6:0] = 1111111
1
1
1
When BITR[7:0] = 11111111 (default)
NOTE
This is the case when the frequency of system clock,
f
SYS
, is 4MHz and the overflow period PRD[2:0] is set
to 111
B
. If the BCLKS of SCCR is 1, BCK is don’t care. And then BIT clock source is 250uS.
The BIT interrupt period is acquired by multiplying clock period of BIT counter and the pre-defined
value of BIT counter. That is, T
BIT_INT
= T
BIT_CLK
X 2
(PRD[2:0]+1)
, where T
BIT_INT
is the interval of BIT
interrupt and T
BIT_CLK
is the clock period of BIT counter.
BITR (Basic Interval Timer Register)
8C
H
7
6
5
4
3
2
1
0
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
R
R
R
R
R
R
R
R
Содержание MC96FR364B
Страница 17: ...MC96FR364B November 2018 Rev 1 4 17 4 PACKAGE DIMENSION...
Страница 18: ...MC96FR364B 18 November 2018 Rev 1 4 Figure 4 1 PKG DIMENSION 28 TSSOP...
Страница 23: ...MC96FR364B November 2018 Rev 1 4 23 6 3 REMOUT Port Data PAD VDD Figure 6 3 REMOUT port...
Страница 69: ...November 2018 Rev 1 4 69 Initial value 00H BIT 7 0 BIT counter value...
