Abov MC96FR364B, Руководство пользователя

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82 November, 2018 Rev.1.4
11.4.1.7 Register Map
Name Address Dir Default Description
T0CR B2
H
R/W 00
H
Timer 0 Mode Control Register
T0 B3
H
R 00
H
Timer 0 Register
T0DR B3
H
W FF
H
Timer 0 Data Register
CDR0 B3
H
R 00
H
Capture 0 Data Register
T1CR B4
H
R/W 00
H
Timer 1 Mode Control Register
Source Clock
(f
SCLK
)
T1
T1/PWM1
POL0 = 1
00 01 02 03 04 09 08 07 06 05 0D 0C 0B 0A 02 01 00 0E 06 05 04 03 0A 09 08 07 03 02 01 00 05 04 06
Duty Cycle
(1+05
H
)X2us = 12us
Duty Cycle
(1+05
H
)X2us = 12us
Duty Cycle
(1+05
H
)X2us = 12us
Period Cycle
(1+0E
H
)X2us = 32us  31.25KHz
Period Cycle
(1+0A
H
)X2us = 22us  45.5KHz
Write 0A
H
to PWM1PR
T1CR[1:0] = 10
H
(2us)
PWM1HR = 00
H
PWM1PR = 0E
H
PWM1DR = 05
H
Source Clock
(f
SCLK
)
Duty Cycle(1+80
H
)X250ns = 32.25us
T1
00 01 02 03 04
7F 80 81 82 3FF 00 01 02
T1/PWM1
POL0 = 1
T1/PWM1
POL0 = 1
Period Cycle(1+3FF
H
)X250ns = 256us  3.9kHz
PWM1PR(8-bit)
PWM1DR(8-bit)
PW1H3 PW1H2
PW1H1 PW1H0
1 1 FF
H
0 0 80
H
T1CK[1:0] = 00
H
(f
SCLK
)
PWM1HR = 03
H
PWM1PR = FF
H
PWM1DR = 80
H
Figure 11-14 Example of PWM Waveform (In case frequency of SCLK(=f
SCLK
) is 4MHz
)
Figure 11-15 Behaviour of waveform when changing period (In case f
SCLK
is 4MHz)