November, 2018 Rev.1.4
141
11.10.3 I
2
C Bit Transfer
The data on the SDA line must be stable during HIGH period of the clock, SCL. The HIGH or LOW
state of the data line can only change when the clock signal on the SCL line is LOW. The exceptions
are START(S), repeated START(Sr) and STOP(P) condition where data line changes when clock line
is high.
11.10.4 Start / Repeated Start / Stop
One master can issue a START (S) condition to notice other devices connected to the SCL, SDA
lines that it will use the bus. A STOP (P) condition is generated by the master to release the bus lines
so that other devices can use it.
A high to low transition on the SDA line while SCL is high defines a START (S) condition.
A low to high transition on the SDA line while SCL is high defines a STOP (P) condition.
START and STOP conditions are always generated by the master. The bus is considered to be
busy after START condition. The bus is considered to be free again after STOP condition, ie, the bus
is busy between START and STOP condition. If a repeated START condition (Sr) is generated
instead of STOP condition, the bus stays busy. So, the START and repeated START conditions are
functionally identical.
11.10.5 Data Transfer
Every byte put on the SDA line must be 8-bits long. The number of bytes that can be transmitted
per transfer is unlimited. Each byte has to be followed by an acknowledge bit. Data is transferred with
SCL
SDA
Data line Stable:
Data valid
exept S, Sr, P
Change of Data
allowed
SCL
SDA
START Condition
S
P
STOP Condition
Figure 11-45 Bit Transfer on the I
2
C-Bus
Figure 11-46 START and STOP Condition
Содержание MC96FR364B
Страница 17: ...MC96FR364B November 2018 Rev 1 4 17 4 PACKAGE DIMENSION...
Страница 18: ...MC96FR364B 18 November 2018 Rev 1 4 Figure 4 1 PKG DIMENSION 28 TSSOP...
Страница 23: ...MC96FR364B November 2018 Rev 1 4 23 6 3 REMOUT Port Data PAD VDD Figure 6 3 REMOUT port...
Страница 69: ...November 2018 Rev 1 4 69 Initial value 00H BIT 7 0 BIT counter value...
