November, 2018 Rev.1.4
77
11.4.1.4 8-bit Capture Mode
By setting CAP0(CAP1) to ‘1’ in T0CR(T1CR) register, Timer 0(Timer 1) operates in Capture Mode.
Basic timer function is still effective even in capture mode. So when the counter value reaches to the
pre-defined data value in data register, an interrupt can be issued. When an external interrupt
generating condition is detected on port P36(P37), the counter value is captured into capture register
CDR0(CDR1). At the same time the counter T0(T1) is cleared to 00
H
and counts up again.
The timer interrupt in Capture Mode is very useful when the interval of capture event on port P36(P37)
is longer than the interrupt period of timer. That is, by counting number of timer interrupt, user
software can figure out the time interval of external event. As you know, external interrupt is triggered
by a falling edge, a rising edge or both edge according to the setting of EDEDGE register(Interrupt
Edge Selection Register, AD
H
).
CDR0, T0 and T0DR registers share peripheral address. Reading T0DR gives the value of CDR0 in
Capture Mode, T0 in Timer/Count Mode. Writing T0DR alters the contents of T0DR in any mode.
CDR1, T1 and T1DR is all the same as above.
Содержание MC96FR364B
Страница 17: ...MC96FR364B November 2018 Rev 1 4 17 4 PACKAGE DIMENSION...
Страница 18: ...MC96FR364B 18 November 2018 Rev 1 4 Figure 4 1 PKG DIMENSION 28 TSSOP...
Страница 23: ...MC96FR364B November 2018 Rev 1 4 23 6 3 REMOUT Port Data PAD VDD Figure 6 3 REMOUT port...
Страница 69: ...November 2018 Rev 1 4 69 Initial value 00H BIT 7 0 BIT counter value...
