Abov MC96FR364B, Руководство пользователя

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November, 2018 Rev.1.4 53
10.3 Block Diagram
EA
(IE.7[A8
H
])
Reserved
IRI
BODIF
USTAT0.7/6 [E5
H
]
USTAT0.5 [E5
H
]
BITF.7[8B
H
]
USTAT1.5 [ E5
H
]
USTAT1.7/6 [ E5
H
]
UART RX1
UART TX1
WDTMR.0[8D
H
]
EIFLAG.2[AC
H
]
EIFLAG.0[`AC
H
]
WTMR.4[D4
H
]
TX1
INT13
INT14
INT15
INT16
INT17
INT19
INT20
WDTMR
BCCR
INT23
EIEDGE
EIPOLA
IE[A8
H
]
INT0
INT1
INT2
INT3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
IE1[A9
H
]
IE2[AA
H
]
IE3[AB
H
]
IP[B8
H
] IP1[F8
H
]
Release
Stop/Sleep
FLAG0
FLAG1
FLAG2
FLAG3
INT5
RX0
TX0
RX1
INT6
INT7
INT8
PCI
UART RX0
UART TX0
Timer 0
Timer 1
Timer 2
Timer 3
I2C
REMOCON
WT
WDT
BIT
FLASH
EIFLAG.1[AC
H
]
EIFLAG.3[AC
H
]
Priority High
Priority Low
INT18
KEYSCAN
RMR.7[E8
H
]
Figure 10-2 Block Diagram of Interrupt Controller