TPU2000/2000R Modbus/Modbus Plus/ Modbus TCP/IP Automation Guide
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: 01 03 00 83 00 06 73 lf cr
The decoded LRC checksum is 73. The calculation of the checksum is as such:
1. Neglect the colon (3A) and the lf (Line Feed 0A) and cr (Carriage Return OD). This decreases the
string to
2. The LRC checksum 73 (37 33 in ASCII) should also be saved for comparison to the original data
string. The string for LRC calculation is 01 03 00 83 00 06.
3. The byte data should be added thus 01 + 03 + 00 +83 + 00 + 06 = 8D in HEX. Notice that the bytes
have been decoded from ASCII before performing the addition.
4. A Two’s compliment must be performed on the number to determine the LRC Checksum. Inversion
of the number 8D hex yields 72 hex.
5. To complete the Two’s compliment addition for accurate compilation of the checksum 1 hex must be
added to the inverted bits to yield 72 + 1 = 73 HEX. Thus the two calculated values agree.
Please reference the Modicon Modbus Documentation for additional command configuration on each data type
(0X, 1X, 4X and 6X read write capabilities).
Modbus CRC-16 Calculation
The CRC – 16 error check is much more robust than that of the LRC error check. It is however, a more complex
algorithm to compute. It’s computation is started by setting a word of 16 bits to a value of FFFF hex. A byte of
the message is logically OR’ed with the register word and then shifted in a predictable method. What follows is a
reprint from the protocol manufacturer’s manual MODICON MODBUS PROTOCOL REFERENCE GUIDE – PI-
MBUS-300 Revision J Dated June 1996 published by Modicon Inc. Industrial Automation Systems, One High
Street, North Andover, MA 01845.
“The Cyclical Redundancy Check (CRC) field is two bytes, containing a 16 –bit binary
value. The CRC value is calculated by the transmitting device which appends the CRC
to the message. The receiving device, recalculates a CRC during the receipt of the
message, and compares the calculated value to the value it received in the CRC field. If
the two values are not equal, an error results.
The CRC is started by first preloading a 16 bit register to all 1’s. Then a process
begins of applying successive 8 – bit bytes of the message to the current contents of
the register. Only the eight bits of data in each character are used for generating the
CRC. Start and stop bits and the parity bit do not apply to the CRC.
During the generation of the CRC, each 8-bit character is exclusive ORed with the
register contents. Then the result is shifted in the direction of the least significant bit
(LSB), with a zero filled into the most significant bit (MSB) position. The LSB is
extracted and examined. If the LSB was a 1, the register is then exclusive ORed with a
preset, fixed value. If the LSB was a0, no exclusive OR takes place.
The process is repeated until eight shifts have been performed. After the last eighth
shift, the next 8-bit character is exclusive OR‘ed with the register’s current value and
the process repeats for eight more shifts as described above. The final contents of the
register, after all the characters of the message have been applied, is the CRC value.
1. A procedure for generating a CRC is
2. Load a 16 Bit Register with FFFF hex (all 1’s) Call this the CRC register.
3. Exclusive OR the first 8-bit byte of the message with the two-order byte of the
16 –bit CRC register, putting the result in the CRC register.
4. Shift the CRC register one bit to the right (Toward the LSB), zero-filling the
MSB. Extract and examine the LSB.
5. (If the LSB was 0): Repeat Step 3 ( Another Shift)
