TPU2000/2000R Modbus/Modbus Plus Automation Guide
139
As per Figure 5-45 all 4X memory is read/write capable. In other words, Modbus commands 03 – READ
HOLDING REGISTERS, 16 – WRITE HOLDING REGISTERS, and 23 WRITE/READ HOLDING REGISTERS,
may be used in communicating with the relay.
IT IS MOST IMPORTANT TO REALIZE THAT THE RELAY
DISABLES LINK BETWEEN THE PROTECTIVE RELAY AND THE COMMUNCATION CARD (SIMILAR TO
THE LOCAL REMOTE FEATURE). PROTECTIVE RELAY PROTECTION STILL OCCURS IF SCADA REDI®
IS SET. ONLY THE COMMUNICATION IS DISABLED BETWEEN THE RELAY AND COMMUNICATION
CARD.
C
C
E
E
TARGETS
E
C
TPU 2000
TPU 2000R
OR
SIMULATOR
PC
To AUX COM PORT
WRITING 4X MEMORY
Host
TO COM 3 PORT
READING “FORCED”\
4X MEMORY VALUES
Figure 5-47. Typical Commissioning System
As shown in Figure 5-47, one system (a typical PC operating with a DDE utility and WINDOWS utility for example)
could be forcing the registers and the second system, “the host” verifies that the data values are received
correctly. Although the illustration shows a direct connect scenario, the Host and Simulator devices may be
located offsite and connected to the substation via a modem or fiber optic connection.
Please refer to Section 5 to reference the method of toggling the SCADA REDI® bit Registers 41114 and 41115.
Group II Control Features Explained
Group II places each of the Physical Input statuses reported to the processor in the TPU2000R in to a logical
state which is independent of the state of the contact input status present at the Physical Input of the TPU2000R.
There are three modes which a Physical Input status may be placed in:
•
NORMAL – The TPU2000R Physical Input Status reflects that of the voltage present at the Physical
Input Terminal.
•
FORCED ON – The TPU2000R Physical Input Status reported to the logic of the TPU2000R
processor shall show a state of 1.
•
FORCED OFF – The TPU2000R Physical Input Status reported to the logic of the TPU2000R
processor shall show a state of 0.
The Force Physical Input State only affects the state reported to the central processor logic contained within the
TPU2000R. Table 5-43 lists the definition of the control registers and maps each of the internal control bits.
Seven Registers are required to perform control for Group II functions.