OR
OR
OR
OR
AND
AND
AND
T
1
T
1
TBA_BLOCK
TBA_POTT
MEAS_BWD
BIT_TBE
100
T2
100
T2
OR
OR
OR
OR
AND
AND
AND
T
1
T
1
TBA_BLOCK
TBA_POTT
MEAS_BWD
BIT_TBE
100
T2
100
T2
OR
OR
OR
OR
AND
AND
AND
T
1
T
1
TBA_BLOCK
TBA_POTT
MEAS_BWD
BIT_TBE
100
T2
100
T2
>= 1
>= 1
&
>= 1
>= 1
&
>= 1
>= 1
&
t
= 0 s:
t = signal received
t = CB open:
~
~
A1
A2
B1
B2
TBA_BLOCK
TBA_POTT
T1
MEAS_BWD
T2
100
BIT_TBE
TBA_BLOCK
TBA_POTT
T1
MEAS_BWD
T2
100
BIT_TBE
~
~
A1
A2
B1
B2
~
~
A1
A2
B1
B2
TBA_BLOCK
TBA_POTT
T1
MEAS_BWD
T2
100
BIT_TBE
18000031-IEC19000436-1-en.vsdx
IEC19000436 V1 EN-US
Figure 32: Solutions to combat reversal of power direction
BIT_TBA = ( Unblock) × MeasOreach
BIT_TBE blocks TRIP_POTT (see POTT receive logic)
The critical relay A2 cannot trip, because the reverse measurement signal [MEAS_BWD] is
maintained for at least T1 (setting
t1TransBl) and resets at the latest after T2 (setting
t2TransBl). The purpose of T2 is to ensure that blocking is maintained should there be
autoreclosure of the faulted circuit.
T1 allows time for the incorrect Com Rec signal to reset. Its setting is thus given by the reset
time of relay B2 and the reset time of the communication channel. The receiver signal must not
be prolonged.
Tripping takes place instantaneously, if the tripping condition TBA is still fulfilled after the
time T1.
Tripping always causes the logic to reset, after which it remains inactive for 100 ms. The
faulted circuit will therefore be immediately tripped, for example, in the case of an
unsuccessful autoreclosure attempt.
Section 5
1MRK 505 406-UEN B
Bay protection functions
82
Bay protection functions REB500
Technical manual
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