Table 60: Signals POTT_REC
Signal
In
Out
Source
Drain
MEAS OR2
X
Binary output: Meas Oreach
BIT_UNBL
X
Internal logic signal (UNBLOCK)
HFREC
X
Binary input: Com Rec
BIT_TBE
X
Internal logic signal TRANSBL
DELAY2
X
Binary output: Delay 2
M_OWN
X
Internal logic signal (TRIP2)
EXTBLK_HF
X
Binary input: Com Rec
MEAS_BWD
X
Binary output: Meas Bward
UWEAK_L1
X
UL1 < Umin
UWEAK_L2
X
UL2 < Umin
UWEAK_L3
X
UL3 < Umin
P_WEAK
X
Setting: Weak
On = 1; Off = 0
TBA_POTT
X
Internal logic signal
TRANSBL
TRIP_POTT
X
Internal signal to tripping
logic (TRIP2), where it is
compared with all the
tripping conditions to
generate the binary
signals Trip L1, Trip L2
etc.
UWEAK_POTT
X
Internal signal to tripping
logic (TRIP1)
UWEAK_L1_POTT
X
Internal signal to tripping
logic (TRIP1)
UWEAK_L2_POTT
X
Internal signal to tripping
logic (TRIP1)
UWEAK_L3_POTT
X
Internal signal to tripping
logic (TRIP1)
Overreaching blocking scheme (BLOCK OR)
GUID-26BC59BE-2C94-4675-A3EA-E6724D37FEAC v1
The BLOCK OR logic is divided into a receive logic (BLOC_REC) and a transmit logic
(BLOC_SEND).
The output signals from the receive logic (BLOC_REC) are transferred to the tripping logic,
while taking account of any transient blocking due to reversal of energy direction (TRANSBL).
The output signals from the transmit logic are transferred to the common transmit logic for
PUTT, POTT and BLOCK OR schemes. The tripping and transmit criteria can be seen from the
tabular overview below.
Section 5
1MRK 505 406-UEN B
Bay protection functions
78
Bay protection functions REB500
Technical manual
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