Other combinations of the states of these two inputs do not result in any switching of the
AnalogAddr channels and the prevailing situation is maintained.
•
The function (timer, all measuring elements and the associated outputs) is
automatically re-initialised when busbar inputs are switched. This
procedure takes about 60 ms (internal response times). The function then
begins to evaluate the new busbar voltage and from this instant onwards
the generation of an enable signal (PermitToClose) relating to the new
system configuration is possible.
•
The two binary inputs
uBus1Activ and uBus2Activ shall be not used in
configurations in which only one busbar input (
uBusInput1) is defined.
Blocking inputs for preventing the synchrocheck function from issuing an
enable signal (BlckTrigBus1, BlckTrigBus2, BlckTrigLine)
These are assigned to the corresponding voltage inputs and used mainly when the VT circuit
can be interrupted by fuse-failure equipment (miniature circuit-breakers). In such cases, the
blocking inputs are connected to auxiliary contacts on the fuse-failure equipment. This
precaution eliminates any risk of the synchrocheck function permitting the closure of a circuit-
breaker onto a line it considers to be de-energized, which in reality is under voltage.
Function of the blocking inputs:
•
Both busbar voltage inputs have been configured:
Which of the blocking inputs is enabled depends on which of the busbar inputs
uBus1Activ and uBus2Activ is active, that is, on which voltage input is active:
uBus1Activ
uBus2Activ
Active blocking inputs
(T) TRUE
(F) FALSE
BlckSyncBus1 and BlckSyncLine
(F) FALSE
(T) TRUE
BlckSyncBus2 and BlckSyncLine
Other combinations of the states of these two inputs do not influence the blocking inputs
and the prevailing situation is maintained.
•
If only one busbar voltage input is configured, all the blocking I/Ps (BlkSyncBus1,
BlkSyncBus2 and BlckTrigLine) are enabled regardless of the states of the binary I/Ps
uBus1Activ and uBus2Activ.
The active blocking inputs are connected to an OR function so that a logical 1 from any one of
them causes all the measuring elements and the associated outputs (start, AmplDifOK,
PhaseDifOK, FreqDifOK, LiveBus, LiveLine, DeadBus and DeadLine) and also the enabling
output (PermitToClose) to reset. The algorithm of the synchrocheck function, however,
continues to run.
Inputs for enabling the synchrocheck function (ReleaseInp1, ReleaseInp2)
Since the synchrocheck function is only required during the relevant switching operations and
autoreclosure cycles, it may be blocked at all other times to save processor time. The binary
inputs ReleaseInp1 and ReleaseInp2 are used for this purpose. Internally they are the inputs of
an OR gate, so that at least one must be active before the synchrocheck program will run.
If neither of the two enabling signals is at logical 1, processing of the algorithm ceases. All the
function’s measuring element outputs also reset immediately and any circuit-breaker close
enabling signal (PermitToClose) resets after the time set for
t
‑
Reset.
Conditional enabling of the synchrocheck function is especially recommended, where it has to
operate in conjunction with other functions in the same unit such as distance protection,
Section 5
1MRK 505 406-UEN B
Bay protection functions
128
Bay protection functions REB500
Technical manual
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