BLOCK receive logic (BLOC_REC)
GUID-FF5B11F4-7F28-49B4-BBC1-C4C142D6D30F v1
AND
OR
AND
AND
T1
TRIP_BLOCK
TBA_BLOCK
P_BLOCK
HFFAIL
MEAS_OR2
P_T1_BLOCK
HFREC
DELAY2
M_OWN
BI T_TBE
18000029-IEC19000434-1-en.vsdx
IEC19000434 V1 EN-US
Figure 30: BLOC_REC segment
Table 62: Signals BLOC_REC
Signal
In
Out
Source
Drain
P_BLOCK
X
Setting: Com Mode
BLOCK OR. P_BLOCK= 1
HFFAIL
X
Binary input Com Fail
BIT_TBE
X
Internal logic signal TRANSBL
MEAS OR2
X
Binary output: Meas Oreach
DELAY2
X
Binary output: Delay 2
MEAS_BWD
X
Binary output: Meas Bward
EXTBLK_HF
X
Binary input: Com Rec
P_T1_BLOCK
Setting: t1Block
M_OWN
X
Internal logic signal (TRIP2)
HFREC
X
Binary input: Com Rec
TRIP_BLOCK
X
Internal signal to tripping
logic (TRIP2), where it is
compared with all the
tripping conditions to
generate the binary
signals Trip L1, Trip L2 etc.
TBA_BLOCK
X
Internal logic signal
TRANSBL
Reversal of power direction (TRANSBL)
GUID-967B11E2-07FE-4A97-BAE5-7A1B47E5868E v1
This logic is only used in conjunction with a permissive over-reaching transfer tripping scheme
(POTT) or an overreaching blocking scheme (BLOCK OR) on double-circuit lines with in-feeds
from both ends and a high mutual zero-sequence impedance (both circuits on the same
pylons). A blocking scheme does not require this logic, providing the waiting time is set
sufficiently long.
Section 5
1MRK 505 406-UEN B
Bay protection functions
80
Bay protection functions REB500
Technical manual
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