Factory Configuration (FCFG)
9.2.1.5
CONFIG_RF_FRONTEND_DIV12 Register (Offset = D0h) [reset = FFFFFFFFh]
CONFIG_RF_FRONTEND_DIV12 is shown in
and described in
Configuration of RF Frontend in Divide-by-12 Mode
Divide-by-12 mode is only available for CC13xx.
Figure 9-27. CONFIG_RF_FRONTEND_DIV12 Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
IFAMP_IB
LNA_IB
IFAMP_TRIM
CTL_PA0_TRIM
R-Fh
R-Fh
R-1Fh
R-1Fh
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CTL_PA0_TRI
RESERVED
RFLDO_TRIM_OUTPUT
M
R-1Fh
R-7Fh
R-7Fh
Table 9-29. CONFIG_RF_FRONTEND_DIV12 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-28
IFAMP_IB
R
Fh
Trim value used for ADI_0_RF:IFAMPCTL3.IB.
Value is read by RF Core ROM FW during RF Core initialization.
27-24
LNA_IB
R
Fh
Trim value for ADI_0_RF:LNACTL2.IB.
Value is read by RF Core ROM FW during RF Core initialization.
23-19
IFAMP_TRIM
R
1Fh
Trim value for ADI_0_RF:IFAMPCTL0.TRIM.
Value is read by RF Core ROM FW during RF Core initialization.
18-14
CTL_PA0_TRIM
R
1Fh
Trim value for ADI_0_RF:PACTL0.TRIM.
Value is read by RF Core ROM FW during RF Core initialization.
13-7
RESERVED
R
7Fh
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
6-0
RFLDO_TRIM_OUTPUT
R
7Fh
Trim value for ADI_0_RF:RFLDO1.TRIM_OUT.
Value is read by RF Core ROM FW during RF Core initialization.
724
Device Configuration
SWCU117C – February 2015 – Revised September 2015
Copyright © 2015, Texas Instruments Incorporated