GPRAM
ENABLED
SPLIT
Reset
OFF
Invalidating
Invalidating
VIMS Configurations
7.1
VIMS Configurations
7.1.1 VIMS Modes
The VIMS cache RAM block and the Cache block can operate in the following modes:
•
GPRAM
•
CACHE
•
OFF
The current mode is shown in the VIMS:STAT.* register, and mode switching is controlled through the
VIMS:CTL.MODE register. The mode transitions are shown in
. Lines in black are software
initiated changes through the VIMS:CTL.MODE register. Lines in brown are hardware initiated changes.
The
invalidating
state is a transition state controlled by hardware. Invalidation clears the entire content of
the RAM block and takes 1029 clock periods to perform.
Figure 7-2. VIMS Mode Switching Flowchart
Once a mode change is initiated, shown in the VIMS:STATUS.MODE_CHANGING register, the mode
change must complete before another mode change can be initiated. The VIMS:CTL.MODE register is
blocked for updates during a mode change.
534
Versatile Instruction Memory System (VIMS)
SWCU117C – February 2015 – Revised September 2015
Copyright © 2015, Texas Instruments Incorporated