WCLK
BCLK
A
Dx
n-1
n-2
n-3
2
1
0
n-1
n-2
n-3
Channel 0 (left)
Channel 1 (right)
WCLK period = 1/F
S
2
1
0
n-1
LSB
LSB
MSB
MSB
WCLK
BCLK
ADx
MSB
MSB
LSB
LSB
Right channel
Left channel
WCLK period = 1/F
S
n-1
n-2
n-3
0
n-1
n-2
n-3
2
1
0
2
1
0
Serial Interface Formats
Figure 22-6. RJF Interface Format
22.6.4 DSP
shpws the DSP interface format. DSP is a single-phase format,
I2S:AIFFMTCFG.DUAL_PHASE = 0, where WCLK is high for one BCLK period, followed by each audio
channel back-to-back. Data is sampled on the falling edge of BCLK and updated on the rising edge of
BCLK; this is configured by setting I2S:AIFFMTCFG.SMPL_EDGE = 0.
There is an optional IDLE period at the end of the clock phase between the last data channel and the next
WCLK period; logical 0 is output during this period. The number of BCLK cycles in the phase must be
equal to or higher than the word length, as specified in the I2S:AIFFMTCFG.WORD_LEN register, times
the number of specified channels (determined by the most significant 1 in all the I2S:AIFWMASKn
registers combined).
When sample words are back-to-back, LSB of the previous sample are output in the DATA DELAY cycle.
Figure 22-7. DSP Interface Format (Showing First Two of Eight Possible Channels)
1433
SWCU117C – February 2015 – Revised September 2015
Integrated Interchip Sound (I2S) Module
Copyright © 2015, Texas Instruments Incorporated