Interrupts and Events Registers
4.7.2.76 UDMACH14BSEL Register (Offset = 574h) [reset = 1h]
UDMACH14BSEL is shown in
and described in
.
Output Selection for DMA Channel 14 REQ
Figure 4-85. UDMACH14BSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
EV
R-0h
R/W-1h
Table 4-90. UDMACH14BSEL Register Field Descriptions
Bit
Field
Type
Reset
Description
31-7
RESERVED
R
0h
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
361
SWCU117C – February 2015 – Revised September 2015
Interrupts and Events
Copyright © 2015, Texas Instruments Incorporated