PRCM Registers
6.2.4.5
CLKLOADCTL Register (Offset = 28h) [reset = 2h]
CLKLOADCTL is shown in
and described in
Clock Load Control
Figure 6-44. CLKLOADCTL Register
31
30
29
28
27
26
25
24
RESERVED
R-0h
23
22
21
20
19
18
17
16
RESERVED
R-0h
15
14
13
12
11
10
9
8
RESERVED
R-0h
7
6
5
4
3
2
1
0
RESERVED
LOAD_DONE
LOAD
R-0h
R-1h
W-0h
Table 6-49. CLKLOADCTL Register Field Descriptions
Bit
Field
Type
Reset
Description
31-2
RESERVED
R
0h
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
1
LOAD_DONE
R
1h
Status of LOAD.
Will be cleared to 0 when any of the registers requiring a LOAD is
written to, and be set to 1 when a LOAD is done.
Note that writing no change to a register will result in the
LOAD_DONE being cleared.
0 : One or more registers have been write accessed after last LOAD
1 : No registers are write accessed after last LOAD
479
SWCU117C – February 2015 – Revised September 2015
Power, Reset, and Clock Management
Copyright © 2015, Texas Instruments Incorporated