I
2
C Registers
21.5.1.16 MMIS Register (Offset = 818h) [reset = 0h]
MMIS is shown in
and described in
.
Master Masked Interrupt Status
This register show which interrupt is active (based on result from MRIS and MIMR).
Figure 21-29. MMIS Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESERVED
R-0h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESERVED
MIS
R-0h
R-0h
Table 21-18. MMIS Register Field Descriptions
Bit
Field
Type
Reset
Description
31-1
RESERVED
R
0h
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
0
MIS
R
0h
Masked interrupt status
0: An interrupt has not occurred or is masked.
1: A master interrupt is pending.
This bit is cleared by writing 1 to the MICR.IC bit .
1425
SWCU117C – February 2015 – Revised September 2015
Inter-Integrated Circuit (I
2
C) Interface
Copyright © 2015, Texas Instruments Incorporated