PRCM Registers
6.2.1.7
ANABYPASSVAL1 Register (Offset = 18h) [reset = 0h]
ANABYPASSVAL1 is shown in
and described in
.
Analog Bypass Values 1
Figure 6-13. ANABYPASSVAL1 Register
31
30
29
28
27
26
25
24
RESERVED
R/W-0h
23
22
21
20
19
18
17
16
RESERVED
XOSC_HF_ROW_Q12
R/W-0h
R/W-0h
15
14
13
12
11
10
9
8
XOSC_HF_COLUMN_Q12
R/W-0h
7
6
5
4
3
2
1
0
XOSC_HF_COLUMN_Q12
R/W-0h
Table 6-15. ANABYPASSVAL1 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-20
RESERVED
R/W
0h
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
19-16
XOSC_HF_ROW_Q12
R/W
0h
Internal. Only to be used through TI provided API.
15-0
XOSC_HF_COLUMN_Q1
R/W
0h
Internal. Only to be used through TI provided API.
2
439
SWCU117C – February 2015 – Revised September 2015
Power, Reset, and Clock Management
Copyright © 2015, Texas Instruments Incorporated