Cortex-M3 Processor Registers
2.7.5.3
ACPR Register (Offset = 10h) [reset = 0h]
ACPR is shown in
and described in
Async Clock Prescaler
This register scales the baud rate of the asynchronous output.
Figure 2-133. ACPR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
PRESCALER
R/W-0h
R/W-0h
Table 2-160. ACPR Register Field Descriptions
Bit
Field
Type
Reset
Description
31-13
RESERVED
R/W
0h
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
12-0
PRESCALER
R/W
0h
Divisor for input trace clock is (PRE 1).
210
SWCU117C – February 2015 – Revised September 2015
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