PRCM Registers
6.2.1.10 ADCDOUBLERNANOAMPCTL Register (Offset = 24h) [reset = 0h]
ADCDOUBLERNANOAMPCTL is shown in
and described in
ADC Doubler Nanoamp Control
Figure 6-16. ADCDOUBLERNANOAMPCTL Register
31
30
29
28
27
26
25
24
RESERVED
NANOAMP_BI
AS_ENABLE
R/W-0h
R/W-0h
23
22
21
20
19
18
17
16
SPARE23
RESERVED
R/W-0h
R/W-0h
15
14
13
12
11
10
9
8
RESERVED
R/W-0h
7
6
5
4
3
2
1
0
RESERVED
ADC_SH_MOD
ADC_SH_VBU
RESERVED
ADC_IREF_CTRL
E_EN
F_EN
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 6-18. ADCDOUBLERNANOAMPCTL Register Field Descriptions
Bit
Field
Type
Reset
Description
31-25
RESERVED
R/W
0h
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
24
NANOAMP_BIAS_ENABL R/W
0h
Internal. Only to be used through TI provided API.
E
23
SPARE23
R/W
0h
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior
22-6
RESERVED
R/W
0h
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
5
ADC_SH_MODE_EN
R/W
0h
Internal. Only to be used through TI provided API.
4
ADC_SH_VBUF_EN
R/W
0h
Internal. Only to be used through TI provided API.
3-2
RESERVED
R/W
0h
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
1-0
ADC_IREF_CTRL
R/W
0h
Internal. Only to be used through TI provided API.
442
Power, Reset, and Clock Management
SWCU117C – February 2015 – Revised September 2015
Copyright © 2015, Texas Instruments Incorporated