Cortex-M3 Processor Registers
2.7.5.6
FFCR Register (Offset = 304h) [reset = 102h]
FFCR is shown in
and described in
.
Formatter and Flush Control
When one of the two single wire output (SWO) modes is selected, ENFCONT enables the formatter to be
bypassed. If the formatter is bypassed, only the ITM/DWT trace source (ATDATA2) passes through. The
TPIU accepts and discards data that is presented on the ETM port (ATDATA1). This function is intended
to be used when it is necessary to connect a device containing an ETM to a trace capture device that is
only able to capture Serial Wire Output (SWO) data. Enabling or disabling the formatter causes
momentary data corruption.
Note: If the selected pin protocol register (SPPR.PROTOCOL) is set to 0x00 (TracePort mode), this
register always reads 0x102, because the formatter is automatically enabled. If one of the serial wire
modes is then selected, the register reverts to its previously programmed value.
Figure 2-136. FFCR Register
31
30
29
28
27
26
25
24
RESERVED
R/W-0h
23
22
21
20
19
18
17
16
RESERVED
R/W-0h
15
14
13
12
11
10
9
8
RESERVED
TRIGIN
R/W-0h
R/W-1h
7
6
5
4
3
2
1
0
RESERVED
ENFCONT
RESERVED
R/W-0h
R/W-1h
R/W-0h
Table 2-163. FFCR Register Field Descriptions
Bit
Field
Type
Reset
Description
31-9
RESERVED
R/W
0h
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
8
TRIGIN
R/W
1h
Indicates that triggers are inserted when a trigger pin is asserted.
7-2
RESERVED
R/W
0h
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
1
ENFCONT
R/W
1h
Enable continuous formatting:
0: Continuous formatting disabled
1: Continuous formatting enabled
0
RESERVED
R/W
0h
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
213
SWCU117C – February 2015 – Revised September 2015
Copyright © 2015, Texas Instruments Incorporated