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Cortex-M3 Processor Registers

2.7.4.54 ID_ISAR4 Register (Offset = D70h) [reset = 1310132h]

ID_ISAR4 is shown in

Figure 2-124

and described in

Table 2-150

ISA Feature 4
Information on the instruction set attributes register

Figure 2-124. ID_ISAR4 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

RESERVED

R-1310132h

Table 2-150. ID_ISAR4 Register Field Descriptions

Bit

Field

Type

Reset

Description

31-0

RESERVED

1310132h

Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.

197

SWCU117C – February 2015 – Revised September 2015

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Summary of Contents for SimpleLink CC2640

Page 1: ...CC13xx CC26xx SimpleLink Wireless MCU Technical Reference Manual Literature Number SWCU117C February 2015 Revised September 2015 ...

Page 2: ...Processor 28 2 1 The Cortex M3 Processor Introduction 29 2 2 Block Diagram 29 2 3 Overview 30 2 3 1 System level Interface 30 2 3 2 Integrated Configurable Debug 30 2 3 3 Trace Port Interface Unit 31 2 3 4 Cortex M3 System Component Details 31 2 4 Programming Model 31 2 4 1 Processor Mode and Privilege Levels for Software Execution 32 2 4 2 Stacks 32 2 4 3 Exceptions and Interrupts 32 2 4 4 Data T...

Page 3: ...bric 238 4 3 1 Introduction 238 4 3 2 Event Fabric Overview 239 4 4 AON Event Fabric 239 4 4 1 Common Input Event List 240 4 4 2 Event Subscribers 240 4 5 MCU Event Fabric 241 4 5 1 Common Input Event List 241 4 5 2 Event Subscribers 245 4 6 Memory Map 246 4 7 Interrupts and Events Registers 247 4 7 1 AON_EVENT Registers 247 4 7 2 EVENT Registers 271 5 JTAG Interface 390 5 1 Top Level Debug System...

Page 4: ... Memory Protection 540 7 4 2 Memory Programming 541 7 4 3 FLASH Memory Programming 541 7 5 Power Management Requirements 541 7 6 ROM Functions 543 7 7 SRAM 544 7 8 VIMS Registers 545 7 8 1 FLASH Registers 545 7 8 2 VIMS Registers 671 8 Bootloader 674 8 1 Bootloader Functionality 675 8 1 1 Bootloader Disabling 675 8 1 2 Bootloader Backdoor 675 8 2 Bootloader Interfaces 675 8 2 1 Packet Handling 676...

Page 5: ...1 1 AON_IOC Registers 881 11 11 2 GPIO Registers 887 11 11 3 IOC Registers 910 12 Micro Direct Memory Access µDMA 1039 12 1 μDMA Introduction 1040 12 2 Block Diagram 1041 12 3 Functional Description 1041 12 3 1 Channel Assignments 1042 12 3 2 Priority 1043 12 3 3 Arbitration Size 1043 12 3 4 Request Types 1043 12 3 5 Channel Configuration 1044 12 3 6 Transfer Modes 1046 12 3 7 Transfer Size and In...

Page 6: ...imer 1145 15 1 WDT Introduction 1146 15 2 WDT Functional Description 1146 15 3 WDT Initialization and Configuration 1147 15 4 Watchdog Timer Registers 1148 15 4 1 WDT Registers 1148 16 Random Number Generator 1158 16 1 Overview 1159 16 2 Block Diagram 1159 16 3 TRNG Software Reset 1160 16 4 Interrupt Requests 1160 16 5 TRNG Operation Description 1161 16 5 1 TRNG Shutdown 1161 16 5 2 TRNG Alarms 11...

Page 7: ...324 18 3 BATMON Registers 1325 18 3 1 AON_BATMON Registers 1325 19 Universal Asynchronous Receivers and Transmitters UARTS 1339 19 1 Universal Asynchronous Receiver Transmitter 1340 19 2 Block Diagram 1341 19 3 Signal Description 1341 19 4 Functional Description 1341 19 4 1 Transmit and Receive Logic 1342 19 4 2 Baud rate Generation 1342 19 4 3 Data Transmission 1342 19 4 4 Modem Handshake Support...

Page 8: ... 22 6 Serial Interface Formats 1432 22 6 1 I2S 1432 22 6 2 Left Justified LJF 1433 22 6 3 Right Justified RJF 1433 22 6 4 DSP 1434 22 7 Memory Interface 1435 22 7 1 Word Lengths 1435 22 7 2 Audio Channels 1435 22 7 3 Memory Buffers and Pointers 1436 22 8 Samplestamp Generator 1436 22 8 1 Counters and Registers 1437 22 8 2 Starting Input and Output Pins 1438 22 8 3 Samplestamp Capturing 1438 22 9 U...

Page 9: ... 23 6 Bluetooth Low Energy 1545 23 6 1 Bluetooth Low Energy Commands 1546 23 6 2 Interrupts 1554 23 6 3 Data Handling 1555 23 6 4 Radio Operation Command Descriptions 1556 23 6 5 Immediate Commands 1577 23 7 Proprietary Radio 1578 23 7 1 Packet Formats 1578 23 7 2 Commands 1578 23 7 3 Interrupts 1586 23 7 4 Data Handling 1587 23 7 5 Radio Operation Command Descriptions 1588 23 7 6 Immediate Comman...

Page 10: ...hanged VIMS registers 545 Changed register names in the Device Configuration chapter 689 Changed Device Configuration registers 689 Changed register names in the Cryptography chapter 802 Changed DMA Controller and Integration diagram 806 Changed values in the Performance Table for DMA Based Operations 816 Changed register names in the I O Control chapter 874 Changed IOC Overview section 874 Change...

Page 11: ...l registers 881 Updated image 1047 Changed µDMA registers 1056 Changed General purpose Timer registers 1092 Changed RTC registers 1131 Changed Watchdog registers 1148 Changed Random Number Generator registers 1166 Changed AUX Sensor Controller registers 1219 Changed BATMON registers 1325 Changed Functional Description section 1339 Changed UART feature list 1340 Changed Signals for UART table 1341 ...

Page 12: ...ormance characteristics of the device or modules These are gathered in the corresponding device data sheet Related Documents The following related documents are available on the CC26xx product pages at www ti com CC2620 Data Sheet and Errata CC2620 Technical Documents CC2630 Data Sheet and Errata CC2630 Technical Documents CC2640 Data Sheet and Errata CC2640 Technical Documents CC2650 Data Sheet a...

Page 13: ...rs Wiki Texas Instruments Embedded Processors Wiki TI BLE Wiki Texas Instruments Bluetooth Smart Wiki Established to assist developers using the many Embedded Processors from TI to get started help each other innovate and foster the growth of general knowledge about the hardware and software surrounding these devices Register Field and Bit Calls The naming convention applied for a call consists of...

Page 14: ...t chapters in this guide The CC26xx and CC13xx SimpleLink ultra low power wireless MCU platform system on chips SoCs are optimized for ultra low power while providing fast and capable MCU systems to enable short processing times and high integration The combination of an ARM Cortex M3 processing core of up to 48 MHz flash memory and a wide selection of peripherals makes the CC26xx and CC13xx devic...

Page 15: ...quipment HID Applications Home and Building Automation Lighting Control Alarm and Security Electronic Shelf Labeling Proximity Tags Medical Remote Controls Wireless Sensor Networks 1 2 Overview Figure 1 1 shows the building blocks of the CC26xx and CC13xx devices Figure 1 1 CC26xx and CC13xx Block Diagram 15 SWCU117C February 2015 Revised September 2015 Architectural Overview Submit Documentation ...

Page 16: ...d Advanced serial integration Universal asynchronous receiver and transmitter UART Inter integrated circuit I2C module Synchronous serial interface modules SSIs Audio interface I2S module System integration Direct memory access DMA controller Four 32 bit timers up to eight 16 bit with pulse width modulation PWM capability and synchronization 32 kHz real time clock RTC Watchdog timer On chip temper...

Page 17: ...sponse to interrupts The following are features of the processor core 32 bit ARM Cortex M3 architecture optimized for small footprint embedded applications Outstanding processing performance combined with fast interrupt handling Thumb 2 mixed 16 and 32 bit instruction set delivers the high performance expected of a 32 bit ARM core in a compact memory size usually associated with 8 and 16 bit devic...

Page 18: ...ions system handlers and can set CC26xx and CC13xx device interrupts Features of the NVIC are as follows Deterministic fast interrupt processing Always 12 cycles or just 6 cycles with tail chaining External nonmaskable interrupt NMI signal available for immediate execution of NMI handler for safety critical applications Dynamically reprioritizable interrupts Exceptional interrupt handling through ...

Page 19: ...iver functions low level protocol stack components and a serial bootloader SPI or UART 1 3 3 Radio The CC26xx and CC13xx device family provides a highly integrated low power 2 4 GHz radio transceiver with support for multiple modulations and packet formats The CC13xx provides similar functionality optimized for the sub 1 GHz bands and also allows limited operation in the 2 4 GHz band The radio sub...

Page 20: ...g timer is used to regain control when the system fails because of a software error or an external device fails to respond properly The watchdog timer can generate an interrupt or a reset when a predefined time out value is reached 1 3 5 2 Always on Domain The AON domain contains circuitry that is always enabled except for the shutdown mode where the digital supply is off This domain includes the ...

Page 21: ...lock sources for microcontroller system clock RC oscillator HSRCOSC On chip resource providing a 48 MHz frequency The 24 MHz crystal oscillator HSXOSC is a frequency accurate clock source from an external crystal connected across the X24M_P input and X24M_N output pins The internal 32 kHz RC oscillator is an on chip resource providing a 32 kHz frequency used during power saving modes and for RTC T...

Page 22: ... transfers using the µDMA controller Separate channels for TX and RX Receive single request asserted when data is in the FIFO burst request asserted at programmed FIFO level Transmit single request asserted when there is space in the FIFO burst request asserted at programmed FIFO level 1 3 8 2 I2 C The I2 C bus provides bidirectional data transfer through a 2 wire design a serial data line SDA and...

Page 23: ...ster or slave device As a slave device the SSI can be configured to disable its output which allows coupling of a master device with multiple slave devices The TX and RX paths are buffered with separate internal FIFOs The SSI also includes a programmable bit rate clock divider and prescaler to generate the output serial clock derived from the input clock of the SSI Bit rates are generated based on...

Page 24: ...directly from the main CPU The sensor controller engine CPU can read and monitor sensors or perform other tasks autonomously thereby reducing power consumption and offloading the main CPU The sensor controller is set up using a PC based configuration tool and typical use cases may be but not limited to the following Analog sensors using integrated ADC Digital sensors using GPIO with bit banged I2 ...

Page 25: ...m numbers for backoff calculations or security keys 1 3 12 cJTAG and JTAG The Joint Test Action Group JTAG port is an IEEE standard that defines a test access port TAP and boundary scan architecture for digital integrated circuits The JTAG port also provides a standardized serial interface for controlling the associated test logic The TAP Instruction Register IR and Data Registers DR can be used t...

Page 26: ... use on the CC26xx and CC13xx device family Figure 1 2 shows an overview of the supply system Figure 1 2 CC26xx and CC13xx Supply System 1 3 13 1 1 VDDS The battery voltage on the CC26xx and CC13xx device family is called VDDS supply This supply has the highest potential in the system and typically is the only one provided by the user 26 Architectural Overview SWCU117C February 2015 Revised Septem...

Page 27: ...ulators are powered up or down automatically by firmware when needed 1 3 13 2 DC DC Converter The on chip buck mode DC DC converter provides a simple way to reduce the power consumption of the device The DC DC converter is integrated into the supply system and handles bias and clocks automatically through the system controller The DC DC converter is controlled through the AON_SYSCTL PWRCTL registe...

Page 28: ...This chapter provides information on the CC26xx and CC13xx implementation of the Cortex M3 processor For technical details on the instruction set see the Cortex M3 M4F Instruction Set Technical User s Manual SPMU159 Topic Page 2 1 The Cortex M3 Processor Introduction 29 2 2 Block Diagram 29 2 3 Overview 30 2 4 Programming Model 31 2 5 Cortex M3 Core Registers 33 2 6 Instruction Set Summary 47 2 7 ...

Page 29: ...g with data matching for watchpoint generation DWT JTAG debug port FPB Migration from the ARM7 processor family for better performance and power efficiency Standard trace support ITM TPIU with asynchronous serial wire output SWO Optimized for single cycle flash memory use Ultra low power consumption with integrated sleep modes 48 MHz operation 2 2 Block Diagram Figure 2 1 shows the core processor ...

Page 30: ...ntire device to be rapidly powered down Figure 2 1 CPU Block Diagram 2 3 Overview 2 3 1 System level Interface The Cortex M3 processor provides multiple interfaces using AMBA technology to provide high speed low latency memory accesses The core supports unaligned data accesses and implements atomic bit manipulation that enables faster peripheral controls system spinlocks and thread safe Boolean da...

Page 31: ...m the ITM and an off chip trace port analyzer Figure 2 2 TPIU Block Diagram See CM3_TIPROP for more information 2 3 4 Cortex M3 System Component Details The Cortex M3 includes the following system components SysTick A 24 bit count down timer that can be used as a real time operating system RTOS tick timer or as a simple counter see Section 3 2 1 SysTick Nested Vectored Interrupt Controller An embe...

Page 32: ...ack and the process stack with a pointer for each held in independent registers see the SP register in Table 2 16 In thread mode the CONTROL register see Table 2 24 controls whether the processor uses the main stack or the process stack In handler mode the processor always uses the main stack Table 2 1 lists the options for processor operations Table 2 1 Summary of Processor Mode Privilege Level a...

Page 33: ... R13 www ti com Cortex M3 Core Registers 2 5 Cortex M3 Core Registers Figure 2 3 shows the Cortex M3 register set Table 2 2 lists the core registers The core registers are not memory mapped and are accessed by register name so the base address is N A not applicable and there is no offset Figure 2 3 Cortex M3 Register Set Note Banked version of SP 33 SWCU117C February 2015 Revised September 2015 Th...

Page 34: ...ister See Section 2 5 2 17 PRIMASK R W 0x0000 0000 Priority mask register See Section 2 5 2 18 FAULTMASK R W 0x0000 0000 Fault mask register See Section 2 5 2 19 BASEPRI R W 0x0000 0000 Base priority mask register See Section 2 5 2 20 CONTROL R W 0x0000 0000 Control register See Section 2 5 2 21 2 5 2 Core Register Descriptions This section lists and describes the Cortex M3 registers in the order ...

Page 35: ... 32 bit general purpose registers for data operations and can be accessed from either privileged or unprivileged mode Type R W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA Bits Field Name Description Type Reset 31 0 DATA Register data R W 2 5 2 4 Cortex General Purpose Register 3 R3 Table 2 6 Cortex General Purpose Register 3 R3 Address Offset Reset Ph...

Page 36: ... 32 bit general purpose registers for data operations and can be accessed from either privileged or unprivileged mode Type R W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA Bits Field Name Description Type Reset 31 0 DATA Register data R W 2 5 2 7 Cortex General Purpose Register 6 R6 Table 2 9 Cortex General Purpose Register 6 R6 Address Offset Reset Ph...

Page 37: ... 32 bit general purpose registers for data operations and can be accessed from either privileged or unprivileged mode Type R W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA Bits Field Name Description Type Reset 31 0 DATA Register data R W 2 5 2 10 Cortex General Purpose Register 9 R9 Table 2 12 Cortex General Purpose Register 9 R9 Address Offset Reset ...

Page 38: ...are 32 bit general purpose registers for data operations and can be accessed from either privileged or unprivileged mode Type R W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA Bits Field Name Description Type Reset 31 0 DATA Register data R W 2 5 2 13 Cortex General Purpose Register 12 R12 Table 2 15 Cortex General Purpose Register 12 R12 Address Offset...

Page 39: ... 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SP Bits Field Name Description Type Reset 31 0 SP This field is the address of the stack pointer R W 2 5 2 15 Link Register LR Table 2 17 Link Register LR Address Offset Reset 0xFFFF FFFF Physical Address Instance Description The Link Register LR is register R14 and it stores the return information for subroutines function calls and exceptions ...

Page 40: ...or unprivileged mode Type R W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PC Bits Field Name Description Type Reset 31 0 PC This field is the current program address R W 2 5 2 17 Program Status Register PSR Table 2 19 PSR Combinations Register Type Combination PSR R W 1 2 APSR EPSR and IPSR IEPSR RO EPSR and IPSR IAPSR R W APSR and IPSR EAPSR R W APSR and ...

Page 41: ...sters using the register name as an argument to the MSR or MRS instructions For example all of the registers can be read using PSR with the MRS instruction or APSR only can be written to using APSR with the MSR instruction Table 2 20 shows the possible register combinations for the PSR See the MRS and MSR instruction descriptions in the Cortex M3 M4F Instruction Set Technical User s Manual SPMU159...

Page 42: ...value on an exception entry or reset Attempting to execute instructions when this bit is clear results in a fault or lockup For more information see Section 4 2 4 Lockup The value of this bit is meaningful only when accessing PSR or EPSR 23 16 RESERVED Reserved RO 0x00 15 10 ICI IT EPSR ICI IT status RO 0x0 These bits along with bits 26 25 contain the ICI field for an interrupted load multiple or ...

Page 43: ...l 0x0C Reserved for debug 0x0D Reserved 0x0E PendSV 0x0F SysTick 0x10 Interrupt vector 0 0x11 Interrupt vector 1 0x31 Interrupt vector 33 0x32 0x7F Reserved For more information see Section 4 1 2 Exception Types The value of this field is meaningful only when accessing PSR or IPSR 43 SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorp...

Page 44: ...of the PRIMASK register For more information on these instructions see the Cortex M3 M4F Instruction Set Technical User s Manual SPMU159 For more information on exception priority levels see Section 4 1 2 Exception Types Type R W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED PRIMASK Bits Field Name Description Type Reset 31 1 RESERVED Software must ...

Page 45: ...FAULTMASK register See the Cortex M3 M4F Instruction Set Technical User s Manual SPMU159 for more information on these instructions For more information on exception priority levels see Section 4 1 2 Exception Types Type R W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED FAULTMASK Bits Field Name Description Type Reset 31 1 RESERVED Reserved RO 0x000...

Page 46: ...RVED Bits Field Name Description Type Reset 31 8 RESERVED Reserved RO 0x0000 00 7 5 BASEPRI Base Priority R W 0x0 Any exception that has a programmable priority level with the same or lower priority as the value of this field is masked The PRIMASK register can be used to mask all exceptions with programmable priority levels Higher priority exceptions have lower priority levels Value Description 0x...

Page 47: ...ISB instruction executes use the new stack pointer See the Cortex M3 M4F Instruction Set Technical User s Manual SPMU159 Type R W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED ASP TMPL Bits Field Name Description Type Reset 31 2 RESERVED Reserved RO 0x0000 000 1 ASP Active Stack Pointer R W 0 Value Description 1 PSP is the current stack pointer 0 MS...

Page 48: ...te disable CPSID I interrupts Change processor state enable CPSIE I interrupts DMB Data memory barrier DSB Data synchronization barrier EOR EORS Rd Rn Op2 Exclusive OR N Z C ISB Instruction synchronization barrier IT If Then condition block LDM Rn reglist Load multiple registers increment after Load multiple registers decrement LDMDB LDMEA Rn reglist before LDMFD LDMIA Rn reglist Load multiple reg...

Page 49: ...N Z C V SBC SBCS Rd Rn Op2 Subtract with carry N Z C V SBFX Rd Rn lsb width Signed bit field extract SDIV Rd Rn Rm Signed divide SEV Send event Signed multiply with accumulate 32 SMLAL RdLo RdHi Rn Rm 32 64 64 bit result SMULL RdLo RdHi Rn Rm Signed multiply 32 32 64 bit result SSAT Rd n Rm shift s Signed saturate Q STM Rn reglist Store multiple registers increment after Store multiple registers d...

Page 50: ...t UDIV Rd Rn Rm Unsigned divide Unsigned multiply with accumulate 32 UMLAL RdLo RdHi Rn Rm 32 32 32 64 bit result UMULL RdLo RdHi Rn Rm Unsigned multiply 32 2 64 bit result USAT Rd n Rm shift s Unsigned saturate Q UXTB Rd Rm ROR n Zero extend a byte UXTH Rd Rm ROR n Zero extend a halfword USAT Rd n Rm shift s Unsigned saturate Q UXTB Rd Rm ROR n Zero extend a byte UXTH Rd Rm ROR n Zero extend a ha...

Page 51: ... SLEEPCNT Sleep Count Section 2 7 1 5 14h LSUCNT LSU Count Section 2 7 1 6 18h FOLDCNT Fold Count Section 2 7 1 7 1Ch PCSR Program Counter Sample Section 2 7 1 8 20h COMP0 Comparator 0 Section 2 7 1 9 24h MASK0 Mask 0 Section 2 7 1 10 28h FUNCTION0 Function 0 Section 2 7 1 11 30h COMP1 Comparator 1 Section 2 7 1 12 34h MASK1 Mask 1 Section 2 7 1 13 38h FUNCTION1 Function 1 Section 2 7 1 14 40h COM...

Page 52: ...t Emits an event when the POSTCNT counter triggers it See CYCTAP and POSTPRESET for details This event is only emitted if PCSAMPLEENA is disabled PCSAMPLEENA overrides the setting of this bit 0 Cycle count events disabled 1 Cycle count events enabled 21 FOLDEVTENA R W 0h Enables Folded instruction count event Emits an event when FOLDCNT overflows every 256 cycles of folded instructions A folded in...

Page 53: ...2h Tap at bit 26 of CYCCNT 3h Tap at bit 28 of CYCCNT 9 CYCTAP R W 0h Selects a tap on CYCCNT These are spaced at bits 6 and 10 When the selected bit in CYCCNT changes from 0 to 1 or 1 to 0 it emits into the POSTCNT post scalar counter That counter then counts down On a bit change when post scalar is 0 it triggers an event for PC sampling or cycle count event see details in CYCEVTENA 0h Selects bi...

Page 54: ... use the counter to measure elapsed execution time By subtracting a start and an end time an application can measure time between in core clocks other than when Halted in debug This is valid to 232 core clock cycles for example almost 89 5 seconds at 48MHz Figure 2 5 CYCCNT Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CYCCNT R W 0h Table 2 28 CYCCN...

Page 55: ...ption 31 8 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 7 0 CPICNT R W X Current CPI counter value Increments on the additional cycles the first cycle is not counted required to execute all instructions except those recorded by LSUCNT This counter also increments on all instruction fetch stalls If CT...

Page 56: ...ld Descriptions Bit Field Type Reset Description 31 8 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 7 0 EXCCNT R W X Current interrupt overhead counter value Counts the total cycles spent in interrupt processing for example entry stacking return unstacking pre emption An event is emitted on counter ov...

Page 57: ...tware must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 7 0 SLEEPCNT R W X Sleep counter Counts the number of cycles during which the processor is sleeping An event is emitted on counter overflow every 256 cycles This counter initializes to 0 when it is enabled using CTRL SLEEPEVTENA Note that the sleep counter is clocked using C...

Page 58: ... not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 7 0 LSUCNT R W X LSU counter This counts the total number of cycles that the processor is processing an LSU operation The initial execution cost of the instruction is not counted For example an LDR that takes two cycles to complete increments this counter one cycle Equivalently an LDR...

Page 59: ...7 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED FOLDCNT R W 0h R W X Table 2 33 FOLDCNT Register Field Descriptions Bit Field Type Reset Description 31 8 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 7 0 FOLDCNT R W X This counts the total number folded instructions This counter initializes to 0 w...

Page 60: ...d is the instruction address of a recently executed instruction If the core is in debug state the value returned is 0xFFFFFFFF Figure 2 11 PCSR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EIASAMPLE R X Table 2 34 PCSR Register Field Descriptions Bit Field Type Reset Description 31 0 EIASAMPLE R X Execution instruction address sample or 0xFFFFFFFF ...

Page 61: ...7 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 COMP R W X Table 2 35 COMP0 Register Field Descriptions Bit Field Type Reset Description 31 0 COMP R W X Reference value to compare against PC or the data address as given by FUNCTION0 Comparator 0 can also compare against the value of the PC Sampler Counter CYCCNT 61 SWCU117C February 2015 Revised September 2015 Submit Docum...

Page 62: ...1 4 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 3 0 MASK R W X Mask on data address when matching against COMP0 This is the size of the ignore mask That is DWT matching is performed as ADDR ANDed with 0xFFFF left bit shifted by MASK COMP0 However the actual comparison is slightly more complex to ena...

Page 63: ...alue than the reset value may result in undefined behavior 24 MATCHED R W 0h This bit is set when the comparator matches and indicates that the operation defined by FUNCTION has occurred since this bit was last read This bit is cleared on read 23 8 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 7 CYCMATC...

Page 64: ...ad or write 0xC EMITRANGE 0 sample data for read transfers EMITRANGE 1 sample Daddr lower 16 bits for read transfers 0xD EMITRANGE 0 sample data for write transfers EMITRANGE 1 sample Daddr lower 16 bits for write transfers 0xE EMITRANGE 0 sample PC data for read transfers EMITRANGE 1 sample Daddr lower 16 bits data for read transfers 0xF EMITRANGE 0 sample PC data for write transfers EMITRANGE 1 ...

Page 65: ...3 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 COMP R W X Table 2 38 COMP1 Register Field Descriptions Bit Field Type Reset Description 31 0 COMP R W X Reference value to compare against PC or the data address as given by FUNCTION1 Comparator 1 can also compare data values So this register can contain reference values for data matching 65 SWCU117C February 2015 Revised September 2015...

Page 66: ...1 4 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 3 0 MASK R W X Mask on data address when matching against COMP1 This is the size of the ignore mask That is DWT matching is performed as ADDR ANDed with 0xFFFF left bit shifted by MASK COMP1 However the actual comparison is slightly more complex to ena...

Page 67: ...curred since this bit was last read This bit is cleared on read 23 20 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 19 16 DATAVADDR1 R W 0h Identity of a second linked address comparator for data value matching when DATAVMATCH 1 and LNK1ENA 1 15 12 DATAVADDR0 R W 0h Identity of a linked address comparat...

Page 68: ...EMITRANGE 0 sample data for write transfers EMITRANGE 1 sample Daddr lower 16 bits for write transfers 0xE EMITRANGE 0 sample PC data for read transfers EMITRANGE 1 sample Daddr lower 16 bits data for read transfers 0xF EMITRANGE 0 sample PC data for write transfers EMITRANGE 1 sample Daddr lower 16 bits data for write transfers Note 1 If the ETM is not fitted then ETM trigger is not possible Note...

Page 69: ... Figure 2 18 COMP2 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 COMP R W X Table 2 41 COMP2 Register Field Descriptions Bit Field Type Reset Description 31 0 COMP R W X Reference value to compare against PC or the data address as given by FUNCTION2 69 SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Texas I...

Page 70: ...1 4 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 3 0 MASK R W X Mask on data address when matching against COMP2 This is the size of the ignore mask That is DWT matching is performed as ADDR ANDed with 0xFFFF left bit shifted by MASK COMP2 However the actual comparison is slightly more complex to ena...

Page 71: ...st not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 24 MATCHED R W 0h This bit is set when the comparator matches and indicates that the operation defined by FUNCTION has occurred since this bit was last read This bit is cleared on read 23 6 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than ...

Page 72: ...ad or write 0xC EMITRANGE 0 sample data for read transfers EMITRANGE 1 sample Daddr lower 16 bits for read transfers 0xD EMITRANGE 0 sample data for write transfers EMITRANGE 1 sample Daddr lower 16 bits for write transfers 0xE EMITRANGE 0 sample PC data for read transfers EMITRANGE 1 sample Daddr lower 16 bits data for read transfers 0xF EMITRANGE 0 sample PC data for write transfers EMITRANGE 1 ...

Page 73: ... Figure 2 21 COMP3 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 COMP R W X Table 2 44 COMP3 Register Field Descriptions Bit Field Type Reset Description 31 0 COMP R W X Reference value to compare against PC or the data address as given by FUNCTION3 73 SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Texas I...

Page 74: ...1 4 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 3 0 MASK R W X Mask on data address when matching against COMP3 This is the size of the ignore mask That is DWT matching is performed as ADDR ANDed with 0xFFFF left bit shifted by MASK COMP3 However the actual comparison is slightly more complex to ena...

Page 75: ...must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 24 MATCHED R W 0h This bit is set when the comparator matches and indicates that the operation defined by FUNCTION has occurred since this bit was last read This bit is cleared on read 23 6 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value t...

Page 76: ...ad or write 0xC EMITRANGE 0 sample data for read transfers EMITRANGE 1 sample Daddr lower 16 bits for read transfers 0xD EMITRANGE 0 sample data for write transfers EMITRANGE 1 sample Daddr lower 16 bits for write transfers 0xE EMITRANGE 0 sample PC data for read transfers EMITRANGE 1 sample Daddr lower 16 bits data for read transfers 0xF EMITRANGE 0 sample PC data for write transfers EMITRANGE 1 ...

Page 77: ...ister Name Section 0h CTRL Control Section 2 7 2 1 4h REMAP Remap Section 2 7 2 2 8h COMP0 Comparator 0 Section 2 7 2 3 Ch COMP1 Comparator 1 Section 2 7 2 4 10h COMP2 Comparator 2 Section 2 7 2 5 14h COMP3 Comparator 3 Section 2 7 2 6 18h COMP4 Comparator 4 Section 2 7 2 7 1Ch COMP5 Comparator 5 Section 2 7 2 8 20h COMP6 Comparator 6 Section 2 7 2 9 24h COMP7 Comparator 7 Section 2 7 2 10 77 SWCU...

Page 78: ...ators sixteen comparators per bank Where less than sixteen code comparators are provided the bank count is zero and the number present indicated by NUM_CODE1 This read only field contains 3 b000 to indicate 0 banks for Cortex M processor 11 8 NUM_LIT R 2h Number of literal slots field 0x0 No literal slots 0x2 Two literal slots 7 4 NUM_CODE1 R 6h Number of code slots field 0x0 No code slots 0x2 Two...

Page 79: ...to be 8 word aligned with one word allocated to each of the eight FPB comparators Figure 2 25 REMAP Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESERVED REMAP R 1h R W X 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 REMAP RESERVED R W X R 0h Table 2 49 REMAP Register Field Descriptions Bit Field Type Reset Description 31 29 RESERVED R 1h This field always reads 3 b001 Writing to this field is...

Page 80: ...See REMAP REMAP 0x1 Set BKPT on lower halfword upper is unaffected 0x2 Set BKPT on upper halfword lower is unaffected 0x3 Set BKPT on both lower and upper halfwords 29 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 28 2 COMP R W 0h Comparison address 1 RESERVED R W 0h Software must not rely on the valu...

Page 81: ...See REMAP REMAP 0x1 Set BKPT on lower halfword upper is unaffected 0x2 Set BKPT on upper halfword lower is unaffected 0x3 Set BKPT on both lower and upper halfwords 29 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 28 2 COMP R W 0h Comparison address 1 RESERVED R W 0h Software must not rely on the valu...

Page 82: ...See REMAP REMAP 0x1 Set BKPT on lower halfword upper is unaffected 0x2 Set BKPT on upper halfword lower is unaffected 0x3 Set BKPT on both lower and upper halfwords 29 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 28 2 COMP R W 0h Comparison address 1 RESERVED R W 0h Software must not rely on the valu...

Page 83: ...See REMAP REMAP 0x1 Set BKPT on lower halfword upper is unaffected 0x2 Set BKPT on upper halfword lower is unaffected 0x3 Set BKPT on both lower and upper halfwords 29 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 28 2 COMP R W 0h Comparison address 1 RESERVED R W 0h Software must not rely on the valu...

Page 84: ...See REMAP REMAP 0x1 Set BKPT on lower halfword upper is unaffected 0x2 Set BKPT on upper halfword lower is unaffected 0x3 Set BKPT on both lower and upper halfwords 29 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 28 2 COMP R W 0h Comparison address 1 RESERVED R W 0h Software must not rely on the valu...

Page 85: ...See REMAP REMAP 0x1 Set BKPT on lower halfword upper is unaffected 0x2 Set BKPT on upper halfword lower is unaffected 0x3 Set BKPT on both lower and upper halfwords 29 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 28 2 COMP R W 0h Comparison address 1 RESERVED R W 0h Software must not rely on the valu...

Page 86: ...x0 Remap to remap address See REMAP REMAP 0x1 Set BKPT on lower halfword upper is unaffected 0x2 Set BKPT on upper halfword lower is unaffected 0x3 Set BKPT on both lower and upper halfwords 29 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 28 2 COMP R W 0h Comparison address 1 RESERVED R W 0h Software...

Page 87: ...x0 Remap to remap address See REMAP REMAP 0x1 Set BKPT on lower halfword upper is unaffected 0x2 Set BKPT on upper halfword lower is unaffected 0x3 Set BKPT on both lower and upper halfwords 29 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 28 2 COMP R W 0h Comparison address 1 RESERVED R W 0h Software...

Page 88: ... 38h STIM14 Stimulus Port 14 Section 2 7 3 15 3Ch STIM15 Stimulus Port 15 Section 2 7 3 16 40h STIM16 Stimulus Port 16 Section 2 7 3 17 44h STIM17 Stimulus Port 17 Section 2 7 3 18 48h STIM18 Stimulus Port 18 Section 2 7 3 19 4Ch STIM19 Stimulus Port 19 Section 2 7 3 20 50h STIM20 Stimulus Port 20 Section 2 7 3 21 54h STIM21 Stimulus Port 21 Section 2 7 3 22 58h STIM22 Stimulus Port 22 Section 2 7...

Page 89: ...pe Reset Description 31 0 STIM0 R W X A write to this location causes data to be written into the FIFO if TER STIMENA0 is set Reading from the stimulus port returns the FIFO status in bit 0 0 full 1 not full The polled FIFO interface does not provide an atomic read modify write so it s users responsibility to ensure exclusive read modify write if this ITM port is used concurrently by interrupts or...

Page 90: ...pe Reset Description 31 0 STIM1 R W X A write to this location causes data to be written into the FIFO if TER STIMENA1 is set Reading from the stimulus port returns the FIFO status in bit 0 0 full 1 not full The polled FIFO interface does not provide an atomic read modify write so it s users responsibility to ensure exclusive read modify write if this ITM port is used concurrently by interrupts or...

Page 91: ...pe Reset Description 31 0 STIM2 R W X A write to this location causes data to be written into the FIFO if TER STIMENA2 is set Reading from the stimulus port returns the FIFO status in bit 0 0 full 1 not full The polled FIFO interface does not provide an atomic read modify write so it s users responsibility to ensure exclusive read modify write if this ITM port is used concurrently by interrupts or...

Page 92: ...pe Reset Description 31 0 STIM3 R W X A write to this location causes data to be written into the FIFO if TER STIMENA3 is set Reading from the stimulus port returns the FIFO status in bit 0 0 full 1 not full The polled FIFO interface does not provide an atomic read modify write so it s users responsibility to ensure exclusive read modify write if this ITM port is used concurrently by interrupts or...

Page 93: ...ype Reset Description 31 0 STIM4 R W X A write to this location causes data to be written into the FIFO if TER STIMENA4 is set Reading from the stimulus port returns the FIFO status in bit 0 0 full 1 not full The polled FIFO interface does not provide an atomic read modify write so it s users responsibility to ensure exclusive read modify write if this ITM port is used concurrently by interrupts o...

Page 94: ...ype Reset Description 31 0 STIM5 R W X A write to this location causes data to be written into the FIFO if TER STIMENA5 is set Reading from the stimulus port returns the FIFO status in bit 0 0 full 1 not full The polled FIFO interface does not provide an atomic read modify write so it s users responsibility to ensure exclusive read modify write if this ITM port is used concurrently by interrupts o...

Page 95: ...ype Reset Description 31 0 STIM6 R W X A write to this location causes data to be written into the FIFO if TER STIMENA6 is set Reading from the stimulus port returns the FIFO status in bit 0 0 full 1 not full The polled FIFO interface does not provide an atomic read modify write so it s users responsibility to ensure exclusive read modify write if this ITM port is used concurrently by interrupts o...

Page 96: ...ype Reset Description 31 0 STIM7 R W X A write to this location causes data to be written into the FIFO if TER STIMENA7 is set Reading from the stimulus port returns the FIFO status in bit 0 0 full 1 not full The polled FIFO interface does not provide an atomic read modify write so it s users responsibility to ensure exclusive read modify write if this ITM port is used concurrently by interrupts o...

Page 97: ...ype Reset Description 31 0 STIM8 R W X A write to this location causes data to be written into the FIFO if TER STIMENA8 is set Reading from the stimulus port returns the FIFO status in bit 0 0 full 1 not full The polled FIFO interface does not provide an atomic read modify write so it s users responsibility to ensure exclusive read modify write if this ITM port is used concurrently by interrupts o...

Page 98: ...ype Reset Description 31 0 STIM9 R W X A write to this location causes data to be written into the FIFO if TER STIMENA9 is set Reading from the stimulus port returns the FIFO status in bit 0 0 full 1 not full The polled FIFO interface does not provide an atomic read modify write so it s users responsibility to ensure exclusive read modify write if this ITM port is used concurrently by interrupts o...

Page 99: ... Type Reset Description 31 0 STIM10 R W X A write to this location causes data to be written into the FIFO if TER STIMENA10 is set Reading from the stimulus port returns the FIFO status in bit 0 0 full 1 not full The polled FIFO interface does not provide an atomic read modify write so it s users responsibility to ensure exclusive read modify write if this ITM port is used concurrently by interrup...

Page 100: ... Type Reset Description 31 0 STIM11 R W X A write to this location causes data to be written into the FIFO if TER STIMENA11 is set Reading from the stimulus port returns the FIFO status in bit 0 0 full 1 not full The polled FIFO interface does not provide an atomic read modify write so it s users responsibility to ensure exclusive read modify write if this ITM port is used concurrently by interrup...

Page 101: ... Type Reset Description 31 0 STIM12 R W X A write to this location causes data to be written into the FIFO if TER STIMENA12 is set Reading from the stimulus port returns the FIFO status in bit 0 0 full 1 not full The polled FIFO interface does not provide an atomic read modify write so it s users responsibility to ensure exclusive read modify write if this ITM port is used concurrently by interrup...

Page 102: ... Type Reset Description 31 0 STIM13 R W X A write to this location causes data to be written into the FIFO if TER STIMENA13 is set Reading from the stimulus port returns the FIFO status in bit 0 0 full 1 not full The polled FIFO interface does not provide an atomic read modify write so it s users responsibility to ensure exclusive read modify write if this ITM port is used concurrently by interrup...

Page 103: ... Type Reset Description 31 0 STIM14 R W X A write to this location causes data to be written into the FIFO if TER STIMENA14 is set Reading from the stimulus port returns the FIFO status in bit 0 0 full 1 not full The polled FIFO interface does not provide an atomic read modify write so it s users responsibility to ensure exclusive read modify write if this ITM port is used concurrently by interrup...

Page 104: ... Type Reset Description 31 0 STIM15 R W X A write to this location causes data to be written into the FIFO if TER STIMENA15 is set Reading from the stimulus port returns the FIFO status in bit 0 0 full 1 not full The polled FIFO interface does not provide an atomic read modify write so it s users responsibility to ensure exclusive read modify write if this ITM port is used concurrently by interrup...

Page 105: ... Type Reset Description 31 0 STIM16 R W X A write to this location causes data to be written into the FIFO if TER STIMENA16 is set Reading from the stimulus port returns the FIFO status in bit 0 0 full 1 not full The polled FIFO interface does not provide an atomic read modify write so it s users responsibility to ensure exclusive read modify write if this ITM port is used concurrently by interrup...

Page 106: ... Type Reset Description 31 0 STIM17 R W X A write to this location causes data to be written into the FIFO if TER STIMENA17 is set Reading from the stimulus port returns the FIFO status in bit 0 0 full 1 not full The polled FIFO interface does not provide an atomic read modify write so it s users responsibility to ensure exclusive read modify write if this ITM port is used concurrently by interrup...

Page 107: ... Type Reset Description 31 0 STIM18 R W X A write to this location causes data to be written into the FIFO if TER STIMENA18 is set Reading from the stimulus port returns the FIFO status in bit 0 0 full 1 not full The polled FIFO interface does not provide an atomic read modify write so it s users responsibility to ensure exclusive read modify write if this ITM port is used concurrently by interrup...

Page 108: ... Type Reset Description 31 0 STIM19 R W X A write to this location causes data to be written into the FIFO if TER STIMENA19 is set Reading from the stimulus port returns the FIFO status in bit 0 0 full 1 not full The polled FIFO interface does not provide an atomic read modify write so it s users responsibility to ensure exclusive read modify write if this ITM port is used concurrently by interrup...

Page 109: ... Type Reset Description 31 0 STIM20 R W X A write to this location causes data to be written into the FIFO if TER STIMENA20 is set Reading from the stimulus port returns the FIFO status in bit 0 0 full 1 not full The polled FIFO interface does not provide an atomic read modify write so it s users responsibility to ensure exclusive read modify write if this ITM port is used concurrently by interrup...

Page 110: ... Type Reset Description 31 0 STIM21 R W X A write to this location causes data to be written into the FIFO if TER STIMENA21 is set Reading from the stimulus port returns the FIFO status in bit 0 0 full 1 not full The polled FIFO interface does not provide an atomic read modify write so it s users responsibility to ensure exclusive read modify write if this ITM port is used concurrently by interrup...

Page 111: ... Type Reset Description 31 0 STIM22 R W X A write to this location causes data to be written into the FIFO if TER STIMENA22 is set Reading from the stimulus port returns the FIFO status in bit 0 0 full 1 not full The polled FIFO interface does not provide an atomic read modify write so it s users responsibility to ensure exclusive read modify write if this ITM port is used concurrently by interrup...

Page 112: ... Type Reset Description 31 0 STIM23 R W X A write to this location causes data to be written into the FIFO if TER STIMENA23 is set Reading from the stimulus port returns the FIFO status in bit 0 0 full 1 not full The polled FIFO interface does not provide an atomic read modify write so it s users responsibility to ensure exclusive read modify write if this ITM port is used concurrently by interrup...

Page 113: ... Type Reset Description 31 0 STIM24 R W X A write to this location causes data to be written into the FIFO if TER STIMENA24 is set Reading from the stimulus port returns the FIFO status in bit 0 0 full 1 not full The polled FIFO interface does not provide an atomic read modify write so it s users responsibility to ensure exclusive read modify write if this ITM port is used concurrently by interrup...

Page 114: ... Type Reset Description 31 0 STIM25 R W X A write to this location causes data to be written into the FIFO if TER STIMENA25 is set Reading from the stimulus port returns the FIFO status in bit 0 0 full 1 not full The polled FIFO interface does not provide an atomic read modify write so it s users responsibility to ensure exclusive read modify write if this ITM port is used concurrently by interrup...

Page 115: ... Type Reset Description 31 0 STIM26 R W X A write to this location causes data to be written into the FIFO if TER STIMENA26 is set Reading from the stimulus port returns the FIFO status in bit 0 0 full 1 not full The polled FIFO interface does not provide an atomic read modify write so it s users responsibility to ensure exclusive read modify write if this ITM port is used concurrently by interrup...

Page 116: ... Type Reset Description 31 0 STIM27 R W X A write to this location causes data to be written into the FIFO if TER STIMENA27 is set Reading from the stimulus port returns the FIFO status in bit 0 0 full 1 not full The polled FIFO interface does not provide an atomic read modify write so it s users responsibility to ensure exclusive read modify write if this ITM port is used concurrently by interrup...

Page 117: ... Type Reset Description 31 0 STIM28 R W X A write to this location causes data to be written into the FIFO if TER STIMENA28 is set Reading from the stimulus port returns the FIFO status in bit 0 0 full 1 not full The polled FIFO interface does not provide an atomic read modify write so it s users responsibility to ensure exclusive read modify write if this ITM port is used concurrently by interrup...

Page 118: ... Type Reset Description 31 0 STIM29 R W X A write to this location causes data to be written into the FIFO if TER STIMENA29 is set Reading from the stimulus port returns the FIFO status in bit 0 0 full 1 not full The polled FIFO interface does not provide an atomic read modify write so it s users responsibility to ensure exclusive read modify write if this ITM port is used concurrently by interrup...

Page 119: ... Type Reset Description 31 0 STIM30 R W X A write to this location causes data to be written into the FIFO if TER STIMENA30 is set Reading from the stimulus port returns the FIFO status in bit 0 0 full 1 not full The polled FIFO interface does not provide an atomic read modify write so it s users responsibility to ensure exclusive read modify write if this ITM port is used concurrently by interrup...

Page 120: ... Type Reset Description 31 0 STIM31 R W X A write to this location causes data to be written into the FIFO if TER STIMENA31 is set Reading from the stimulus port returns the FIFO status in bit 0 0 full 1 not full The polled FIFO interface does not provide an atomic read modify write so it s users responsibility to ensure exclusive read modify write if this ITM port is used concurrently by interrup...

Page 121: ...able tracing on ITM stimulus port 30 29 STIMENA29 R W 0h Bit mask to enable tracing on ITM stimulus port 29 28 STIMENA28 R W 0h Bit mask to enable tracing on ITM stimulus port 28 27 STIMENA27 R W 0h Bit mask to enable tracing on ITM stimulus port 27 26 STIMENA26 R W 0h Bit mask to enable tracing on ITM stimulus port 26 25 STIMENA25 R W 0h Bit mask to enable tracing on ITM stimulus port 25 24 STIME...

Page 122: ...le tracing on ITM stimulus port 6 5 STIMENA5 R W 0h Bit mask to enable tracing on ITM stimulus port 5 4 STIMENA4 R W 0h Bit mask to enable tracing on ITM stimulus port 4 3 STIMENA3 R W 0h Bit mask to enable tracing on ITM stimulus port 3 2 STIMENA2 R W 0h Bit mask to enable tracing on ITM stimulus port 2 1 STIMENA1 R W 0h Bit mask to enable tracing on ITM stimulus port 1 0 STIMENA0 R W 0h Bit mask...

Page 123: ...ble 2 92 TPR Register Field Descriptions Bit Field Type Reset Description 31 4 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 3 0 PRIVMASK R W 0h Bit mask to enable unprivileged User access to ITM stimulus ports Bit 0 enables stimulus ports 0 1 and 7 Bit 1 enables stimulus ports 8 9 and 15 Bit 2 enable...

Page 124: ...ting If multi source trace is in use this field must be written with a non zero value 15 10 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 9 8 TSPRESCALE R W 0h Timestamp prescaler 0h No prescaling 1h Divide by 4 2h Divide by 16 3h Divide by 64 7 5 RESERVED R W 0h Software must not rely on the value of...

Page 125: ... during idle times after a fixed number of two million cycles This provides a time reference for packets and inter packet gaps If SWOENA bit 4 is set timestamps are triggered by activity on the internal trace bus only In this case there is no regular timestamp output when the ITM is idle 0 ITMENA R W 0h Enables ITM This is the master enable and must be set before ITM Stimulus and Trace Enable regi...

Page 126: ...ter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LOCK_ACCESS W 0h Table 2 94 LAR Register Field Descriptions Bit Field Type Reset Description 31 0 LOCK_ACCESS W 0h A privileged write of 0xC5ACCE55 enables more write access to Control Registers TER TPR and TCR An invalid write removes write access 126 SWCU117C February 2015 Revised September 2015 Submit Docu...

Page 127: ...0h R 0h R 1h R 1h Table 2 95 LSR Register Field Descriptions Bit Field Type Reset Description 31 3 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 2 BYTEACC R 0h Reads 0 which means 8 bit lock access is not be implemented 1 ACCESS R 1h Write access to component is blocked All writes are ignored reads are ...

Page 128: ...y Section 2 7 4 18 408h NVIC_IPR2 Irq 8 to 11 Priority Section 2 7 4 19 40Ch NVIC_IPR3 Irq 12 to 15 Priority Section 2 7 4 20 410h NVIC_IPR4 Irq 16 to 19 Priority Section 2 7 4 21 414h NVIC_IPR5 Irq 20 to 23 Priority Section 2 7 4 22 418h NVIC_IPR6 Irq 24 to 27 Priority Section 2 7 4 23 41Ch NVIC_IPR7 Irq 28 to 31 Priority Section 2 7 4 24 420h NVIC_IPR8 Irq 32 to 35 Priority Section 2 7 4 25 D00h...

Page 129: ...AR1 ISA Feature 1 Section 2 7 4 51 D68h ID_ISAR2 ISA Feature 2 Section 2 7 4 52 D6Ch ID_ISAR3 ISA Feature 3 Section 2 7 4 53 D70h ID_ISAR4 ISA Feature 4 Section 2 7 4 54 D88h CPACR Coprocessor Access Control Section 2 7 4 55 DF0h DHCSR Debug Halting Control and Status Section 2 7 4 56 DF4h DCRSR Deubg Core Register Selector Section 2 7 4 57 DF8h DCRDR Debug Core Register Data Section 2 7 4 58 DFCh...

Page 130: ... 10 9 8 RESERVED R 0h 7 6 5 4 3 2 1 0 RESERVED INTLINESNUM R 0h R 1h Table 2 97 ICTR Register Field Descriptions Bit Field Type Reset Description 31 3 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 2 0 INTLINESNUM R 1h Total number of interrupt lines in groups of 32 0 0 32 1 33 64 2 65 96 3 97 128 4 129 ...

Page 131: ... R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 2 DISFOLD R W 0h Disables folding of IT instruction 1 DISDEFWBUF R W 0h Disables write buffer use during default memory map accesses This causes all bus faults to be precise bus faults but decreases the performance of the processor because the stores to memory hav...

Page 132: ...bit is cleared on read only if the MasterType bit in the AHB AP Control Register is set to 0 Otherwise COUNTFLAG is not changed by the debugger read 15 3 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 2 CLKSOURCE R 1h Clock source 0 External reference clock 1 Core clock External clock is not available in...

Page 133: ...ctivated when counting from 1 to 0 Figure 2 74 STRVR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RELOAD R W 0h R W X Table 2 100 STRVR Register Field Descriptions Bit Field Type Reset Description 31 24 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined beh...

Page 134: ...0 RESERVED CURRENT R W 0h R W X Table 2 101 STCVR Register Field Descriptions Bit Field Type Reset Description 31 24 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 23 0 CURRENT R W X Current value at the time the register is accessed No read modify write protection is provided so change with care Writi...

Page 135: ...pe Reset Description 31 NOREF R 1h Reads as one Indicates that no separate reference clock is provided 30 SKEW R 1h Reads as one The calibration value is not exactly 10ms because of clock frequency This could affect its suitability as a software real time clock 29 24 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined...

Page 136: ...e bit returns its current enable state 28 SETENA28 R W 0h Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 28 See EVENT CPUIRQSEL28 EV for details Reading the bit returns its current enable state 27 SETENA27 R W 0h Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 27 See EVENT CPUIRQSEL27 EV for details Reading the bit retu...

Page 137: ...t enables the interrupt number 12 See EVENT CPUIRQSEL12 EV for details Reading the bit returns its current enable state 11 SETENA11 R W 0h Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 11 See EVENT CPUIRQSEL11 EV for details Reading the bit returns its current enable state 10 SETENA10 R W 0h Writing 0 to this bit has no effect writing 1 to this bit enables ...

Page 138: ...ble state 1 SETENA1 R W 0h Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 1 See EVENT CPUIRQSEL1 EV for details Reading the bit returns its current enable state 0 SETENA0 R W 0h Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 0 See EVENT CPUIRQSEL0 EV for details Reading the bit returns its current enable state 138 SWCU...

Page 139: ...ter Field Descriptions Bit Field Type Reset Description 31 2 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 1 SETENA33 R W 0h Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 33 See EVENT CPUIRQSEL33 EV for details Reading the bit returns its current enable state 0...

Page 140: ... bit returns its current enable state 28 CLRENA28 R W 0h Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 28 See EVENT CPUIRQSEL28 EV for details Reading the bit returns its current enable state 27 CLRENA27 R W 0h Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 27 See EVENT CPUIRQSEL27 EV for details Reading the bit ret...

Page 141: ... disables the interrupt number 12 See EVENT CPUIRQSEL12 EV for details Reading the bit returns its current enable state 11 CLRENA11 R W 0h Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 11 See EVENT CPUIRQSEL11 EV for details Reading the bit returns its current enable state 10 CLRENA10 R W 0h Writing 0 to this bit has no effect writing 1 to this bit disable...

Page 142: ...ble state 1 CLRENA1 R W 0h Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 1 See EVENT CPUIRQSEL1 EV for details Reading the bit returns its current enable state 0 CLRENA0 R W 0h Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 0 See EVENT CPUIRQSEL0 EV for details Reading the bit returns its current enable state 142 SW...

Page 143: ...ster Field Descriptions Bit Field Type Reset Description 31 2 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 1 CLRENA33 R W 0h Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 33 See EVENT CPUIRQSEL33 EV for details Reading the bit returns its current enable state...

Page 144: ...mber 29 See EVENT CPUIRQSEL29 EV for details Reading the bit returns its current state 28 SETPEND28 R W 0h Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 28 See EVENT CPUIRQSEL28 EV for details Reading the bit returns its current state 27 SETPEND27 R W 0h Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 27 See EVENT CPUIRQSE...

Page 145: ...o this bit pends the interrupt number 12 See EVENT CPUIRQSEL12 EV for details Reading the bit returns its current state 11 SETPEND11 R W 0h Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 11 See EVENT CPUIRQSEL11 EV for details Reading the bit returns its current state 10 SETPEND10 R W 0h Writing 0 to this bit has no effect writing 1 to this bit pends the inter...

Page 146: ...current state 1 SETPEND1 R W 0h Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 1 See EVENT CPUIRQSEL1 EV for details Reading the bit returns its current state 0 SETPEND0 R W 0h Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 0 See EVENT CPUIRQSEL0 EV for details Reading the bit returns its current state 146 SWCU117C Februar...

Page 147: ... 108 NVIC_ISPR1 Register Field Descriptions Bit Field Type Reset Description 31 2 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 1 SETPEND33 R W 0h Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 33 See EVENT CPUIRQSEL33 EV for details Reading the bit returns its cu...

Page 148: ...eading the bit returns its current state 28 CLRPEND28 R W 0h Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 28 See EVENT CPUIRQSEL28 EV for details Reading the bit returns its current state 27 CLRPEND27 R W 0h Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 27 See EVENT CPUIRQSEL27 EV for det...

Page 149: ...s the corresponding pending interrupt 12 See EVENT CPUIRQSEL12 EV for details Reading the bit returns its current state 11 CLRPEND11 R W 0h Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 11 See EVENT CPUIRQSEL11 EV for details Reading the bit returns its current state 10 CLRPEND10 R W 0h Writing 0 to this bit has no effect writing 1 to this bit...

Page 150: ...state 1 CLRPEND1 R W 0h Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 1 See EVENT CPUIRQSEL1 EV for details Reading the bit returns its current state 0 CLRPEND0 R W 0h Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 0 See EVENT CPUIRQSEL0 EV for details Reading the bit returns its current st...

Page 151: ...r Field Descriptions Bit Field Type Reset Description 31 2 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 1 CLRPEND33 R W 0h Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 33 See EVENT CPUIRQSEL33 EV for details Reading the bit returns its current s...

Page 152: ...PUIRQSEL29 EV for details 28 ACTIVE28 R 0h Reading 0 from this bit implies that interrupt line 28 is not active Reading 1 from this bit implies that the interrupt line 28 is active See EVENT CPUIRQSEL28 EV for details 27 ACTIVE27 R 0h Reading 0 from this bit implies that interrupt line 27 is not active Reading 1 from this bit implies that the interrupt line 27 is active See EVENT CPUIRQSEL27 EV fo...

Page 153: ...12 is not active Reading 1 from this bit implies that the interrupt line 12 is active See EVENT CPUIRQSEL12 EV for details 11 ACTIVE11 R 0h Reading 0 from this bit implies that interrupt line 11 is not active Reading 1 from this bit implies that the interrupt line 11 is active See EVENT CPUIRQSEL11 EV for details 10 ACTIVE10 R 0h Reading 0 from this bit implies that interrupt line 10 is not active...

Page 154: ...for details 1 ACTIVE1 R 0h Reading 0 from this bit implies that interrupt line 1 is not active Reading 1 from this bit implies that the interrupt line 1 is active See EVENT CPUIRQSEL1 EV for details 0 ACTIVE0 R 0h Reading 0 from this bit implies that interrupt line 0 is not active Reading 1 from this bit implies that the interrupt line 0 is active See EVENT CPUIRQSEL0 EV for details 154 SWCU117C F...

Page 155: ...BR1 Register Field Descriptions Bit Field Type Reset Description 31 2 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 1 ACTIVE33 R 0h Reading 0 from this bit implies that interrupt line 33 is not active Reading 1 from this bit implies that the interrupt line 33 is active See EVENT CPUIRQSEL33 EV for detai...

Page 156: ... 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PRI_3 PRI_2 PRI_1 PRI_0 R W 0h R W 0h R W 0h R W 0h Table 2 113 NVIC_IPR0 Register Field Descriptions Bit Field Type Reset Description 31 24 PRI_3 R W 0h Priority of interrupt 3 See EVENT CPUIRQSEL3 EV for details 23 16 PRI_2 R W 0h Priority of interrupt 2 See EVENT CPUIRQSEL2 EV for details 15 8 PRI_1 R W 0h Priority...

Page 157: ... 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PRI_7 PRI_6 PRI_5 PRI_4 R W 0h R W 0h R W 0h R W 0h Table 2 114 NVIC_IPR1 Register Field Descriptions Bit Field Type Reset Description 31 24 PRI_7 R W 0h Priority of interrupt 7 See EVENT CPUIRQSEL7 EV for details 23 16 PRI_6 R W 0h Priority of interrupt 6 See EVENT CPUIRQSEL6 EV for details 15 8 PRI_5 R W 0h Priority...

Page 158: ...28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PRI_11 PRI_10 PRI_9 PRI_8 R W 0h R W 0h R W 0h R W 0h Table 2 115 NVIC_IPR2 Register Field Descriptions Bit Field Type Reset Description 31 24 PRI_11 R W 0h Priority of interrupt 11 See EVENT CPUIRQSEL11 EV for details 23 16 PRI_10 R W 0h Priority of interrupt 10 See EVENT CPUIRQSEL10 EV for details 15 8 PRI_9 R W 0h Prio...

Page 159: ...27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PRI_15 PRI_14 PRI_13 PRI_12 R W 0h R W 0h R W 0h R W 0h Table 2 116 NVIC_IPR3 Register Field Descriptions Bit Field Type Reset Description 31 24 PRI_15 R W 0h Priority of interrupt 15 See EVENT CPUIRQSEL15 EV for details 23 16 PRI_14 R W 0h Priority of interrupt 14 See EVENT CPUIRQSEL14 EV for details 15 8 PRI_13 R W 0h Prio...

Page 160: ...27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PRI_19 PRI_18 PRI_17 PRI_16 R W 0h R W 0h R W 0h R W 0h Table 2 117 NVIC_IPR4 Register Field Descriptions Bit Field Type Reset Description 31 24 PRI_19 R W 0h Priority of interrupt 19 See EVENT CPUIRQSEL19 EV for details 23 16 PRI_18 R W 0h Priority of interrupt 18 See EVENT CPUIRQSEL18 EV for details 15 8 PRI_17 R W 0h Prio...

Page 161: ...27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PRI_23 PRI_22 PRI_21 PRI_20 R W 0h R W 0h R W 0h R W 0h Table 2 118 NVIC_IPR5 Register Field Descriptions Bit Field Type Reset Description 31 24 PRI_23 R W 0h Priority of interrupt 23 See EVENT CPUIRQSEL23 EV for details 23 16 PRI_22 R W 0h Priority of interrupt 22 See EVENT CPUIRQSEL22 EV for details 15 8 PRI_21 R W 0h Prio...

Page 162: ...27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PRI_27 PRI_26 PRI_25 PRI_24 R W 0h R W 0h R W 0h R W 0h Table 2 119 NVIC_IPR6 Register Field Descriptions Bit Field Type Reset Description 31 24 PRI_27 R W 0h Priority of interrupt 27 See EVENT CPUIRQSEL27 EV for details 23 16 PRI_26 R W 0h Priority of interrupt 26 See EVENT CPUIRQSEL26 EV for details 15 8 PRI_25 R W 0h Prio...

Page 163: ...27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PRI_31 PRI_30 PRI_29 PRI_28 R W 0h R W 0h R W 0h R W 0h Table 2 120 NVIC_IPR7 Register Field Descriptions Bit Field Type Reset Description 31 24 PRI_31 R W 0h Priority of interrupt 31 See EVENT CPUIRQSEL31 EV for details 23 16 PRI_30 R W 0h Priority of interrupt 30 See EVENT CPUIRQSEL30 EV for details 15 8 PRI_29 R W 0h Prio...

Page 164: ... 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED PRI_33 PRI_32 R W 0h R W 0h R W 0h Table 2 121 NVIC_IPR8 Register Field Descriptions Bit Field Type Reset Description 31 16 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 15 8 PRI_33 R W 0h Priority of inter...

Page 165: ... 21 20 19 18 17 16 IMPLEMENTER VARIANT CONSTANT R 41h R 2h R Fh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PARTNO REVISION R C23h R 1h Table 2 122 CPUID Register Field Descriptions Bit Field Type Reset Description 31 24 IMPLEMENTER R 41h Implementor code 23 20 VARIANT R 2h Implementation defined variant number 19 16 CONSTANT R Fh Reads as 0xF 15 4 PARTNO R C23h Number of processor within family 3 0 REV...

Page 166: ...rved Writing any other value than the reset value may result in undefined behavior 28 PENDSVSET R W 0h Set pending pendSV bit 0 No action 1 Set pending PendSV 27 PENDSVCLR W X Clear pending pendSV bit 0 No action 1 Clear pending pendSV 26 PENDSTSET R W 0h Set a pending SysTick bit 0 No action 1 Set pending SysTick 25 PENDSTCLR W X Clear pending SysTick bit 0 No action 1 Clear pending SysTick 24 RE...

Page 167: ...execute 1 There are no active exceptions or the currently executing exception is the only active exception 10 9 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 8 0 VECTACTIVE R 0h Active ISR number field Reset clears this field 167 SWCU117C February 2015 Revised September 2015 Submit Documentation Feedbac...

Page 168: ...28 27 26 25 24 RESERVED TBLOFF R W 0h R W 0h 23 22 21 20 19 18 17 16 TBLOFF R W 0h 15 14 13 12 11 10 9 8 TBLOFF R W 0h 7 6 5 4 3 2 1 0 TBLOFF RESERVED R W 0h R W 0h Table 2 124 VTOR Register Field Descriptions Bit Field Type Reset Description 31 30 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 29 7 TB...

Page 169: ...n level It divides the PRI_n field in the Interrupt Priority Registers NVIC_IPR0 NVIC_IPR1 and NVIC_IPR8 into a pre emption level and a subpriority level The binary point is a left of value This means that the PRIGROUP value represents a point starting at the left of the Least Significant Bit LSB The lowest value might not be 0 depending on the number of bits allocated for priorities and implement...

Page 170: ...isabled interrupts are excluded 1 Enabled events and all interrupts including disabled interrupts can wakeup the processor When an event or interrupt enters pending state the event signal wakes up the processor from WFE If the processor is not waiting for an event the event is registered and affects the next WFE The processor also wakes up on execution of an SEV instruction 3 RESERVED R W 0h Softw...

Page 171: ...ta BusFaults caused by load and store instructions This applies to the HardFault NMI and FAULTMASK escalated handlers 0 Data BusFaults caused by load and store instructions cause a lock up 1 Data BusFaults caused by load and store instructions are ignored Set this bit to 1 only when the handler and its data are in absolutely safe memory The normal use of this bit is to probe system devices and bri...

Page 172: ...NA R W 0h Indicates how the processor enters Thread mode 0 Processor can enter Thread mode only when no exception is active 1 Processor can enter Thread mode from any level using the appropriate return value EXC_RETURN Exception returns occur when one of the following instructions loads a value of 0xFXXXXXXX into the PC while in Handler mode POP LDM which includes loading the PC LDR with PC as a d...

Page 173: ...Fault Figure 2 102 SHPR1 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED PRI_6 PRI_5 PRI_4 R W 0h R W 0h R W 0h R W 0h Table 2 128 SHPR1 Register Field Descriptions Bit Field Type Reset Description 31 24 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behav...

Page 174: ...abled the fault is always treated as a Hard Fault Figure 2 103 SHPR2 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PRI_11 RESERVED R W 0h R W 0h Table 2 129 SHPR2 Register Field Descriptions Bit Field Type Reset Description 31 24 PRI_11 R W 0h Priority of system handler 11 SVCall 23 0 RESERVED R W 0h Software must not rely on the value of a reserved...

Page 175: ... 2 104 SHPR3 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PRI_15 PRI_14 RESERVED PRI_12 R W 0h R W 0h R W 0h R W 0h Table 2 130 SHPR3 Register Field Descriptions Bit Field Type Reset Description 31 24 PRI_15 R W 0h Priority of system handler 15 SysTick exception 23 16 PRI_14 R W 0h Priority of system handler 14 Pend SV 15 8 RESERVED R W 0h Software...

Page 176: ...TAC T T T R 0h R 0h R 0h R 0h R 0h R 0h Table 2 131 SHCSR Register Field Descriptions Bit Field Type Reset Description 31 19 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 18 USGFAULTENA R W 0h Usage fault system handler enable 0h Exception disabled 1h Exception enabled 17 BUSFAULTENA R W 0h Bus fault ...

Page 177: ... active 0h Exception is not active 1h Exception is active 6 4 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 3 USGFAULTACT R 0h UsageFault exception active 0h Exception is not active 1h Exception is active 2 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the ...

Page 178: ... DACCVIOL IACCVIOL R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h Table 2 132 CFSR Register Field Descriptions Bit Field Type Reset Description 31 26 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 25 DIVBYZERO R W 0h When CCR DIV_0_TRP see Configuration Control Register on page 8 26 is enabled and an...

Page 179: ...time BFAR is not written 9 PRECISERR R W 0h Precise data bus error return 8 IBUSERR R W 0h Instruction bus error flag This flag is set by a prefetch error The fault stops on the instruction so if the error occurs under a branch shadow no fault occurs BFAR is not written 7 MMARVALID R W 0h Memory Manage Address Register MMFAR address valid flag A later arriving fault such as a bus fault can clear a...

Page 180: ...rity is higher than the monitor When both halting and monitor debug are disabled it only happens for debug events that are not ignored minimally BKPT The Debug Fault Status Register is updated 30 FORCED R W1C 0h Hard Fault activated because a Configurable Fault was received and cannot activate because of priority or because the Configurable Fault is disabled The Hard Fault handler then has to read...

Page 181: ...R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h Table 2 134 DFSR Register Field Descriptions Bit Field Type Reset Description 31 5 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 4 EXTERNAL R W 0h External debug request flag The processor stops on next instruction boundary 0x0 External debug request signal no...

Page 182: ...scriptions Bit Field Type Reset Description 31 0 ADDRESS R W X Mem Manage fault address field This field is the data address of a faulted load or store attempt When an unaligned access faults the address is the actual address that faulted Because an access can be split into multiple parts each aligned this address can be any offset in the range of the requested size Flags CFSR IACCVIOL CFSR DACCVI...

Page 183: ...36 BFAR Register Field Descriptions Bit Field Type Reset Description 31 0 ADDRESS R W X Bus fault address field This field is the data address of a faulted load or store attempt When an unaligned access faults the address is the address requested by the instruction even if that is not the address that faulted Flags CFSR IBUSERR CFSR PRECISERR CFSR IMPRECISERR CFSR UNSTKERR and CFSR STKERR in combi...

Page 184: ...writing a one to the corresponding bit Auxiliary fault inputs to the CPU are tied to 0 Figure 2 111 AFSR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IMPDEF R W 0h Table 2 137 AFSR Register Field Descriptions Bit Field Type Reset Description 31 0 IMPDEF R W 0h Implementation defined The bits map directly onto the signal assignment to the auxiliary ...

Page 185: ...not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 7 4 STATE1 R 3h State1 T bit 1 0x0 N A 0x1 N A 0x2 Thumb 2 encoding with the 16 bit basic instructions plus 32 bit Buncond BL but no other 32 bit basic instructions Note non basic 32 bit instructions can be added using the appropriate instruction attribute but other 32 bit basic instru...

Page 186: ...1 Register Field Descriptions Bit Field Type Reset Description 31 12 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 11 8 MICROCONTROLLER_P R 2h Microcontroller programmer s model ROGRAMMERS_MODEL 0x0 Not supported 0x2 Two stack support 7 0 RESERVED R 0h Software must not rely on the value of a reserved W...

Page 187: ...6 5 4 3 2 1 0 RESERVED R 0h Table 2 140 ID_DFR0 Register Field Descriptions Bit Field Type Reset Description 31 24 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 23 20 MICROCONTROLLER_D R 1h Microcontroller Debug Model memory mapped EBUG_MODEL 0x0 Not supported 0x1 Microcontroller debug v1 ITMv1 and DWTv...

Page 188: ...igure 2 115 ID_AFR0 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED R 0h Table 2 141 ID_AFR0 Register Field Descriptions Bit Field Type Reset Description 31 0 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 188 SWCU117C February 2015 Revised Septembe...

Page 189: ...Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED R 100030h Table 2 142 ID_MMFR0 Register Field Descriptions Bit Field Type Reset Description 31 0 RESERVED R 100030h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 189 SWCU117C February 2015 Revised September 2015 Su...

Page 190: ...R1 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED R 0h Table 2 143 ID_MMFR1 Register Field Descriptions Bit Field Type Reset Description 31 0 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 190 SWCU117C February 2015 Revised September 2015 Submit Do...

Page 191: ... 2 1 0 RESERVED R 0h Table 2 144 ID_MMFR2 Register Field Descriptions Bit Field Type Reset Description 31 25 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 24 WAIT_FOR_INTERRUPT R 1h wait for interrupt stalling _STALLING 0x0 Not supported 0x1 Wait for interrupt supported 23 0 RESERVED R 0h Software must ...

Page 192: ...R3 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED R 0h Table 2 145 ID_MMFR3 Register Field Descriptions Bit Field Type Reset Description 31 0 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 192 SWCU117C February 2015 Revised September 2015 Submit Do...

Page 193: ...30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED R 1101110h Table 2 146 ID_ISAR0 Register Field Descriptions Bit Field Type Reset Description 31 0 RESERVED R 1101110h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 193 SWCU117C February 2015 Revised September 2015 Submit Docum...

Page 194: ...30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED R 2111000h Table 2 147 ID_ISAR1 Register Field Descriptions Bit Field Type Reset Description 31 0 RESERVED R 2111000h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 194 SWCU117C February 2015 Revised September 2015 Submit Docum...

Page 195: ...0 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED R 21112231h Table 2 148 ID_ISAR2 Register Field Descriptions Bit Field Type Reset Description 31 0 RESERVED R 21112231h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 195 SWCU117C February 2015 Revised September 2015 Submit Docu...

Page 196: ...30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED R 1111110h Table 2 149 ID_ISAR3 Register Field Descriptions Bit Field Type Reset Description 31 0 RESERVED R 1111110h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 196 SWCU117C February 2015 Revised September 2015 Submit Docum...

Page 197: ...30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED R 1310132h Table 2 150 ID_ISAR4 Register Field Descriptions Bit Field Type Reset Description 31 0 RESERVED R 1310132h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 197 SWCU117C February 2015 Revised September 2015 Submit Docum...

Page 198: ...ster 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED R W 0h Table 2 151 CPACR Register Field Descriptions Bit Field Type Reset Description 31 0 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 198 SWCU117C February 2015 Revised September 2015 Submit Document...

Page 199: ...it Debug state step an instruction and halt Exceptions activate according to the exception configuration rules C_HALT 0 C_STEP 1 C_MASKINTS 1 Exit Debug state step an instruction and halt PendSV SysTick and external configurable interrupts are disabled otherwise exceptions activate according to standard configuration rules C_HALT 1 C_STEP x C_MASKINTS x Remain in Debug state Figure 2 126 DHCSR Reg...

Page 200: ...ignored and no bits are written into the register 15 6 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 5 C_SNAPSTALL R W 0h If the core is stalled on a load store operation the stall ceases and the instruction is forced to complete This enables Halting debug to gain control of the core It can only be set ...

Page 201: ...d when written by the core which cannot set or clear it The core must write a 1 to it when writing C_HALT to halt itself The values of C_HALT C_STEP and C_MASKINTS are ignored by hardware when C_DEBUGEN 0 The read values for C_HALT C_STEP and C_MASKINTS fields will be unknown to software when C_DEBUGEN 0 201 SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015...

Page 202: ...xecution is resumed Figure 2 127 DCRSR Register 31 30 29 28 27 26 25 24 RESERVED W X 23 22 21 20 19 18 17 16 RESERVED REGWNR W X W X 15 14 13 12 11 10 9 8 RESERVED W X 7 6 5 4 3 2 1 0 RESERVED REGSEL W X W X Table 2 153 DCRSR Register Field Descriptions Bit Field Type Reset Description 31 17 RESERVED W X Software must not rely on the value of a reserved Write 0 16 REGWNR W X 1 Write 0 Read 15 5 RE...

Page 203: ...registers to and from the processor This is the data value written to the register selected by DCRSR When the processor receives a request from DCRSR this register is read or written by the processor using a normal load store unit operation If core register transfers are not being performed software based debug monitors can use this register for communication in non halting debug This enables flag...

Page 204: ...END MON_EN R W 0h R W 0h R W 0h R W 0h R W 0h 15 14 13 12 11 10 9 8 RESERVED VC_HARDERR VC_INTERR VC_BUSERR R W 0h R W 0h R W 0h R W 0h 7 6 5 4 3 2 1 0 VC_STATERR VC_CHKERR VC_NOCPERR VC_MMERR RESERVED VC_CORERES ET R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h Table 2 155 DEMCR Register Field Descriptions Bit Field Type Reset Description 31 25 RESERVED R W 0h Software must not rely on the value of a ...

Page 205: ... not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 10 VC_HARDERR R W 0h Debug trap on Hard Fault Ignored when DHCSR C_DEBUGEN is cleared 9 VC_INTERR R W 0h Debug trap on a fault occurring during an exception entry or return sequence Ignored when DHCSR C_DEBUGEN is cleared 8 VC_BUSERR R W 0h Debug Trap on normal Bus error Ignored when ...

Page 206: ...W X Table 2 156 STIR Register Field Descriptions Bit Field Type Reset Description 31 9 RESERVED W 0h Software must not rely on the value of a reserved Write 0 8 0 INTID W X Interrupt ID field Writing a value to this bit field is the same as manually pending an interrupt by setting the corresponding interrupt bit in an Interrupt Set Pending Register in NVIC_ISPR0 or NVIC_ISPR1 206 SWCU117C February...

Page 207: ...Section 2 7 5 2 10h ACPR Async Clock Prescaler Section 2 7 5 3 F0h SPPR Selected Pin Protocol Section 2 7 5 4 300h FFSR Formatter and Flush Status Section 2 7 5 5 304h FFCR Formatter and Flush Control Section 2 7 5 6 308h FSCR Formatter Synchronization Counter Section 2 7 5 7 FA0h CLAIMMASK Claim Tag Mask Section 2 7 5 8 FA0h CLAIMSET Claim Tag Set Section 2 7 5 9 FA4h CLAIMTAG Current Claim Tag S...

Page 208: ...ED R 0h 7 6 5 4 3 2 1 0 RESERVED FOUR THREE TWO ONE R 0h R 1h R 0h R 1h R 1h Table 2 158 SSPSR Register Field Descriptions Bit Field Type Reset Description 31 4 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 3 FOUR R 1h 4 bit port size support 0x0 Not supported 0x1 Supported 2 THREE R 0h 3 bit port size ...

Page 209: ...VED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 3 FOUR R W 0h 4 bit port enable Writing values with more than one bit set in CSPSR or setting a bit that is not indicated as supported in SSPSR can cause Unpredictable behavior 2 THREE R W 0h 3 bit port enable Writing values with more than one bit set in CSPSR ...

Page 210: ...17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED PRESCALER R W 0h R W 0h Table 2 160 ACPR Register Field Descriptions Bit Field Type Reset Description 31 13 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 12 0 PRESCALER R W 0h Divisor for input trace clock is PRESCALER 1 210 SWCU117C February 2015 R...

Page 211: ... 17 16 RESERVED R W 0h 15 14 13 12 11 10 9 8 RESERVED R W 0h 7 6 5 4 3 2 1 0 RESERVED PROTOCOL R W 0h R W 1h Table 2 161 SPPR Register Field Descriptions Bit Field Type Reset Description 31 2 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 1 0 PROTOCOL R W 1h Trace output protocol 0h TracePort mode 1h S...

Page 212: ... 1 0 RESERVED FTNONSTOP RESERVED R 0h R 1h R 0h Table 2 162 FFSR Register Field Descriptions Bit Field Type Reset Description 31 4 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 3 FTNONSTOP R 1h 0 Formatter can be stopped 1 Formatter cannot be stopped 2 0 RESERVED R 0h This field always reads as zero 212...

Page 213: ...ster reverts to its previously programmed value Figure 2 136 FFCR Register 31 30 29 28 27 26 25 24 RESERVED R W 0h 23 22 21 20 19 18 17 16 RESERVED R W 0h 15 14 13 12 11 10 9 8 RESERVED TRIGIN R W 0h R W 1h 7 6 5 4 3 2 1 0 RESERVED ENFCONT RESERVED R W 0h R W 1h R W 0h Table 2 163 FFCR Register Field Descriptions Bit Field Type Reset Description 31 9 RESERVED R W 0h Software must not rely on the v...

Page 214: ...21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FSCR R 0h Table 2 164 FSCR Register Field Descriptions Bit Field Type Reset Description 31 0 FSCR R 0h The global synchronization trigger is generated by the Program Counter PC Sampler block This means that there is no synchronization counter in the TPIU 214 SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright...

Page 215: ...IMMASK Register Field Descriptions Bit Field Type Reset Description 31 0 CLAIMMASK R Fh This register forms one half of the Claim Tag value When reading this register returns the number of bits that can be set each bit is considered separately 0 This claim tag bit is not implemented 1 This claim tag bit is not implemented The behavior when writing to this register is described in CLAIMSET 215 SWCU...

Page 216: ... W Fh Table 2 166 CLAIMSET Register Field Descriptions Bit Field Type Reset Description 31 0 CLAIMSET W Fh This register forms one half of the Claim Tag value Writing to this location allows individual bits to be set each bit is considered separately 0 No effect 1 Set this bit in the claim tag The behavior when reading from this location is described in CLAIMMASK 216 SWCU117C February 2015 Revised...

Page 217: ...AIMTAG R 0h Table 2 167 CLAIMTAG Register Field Descriptions Bit Field Type Reset Description 31 0 CLAIMTAG R 0h This register forms one half of the Claim Tag value Reading this register returns the current Claim Tag value Reading CLAIMMASK determines how many bits from this register must be used The behavior when writing to this register is described in CLAIMCLR 217 SWCU117C February 2015 Revised...

Page 218: ...W 0h Table 2 168 CLAIMCLR Register Field Descriptions Bit Field Type Reset Description 31 0 CLAIMCLR W 0h This register forms one half of the Claim Tag value Writing to this location enables individual bits to be cleared each bit is considered separately 0 No effect 1 Clear this bit in the claim tag The behavior when reading from this location is described in CLAIMTAG 218 SWCU117C February 2015 Re...

Page 219: ...28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEVID R CA0h Table 2 169 DEVID Register Field Descriptions Bit Field Type Reset Description 31 0 DEVID R CA0h This field returns 0xCA1 if there is an ETM present 0xCA0 if there is no ETM present 219 SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 220: ...his chapter describes the Cortex M3 peripherals Topic Page 3 1 Cortex M3 Peripherals Introduction 221 3 2 Functional Description 221 220 Cortex M3 Peripherals SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 221: ...ss regions as indicated by two addresses listed Table 3 1 Core Peripheral Register Regions ADDRESS CORE PERIPHERAL LINK 0xE000 E010 to 0xE000 E01C System timer SysTick See Section 3 2 1 SysTick 0xE000 E100 to 0xE000 E420 Nested vectored interrupt controller See Section 3 2 2 NVIC 0xE000 EF00 to 0xE000 EF00 NVIC 0xE000 E008 to 0xE000 E00F System control block SCB See Section 3 2 3 SCB 0xE000 ED00 t...

Page 222: ...d the timer counts down on each clock from the reload value to 0 reloads wraps to the value in the STRVR register on the next clock edge then decrements on subsequent clocks Clearing the STRVR register disables the counter on the next wrap When the counter reaches 0 the COUNTFLAG status bit is set The COUNTFLAG bit clears on reads Writing to the STCVR register clears the register and the COUNTFLAG...

Page 223: ...ftware generated interrupt pending see the NVIC_ISPR0 SETPENDn register bit in Section 2 7 4 10 or the STIR INTID register field in Section 2 7 4 60 A pending interrupt remains pending until one of the following occurs The processor enters the ISR for the interrupt changing the state of the interrupt from pending to active Then For a level sensitive interrupt when the processor returns from the IS...

Page 224: ...o a corresponding area in the System space Alternatively the comparators can be individually configured to return a Breakpoint BKPT instruction to the processor core on a match for hardware breakpoint capability A reduced FPB unit contains Two instruction comparators that can be configured individually to return a BKPT instruction to the processor on a match and to provide hardware breakpoint capa...

Page 225: ... reduced DWT contains one comparator that can be used as a watchpoint or as a trigger A reduced DWT does not support data matching The DWT contains counters for the following Clock cycles CYCCNT Folded instructions Load store unit LSU operations Sleep cycles CPI that is all instruction cycles except for the first cycle Interrupt overhead The DWT generates PC samples at defined intervals and interr...

Page 226: ...nd Trace 0xE000 1000 CPU_FPB Cortex M Flash Patch and Breakpoint 0xE000 2000 CPU_ITM Cortex M Instrumentation Trace Macrocell 0xE000 0000 CPU_SCS Cortex M System Control Space 0xE000 E000 CPU_TPIU Cortex M Trace Port Interface Unit 0xE004 0000 FCFG1 Factory Configuration Area 1 0x5000 1000 FLASH Flash Controller 0x4003 0000 FLASHMEM On Chip Flash 0x0000 0000 GPT0 General Purpose Timer 0 0x4001 000...

Page 227: ...iversal Asynchronous Receiver Transmitter 0 0x4000 1000 UDMA0 Micro Direct Memory Access Controller 0 0x4002 0000 VIMS Versatile Instruction Memory System Control 0x4003 4000 WDT Watchdog Timer 0x4008 0000 227 SWCU117C February 2015 Revised September 2015 Cortex M3 Peripherals Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 228: ...nts Topic Page 4 1 Exception Model 229 4 2 Fault Handling 236 4 3 Event Fabric 238 4 4 AON Event Fabric 239 4 5 MCU Event Fabric 241 4 6 Memory Map 246 4 7 Interrupts and Events Registers 247 228 Interrupts and Events SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 229: ...cts the interrupt as still asserted causing the interrupt handler to be re entered errantly This situation can be avoided by either clearing the interrupt source at the beginning of the interrupt handler or by performing a read or write after the write to clear the interrupt source and flush the write buffer For more information on exceptions and interrupts see Section 3 2 2 Cortex M3 Peripherals ...

Page 230: ...tion as system tick Interrupt IRQ An interrupt or IRQ is an exception signaled by a peripheral or generated by a software request and fed through the NVIC prioritized All interrupts are asynchronous to instruction execution In the system peripherals use interrupts to communicate with the processor Table 4 8 lists the interrupts on the CC26xx and CC13xx controller For an asynchronous exception othe...

Page 231: ...64 RF Core and packet engine 2 26 10 0x0000 0068 RF Core hardware 27 11 0x0000 006C RF command acknowledge 28 12 0x0000 0070 I2S 29 13 0x0000 0074 Unassigned 30 14 0x0000 0078 Watchdog timer 31 15 0x0000 007C GPTimer 0A 32 16 0x0000 0080 GPTimer 0B 33 17 0x0000 0084 GPTimer 1A 34 18 0x0000 0088 GPTimer 1B 35 19 0x0000 008C GPTimer 2A 36 20 0x0000 0090 GPTimer 2B 37 21 0x0000 0094 GPTimer 3A 38 22 ...

Page 232: ...system handlers 4 1 4 Vector Table Figure 4 1 contains the reset value of the stack pointer and the start addresses also called exception vectors for all exception handlers The vector table is constructed using the vector address or offset listed in Table 4 1 Figure 4 1 shows the order of the exception vectors in the vector table The least significant bit LSB of each vector must be 1 indicating th...

Page 233: ... an exception handler the exception handler is preempted if a higher priority exception occurs If an exception occurs with the same priority as the exception being handled the handler is not preempted irrespective of the exception number However the status of the new interrupt changes to pending 4 1 6 Interrupt Priority Grouping To increase priority control in systems with interrupts the NVIC supp...

Page 234: ... Section 4 1 7 2 Exception Return Tail Chaining This mechanism speeds up exception servicing When an exception handler completes if a pending exception meets the requirements for exception entry the stack pop is skipped and control transfers to the new exception handler Late Arriving This mechanism speeds up preemption If a higher priority exception occurs during state saving for a previous except...

Page 235: ...hen stacking completes the processor starts executing the exception handler At the same time the processor writes an EXC_RETURN value to the LR indicating which stack pointer corresponds to the stack frame and what operation mode the processor was in before the entry occurred If no higher priority exception occurs during exception entry the processor starts executing the exception handler and auto...

Page 236: ...egister Offset D28h reset X Table 4 4 Faults Fault Handler Fault Status Register Bit Name Bus error on a vector read Hard fault Hard Fault Status HFSR VECTTBL Fault escalated to a hard fault Hard fault Hard Fault Status HFSR FORCED Bus error during exception Bus fault Bus Fault Status BFSR STKERR stacking Bus error during exception Bus fault Bus Fault Status BFSR UNSTEKRR unstacking Bus error duri...

Page 237: ...ently executing An exception handler causes a fault for which the priority is the same as or lower than the exception that is currently executing A fault occurs and the handler for that fault is not enabled NOTE If a bus fault occurs during a stack push when entering a bus fault handler the bus fault does not escalate to a hard fault Thus if a corrupted stack causes a fault the fault handler execu...

Page 238: ...configurable output lines go to the event subscribers A configurable output line from a subscriber can choose from a list of several input events available to the specific subscriber in question Subscribers output event signaling identical to input signaling That is events are simply passed through the event fabric as presented to the input ports Possible event types include system hardware interr...

Page 239: ...used to control and report the selection settings for a subscriber output For each subscriber output an address is mapped for a read register that contains a value representing the selection of the input event currently set for that subscriber output For nonconfigurable outputs only a read only register is implemented A read to that address returns the static predefined value The second type of re...

Page 240: ...the MCU JTAG has one wake up event going to the WUC while the AUX domain has three programmable input events and the MCU domain has four programmable input events These specific input events are ORed together to form a single input to the WUC one from the MCU and one from the AUX Figure 4 5 shows this configuration The inputs can be configured in the two selection registers AON_EVENT AUXWUSEL and ...

Page 241: ...ROG0_EV Event selected by AON_EVENT MCU event selector 0x2 AON_PROG1 AON_EVENT EVTOMCUSEL AON_PROG1_EV Event selected by AON_EVENT MCU event selector 0x3 AON_PROG2 AON_EVENT EVTOMCUSEL AON_PROG2_EV Edge detect event from IOC Configured by the 0x4 AON_GPIO_EDGE IOC IOCFGn EDGE_IRQ_EN and IOC IOCFGn EDGE_DET settings A complete byte transfer event from the SPIS Equivalent to the 0x5 AON_SPIS_BYTE_DO...

Page 242: ... Only interrupts selected with CPE1 in RFC_DBELL RFCPEIFG can trigger a RFC_CPE_1 event 0x1F NOT_USED 0x20 NOT_USED 0x21 NOT_USED 0x22 SSI0_COMB SSI0 combined interrupt interrupt flags are found here SSI0 MIS 0x23 SSI1_COMB SSI0 combined interrupt interrupt flags are found here SSI1 MIS 0x24 UART0_COMB UART0 combined interrupt interrupt flags are found here UART0 MIS 0x25 0x26 DMA_ERR DMA bus erro...

Page 243: ...V 0x4F GPT1A_DMABREQ GPT 1A DMA trigger event Configured by GPT1 DMAEV 0x50 GPT1B_DMABREQ GPT 1B DMA trigger event Configured by GPT1 DMAEV 0x51 GPT2A_DMABREQ GPT 2A DMA trigger event Configured by GPT2 DMAEV 0x52 GPT2B_DMABREQ GPT 2B DMA trigger event Configured by GPT2 DMAEV 0x53 GPT3A_DMABREQ GPT 3A DMA trigger event Configured by GPT3 DMAEV 0x54 GPT3B_DMABREQ GPT 3B DMA trigger event Configure...

Page 244: ...X_COMPA AUX COMP B event corresponds to 0x6B AUX_COMPB AUX_EVCTL EVTOMCUFLAGS AUX_COMPB AUX TDC measurement done event corresponds to the flag 0x6C AUX_TDC_DONE AUX_EVCTL EVTOMCUFLAGS TDC_DONE and the AUX_TDC status AUX_TDC STAT DONE AUX TIMER 0 event corresponds to 0x6D AUX_TIMER0_EV AUX_EVCTL EVTOMCUFLAGS TIMER0_EV AUX TIMER 1 event corresponds to 0x6E AUX_TIMER1_EV AUX_EVCTL EVTOMCUFLAGS TIMER1...

Page 245: ...vent fabric EVENT CPUIRQSEL29 is a read only register for routing within the MCU event fabric and cannot be configured but the input event within the AON event fabric going to this line can be configured One dynamic event interrupt called Dynamic Programmable Event has the valid selections as seen in Table 4 8 The EVENT CPUIRQSEL29 register is used to configure the input See the EVENT CPUIRQSEL30 ...

Page 246: ...AUX_SWEV2 AUX Software triggered event n n 0 2 0x2F AUX_COMPA Comparator A triggered 0x30 AUX_COMPB Comparator B triggered 0x31 AUX_ADC_DONE ADC conversion completed 0x32 AUX_TDC_DONE TDC completed or timed out 0x33 to 0x34 AUX_TIMER0_EV to AUX_TIMER1_EV AUX Timer n Event n 0 1 0x35 BATMON_TEMP BATMON temperature update event 0x36 BATMON_VOLT BATMON voltage update event 0x37 AUX_COMPB_ASYNC Compar...

Page 247: ...contents must not be modified Table 4 9 AON_EVENT Registers Offset Acronym Register Name Section 0h MCUWUSEL Wake up Selector For MCU Section 4 7 1 1 4h AUXWUSEL Wake up Selector For AUX Section 4 7 1 2 8h EVTOMCUSEL Event Selector For MCU Event Fabric Section 4 7 1 3 Ch RTCSEL RTC Capture Event Selector For AON_RTC Section 4 7 1 4 247 SWCU117C February 2015 Revised September 2015 Interrupts and E...

Page 248: ...MCUCLK PWR_DWN_SRC NONE to also set up a wake up event here before MCU is requesting power down PRCM requests uLDO see conditions in PRCM VDCTL ULDO as it speeds up the wake up procedure Figure 4 6 MCUWUSEL Register 31 30 29 28 27 26 25 24 RESERVED WU3_EV R 0h R W 3Fh 23 22 21 20 19 18 17 16 RESERVED WU2_EV R 0h R W 3Fh 15 14 13 12 11 10 9 8 RESERVED WU1_EV R 0h R W 3Fh 7 6 5 4 3 2 1 0 RESERVED WU...

Page 249: ...22 17h Edge detect on PAD23 18h Edge detect on PAD24 19h Edge detect on PAD25 1Ah Edge detect on PAD26 1Bh Edge detect on PAD27 1Ch Edge detect on PAD28 1Dh Edge detect on PAD29 1Eh Edge detect on PAD30 1Fh Edge detect on PAD31 20h Edge detect on any PAD 23h RTC channel 0 event 24h RTC channel 1 event 25h RTC channel 2 event 26h RTC channel 0 delayed event 27h RTC channel 1 delayed event 28h RTC c...

Page 250: ...AD1 2h Edge detect on PAD2 3h Edge detect on PAD3 4h Edge detect on PAD4 5h Edge detect on PAD5 6h Edge detect on PAD6 7h Edge detect on PAD7 8h Edge detect on PAD8 9h Edge detect on PAD9 Ah Edge detect on PAD10 Bh Edge detect on PAD11 Ch Edge detect on PAD12 Dh Edge detect on PAD13 Eh Edge detect on PAD14 Fh Edge detect on PAD15 10h Edge detect on PAD16 11h Edge detect on PAD17 12h Edge detect on...

Page 251: ...ted 32h TDC completed or timed out 33h AUX Timer 0 Event 34h AUX Timer 1 Event 35h BATMON temperature update event 36h BATMON voltage update event 37h Comparator B triggered Asynchronous signal directly from the AUX Comparator B as opposed to AUX_COMPB which is synchronized in AUX 38h Comparator B not triggered Asynchronous signal directly from AUX Comparator B inverted as opposed to AUX_COMPB whi...

Page 252: ...22 17h Edge detect on PAD23 18h Edge detect on PAD24 19h Edge detect on PAD25 1Ah Edge detect on PAD26 1Bh Edge detect on PAD27 1Ch Edge detect on PAD28 1Dh Edge detect on PAD29 1Eh Edge detect on PAD30 1Fh Edge detect on PAD31 20h Edge detect on any PAD 23h RTC channel 0 event 24h RTC channel 1 event 25h RTC channel 2 event 26h RTC channel 0 delayed event 27h RTC channel 1 delayed event 28h RTC c...

Page 253: ... 2h Edge detect on PAD2 3h Edge detect on PAD3 4h Edge detect on PAD4 5h Edge detect on PAD5 6h Edge detect on PAD6 7h Edge detect on PAD7 8h Edge detect on PAD8 9h Edge detect on PAD9 Ah Edge detect on PAD10 Bh Edge detect on PAD11 Ch Edge detect on PAD12 Dh Edge detect on PAD13 Eh Edge detect on PAD14 Fh Edge detect on PAD15 10h Edge detect on PAD16 11h Edge detect on PAD17 12h Edge detect on PA...

Page 254: ...omparator A triggered 30h Comparator B triggered 31h ADC conversion completed 32h TDC completed or timed out 33h AUX Timer 0 Event 34h AUX Timer 1 Event 35h BATMON temperature update event 36h BATMON voltage update event 37h Comparator B triggered Asynchronous signal directly from the AUX Comparator B as opposed to AUX_COMPB which is synchronized in AUX 38h Comparator B not triggered Asynchronous ...

Page 255: ... when AON_WUC AUXCLK PWR_DWN_SRC NONE to also set up a wake up event here before AUX is requesting power down AUX_WUC PWRDWNREQ REQ is asserted as it speeds up the wake up procedure Figure 4 7 AUXWUSEL Register 31 30 29 28 27 26 25 24 RESERVED R 0h 23 22 21 20 19 18 17 16 RESERVED WU2_EV R 0h R W 3Fh 15 14 13 12 11 10 9 8 RESERVED WU1_EV R 0h R W 3Fh 7 6 5 4 3 2 1 0 RESERVED WU0_EV R 0h R W 3Fh Ta...

Page 256: ...22 17h Edge detect on PAD23 18h Edge detect on PAD24 19h Edge detect on PAD25 1Ah Edge detect on PAD26 1Bh Edge detect on PAD27 1Ch Edge detect on PAD28 1Dh Edge detect on PAD29 1Eh Edge detect on PAD30 1Fh Edge detect on PAD31 20h Edge detect on any PAD 23h RTC channel 0 event 24h RTC channel 1 event 25h RTC channel 2 event 26h RTC channel 0 delayed event 27h RTC channel 1 delayed event 28h RTC c...

Page 257: ...D1 2h Edge detect on PAD2 3h Edge detect on PAD3 4h Edge detect on PAD4 5h Edge detect on PAD5 6h Edge detect on PAD6 7h Edge detect on PAD7 8h Edge detect on PAD8 9h Edge detect on PAD9 Ah Edge detect on PAD10 Bh Edge detect on PAD11 Ch Edge detect on PAD12 Dh Edge detect on PAD13 Eh Edge detect on PAD14 Fh Edge detect on PAD15 10h Edge detect on PAD16 11h Edge detect on PAD17 12h Edge detect on ...

Page 258: ...eted 32h TDC completed or timed out 33h AUX Timer 0 Event 34h AUX Timer 1 Event 35h BATMON temperature update event 36h BATMON voltage update event 37h Comparator B triggered Asynchronous signal directly from the AUX Comparator B as opposed to AUX_COMPB which is synchronized in AUX 38h Comparator B not triggered Asynchronous signal directly from AUX Comparator B inverted as opposed to AUX_COMPB wh...

Page 259: ...2 17h Edge detect on PAD23 18h Edge detect on PAD24 19h Edge detect on PAD25 1Ah Edge detect on PAD26 1Bh Edge detect on PAD27 1Ch Edge detect on PAD28 1Dh Edge detect on PAD29 1Eh Edge detect on PAD30 1Fh Edge detect on PAD31 20h Edge detect on any PAD 23h RTC channel 0 event 24h RTC channel 1 event 25h RTC channel 2 event 26h RTC channel 0 delayed event 27h RTC channel 1 delayed event 28h RTC ch...

Page 260: ...7h Comparator B triggered Asynchronous signal directly from the AUX Comparator B as opposed to AUX_COMPB which is synchronized in AUX 38h Comparator B not triggered Asynchronous signal directly from AUX Comparator B inverted as opposed to AUX_COMPB which is synchronized in AUX 3Fh No event always low 260 Interrupts and Events SWCU117C February 2015 Revised September 2015 Submit Documentation Feedb...

Page 261: ...D R 0h 23 22 21 20 19 18 17 16 RESERVED AON_PROG2_EV R 0h R W 2Bh 15 14 13 12 11 10 9 8 RESERVED AON_PROG1_EV R 0h R W 2Bh 7 6 5 4 3 2 1 0 RESERVED AON_PROG0_EV R 0h R W 2Bh Table 4 12 EVTOMCUSEL Register Field Descriptions Bit Field Type Reset Description 31 22 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined beha...

Page 262: ...PAD23 18h Edge detect on PAD24 19h Edge detect on PAD25 1Ah Edge detect on PAD26 1Bh Edge detect on PAD27 1Ch Edge detect on PAD28 1Dh Edge detect on PAD29 1Eh Edge detect on PAD30 1Fh Edge detect on PAD31 20h Edge detect on any PAD 23h RTC channel 0 event 24h RTC channel 1 event 25h RTC channel 2 event 26h RTC channel 0 delayed event 27h RTC channel 1 delayed event 28h RTC channel 2 delayed event...

Page 263: ... PAD4 5h Edge detect on PAD5 6h Edge detect on PAD6 7h Edge detect on PAD7 8h Edge detect on PAD8 9h Edge detect on PAD9 Ah Edge detect on PAD10 Bh Edge detect on PAD11 Ch Edge detect on PAD12 Dh Edge detect on PAD13 Eh Edge detect on PAD14 Fh Edge detect on PAD15 10h Edge detect on PAD16 11h Edge detect on PAD17 12h Edge detect on PAD18 13h Edge detect on PAD19 14h Edge detect on PAD20 15h Edge d...

Page 264: ...Timer 0 Event 34h AUX Timer 1 Event 35h BATMON temperature update event 36h BATMON voltage update event 37h Comparator B triggered Asynchronous signal directly from the AUX Comparator B as opposed to AUX_COMPB which is synchronized in AUX 38h Comparator B not triggered Asynchronous signal directly from AUX Comparator B inverted as opposed to AUX_COMPB which is synchronized in AUX 3Fh No event alwa...

Page 265: ...AD23 18h Edge detect on PAD24 19h Edge detect on PAD25 1Ah Edge detect on PAD26 1Bh Edge detect on PAD27 1Ch Edge detect on PAD28 1Dh Edge detect on PAD29 1Eh Edge detect on PAD30 1Fh Edge detect on PAD31 20h Edge detect on any PAD 23h RTC channel 0 event 24h RTC channel 1 event 25h RTC channel 2 event 26h RTC channel 0 delayed event 27h RTC channel 1 delayed event 28h RTC channel 2 delayed event ...

Page 266: ...tor B triggered Asynchronous signal directly from the AUX Comparator B as opposed to AUX_COMPB which is synchronized in AUX 38h Comparator B not triggered Asynchronous signal directly from AUX Comparator B inverted as opposed to AUX_COMPB which is synchronized in AUX 3Fh No event always low 266 Interrupts and Events SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyri...

Page 267: ... Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESERVED R 0h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RTC_CH1_CAPT_EV R 0h R W 3Fh Table 4 13 RTCSEL Register Field Descriptions Bit Field Type Reset Description 31 6 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 267 SWCU117C February 2015...

Page 268: ...ge detect on PAD24 19h Edge detect on PAD25 1Ah Edge detect on PAD26 1Bh Edge detect on PAD27 1Ch Edge detect on PAD28 1Dh Edge detect on PAD29 1Eh Edge detect on PAD30 1Fh Edge detect on PAD31 20h Edge detect on any PAD 23h RTC channel 0 event 24h RTC channel 1 event 25h RTC channel 2 event 26h RTC channel 0 delayed event 27h RTC channel 1 delayed event 28h RTC channel 2 delayed event 29h RTC com...

Page 269: ...ed Asynchronous signal directly from the AUX Comparator B as opposed to AUX_COMPB which is synchronized in AUX 38h Comparator B not triggered Asynchronous signal directly from AUX Comparator B inverted as opposed to AUX_COMPB which is synchronized in AUX 3Fh No event always low 269 SWCU117C February 2015 Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright 2015 Texa...

Page 270: ...19 4Ch CPUIRQSEL19 Output Selection for CPU Interrupt 19 Section 4 7 2 20 50h CPUIRQSEL20 Output Selection for CPU Interrupt 20 Section 4 7 2 21 54h CPUIRQSEL21 Output Selection for CPU Interrupt 21 Section 4 7 2 22 58h CPUIRQSEL22 Output Selection for CPU Interrupt 22 Section 4 7 2 23 5Ch CPUIRQSEL23 Output Selection for CPU Interrupt 23 Section 4 7 2 24 60h CPUIRQSEL24 Output Selection for CPU I...

Page 271: ... 7 2 67 54Ch UDMACH9BSEL Output Selection for DMA Channel 9 REQ Section 4 7 2 68 550h UDMACH10SSEL Output Selection for DMA Channel 10 SREQ Section 4 7 2 69 554h UDMACH10BSEL Output Selection for DMA Channel 10 REQ Section 4 7 2 70 558h UDMACH11SSEL Output Selection for DMA Channel 11 SREQ Section 4 7 2 71 55Ch UDMACH11BSEL Output Selection for DMA Channel 11 REQ Section 4 7 2 72 560h UDMACH12SSEL...

Page 272: ...0 Output Selection for NMI Subscriber 0 Section 4 7 2 93 900h I2SSTMPSEL0 Output Selection for I2S Subscriber 0 Section 4 7 2 94 A00h FRZSEL0 Output Selection for FRZ Subscriber 0 Section 4 7 2 95 F00h SWEV Set or Clear Software Events Section 4 7 2 96 272 Interrupts and Events SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated...

Page 273: ... R 4h Table 4 15 CPUIRQSEL0 Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 4h Read only selection value 4h Edge detect event from IOC Configured by the IOC IOCFGn EDGE_IRQ_EN and IOC IOCFGn EDGE_DET settings 273 SWCU117C February ...

Page 274: ...0 9 8 7 6 5 4 3 2 1 0 RESERVED EV R 0h R 9h Table 4 16 CPUIRQSEL1 Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 9h Read only selection value 9h Interrupt event from I2C 274 Interrupts and Events SWCU117C February 2015 Revised Sep...

Page 275: ...eld Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 1Eh Read only selection value 1Eh Combined Interrupt for CPE Generated events Corresponding flags are here RFC_DBELL RFCPEIFG Only interrupts selected with CPE1 in RFC_DBELL RFCPEIFG can trigger...

Page 276: ...22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED R 38h Table 4 18 CPUIRQSEL3 Register Field Descriptions Bit Field Type Reset Description 31 0 RESERVED R 38h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 276 Interrupts and Events SWCU117C February 2015 Revised September 2015 Submit Documentation Fe...

Page 277: ...RESERVED EV R 0h R 7h Table 4 19 CPUIRQSEL4 Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 7h Read only selection value 7h Event from AON_RTC controlled by the AON_RTC CTL COMB_EV_MASK setting 277 SWCU117C February 2015 Revised Se...

Page 278: ... RESERVED EV R 0h R 24h Table 4 20 CPUIRQSEL5 Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 24h Read only selection value 24h UART0 combined interrupt interrupt flags are found here UART0 MIS 278 Interrupts and Events SWCU117C Fe...

Page 279: ...riptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 1Ch Read only selection value 1Ch AUX software event 0 triggered by AUX_EVCTL SWEVSET SWEV0 also available as AUX_EVENT0 AON wake up event MCU domain wake up control AON_EVENT MCUWUSEL AUX domain wake u...

Page 280: ...0 RESERVED EV R 0h R 22h Table 4 22 CPUIRQSEL7 Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 22h Read only selection value 22h SSI0 combined interrupt interrupt flags are found here SSI0 MIS 280 Interrupts and Events SWCU117C Feb...

Page 281: ...0 RESERVED EV R 0h R 23h Table 4 23 CPUIRQSEL8 Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 23h Read only selection value 23h SSI0 combined interrupt interrupt flags are found here SSI1 MIS 281 SWCU117C February 2015 Revised Sep...

Page 282: ...ield Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 1Bh Read only selection value 1Bh Combined Interrupt for CPE Generated events Corresponding flags are here RFC_DBELL RFCPEIFG Only interrupts selected with CPE0 in RFC_DBELL RFCPEIFG can trigge...

Page 283: ...SERVED EV R 0h R 1Ah Table 4 25 CPUIRQSEL10 Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 1Ah Read only selection value 1Ah Combined RCF hardware interrupt corresponding flag is here RFC_DBELL RFHWIFG 283 SWCU117C February 2015 R...

Page 284: ...D EV R 0h R 19h Table 4 26 CPUIRQSEL11 Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 19h Read only selection value 19h RFC Doorbell Command Acknowledgment Interrupt equivalent to RFC_DBELL RFACKIFG ACKFLAG 284 Interrupts and Even...

Page 285: ...1 10 9 8 7 6 5 4 3 2 1 0 RESERVED EV R 0h R 8h Table 4 27 CPUIRQSEL12 Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 8h Read only selection value 8h Interrupt event from I2S 285 SWCU117C February 2015 Revised September 2015 Interr...

Page 286: ...escriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 1Dh Read only selection value 1Dh AUX software event 1 triggered by AUX_EVCTL SWEVSET SWEV1 also available as AUX_EVENT2 AON wake up event MCU domain wake up control AON_EVENT MCUWUSEL AUX domain wak...

Page 287: ...4 3 2 1 0 RESERVED EV R 0h R 18h Table 4 29 CPUIRQSEL14 Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 18h Read only selection value 18h Watchdog interrupt event controlled by WDT CTL INTEN 287 SWCU117C February 2015 Revised Septe...

Page 288: ... 5 4 3 2 1 0 RESERVED EV R 0h R 10h Table 4 30 CPUIRQSEL15 Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 10h Read only selection value 10h GPT0A interrupt event controlled by GPT0 TAMR 288 Interrupts and Events SWCU117C February ...

Page 289: ... 5 4 3 2 1 0 RESERVED EV R 0h R 11h Table 4 31 CPUIRQSEL16 Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 11h Read only selection value 11h GPT0B interrupt event controlled by GPT0 TBMR 289 SWCU117C February 2015 Revised September...

Page 290: ... 5 4 3 2 1 0 RESERVED EV R 0h R 12h Table 4 32 CPUIRQSEL17 Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 12h Read only selection value 12h GPT1A interrupt event controlled by GPT1 TAMR 290 Interrupts and Events SWCU117C February ...

Page 291: ... 5 4 3 2 1 0 RESERVED EV R 0h R 13h Table 4 33 CPUIRQSEL18 Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 13h Read only selection value 13h GPT1B interrupt event controlled by GPT1 TBMR 291 SWCU117C February 2015 Revised September...

Page 292: ...6 5 4 3 2 1 0 RESERVED EV R 0h R Ch Table 4 34 CPUIRQSEL19 Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R Ch Read only selection value Ch GPT2A interrupt event controlled by GPT2 TAMR 292 Interrupts and Events SWCU117C February 20...

Page 293: ...6 5 4 3 2 1 0 RESERVED EV R 0h R Dh Table 4 35 CPUIRQSEL20 Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R Dh Read only selection value Dh GPT2B interrupt event controlled by GPT2 TBMR 293 SWCU117C February 2015 Revised September 2...

Page 294: ...6 5 4 3 2 1 0 RESERVED EV R 0h R Eh Table 4 36 CPUIRQSEL21 Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R Eh Read only selection value Eh GPT3A interrupt event controlled by GPT3 TAMR 294 Interrupts and Events SWCU117C February 20...

Page 295: ...6 5 4 3 2 1 0 RESERVED EV R 0h R Fh Table 4 37 CPUIRQSEL22 Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R Fh Read only selection value Fh GPT3B interrupt event controlled by GPT3 TBMR 295 SWCU117C February 2015 Revised September 2...

Page 296: ...IRQSEL23 Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 5Dh Read only selection value 5Dh CRYPTO result available interrupt event the corresponding flag is found here CRYPTO IRQSTAT RESULT_AVAIL Controlled by CRYPTO IRQSTAT RESULT...

Page 297: ...2 1 0 RESERVED EV R 0h R 27h Table 4 39 CPUIRQSEL24 Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 27h Read only selection value 27h Combined DMA done corresponding flags are here UDMA0 REQDONE 297 SWCU117C February 2015 Revised S...

Page 298: ...5 4 3 2 1 0 RESERVED EV R 0h R 26h Table 4 40 CPUIRQSEL25 Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 26h Read only selection value 26h DMA bus error corresponds to UDMA0 ERROR STATUS 298 Interrupts and Events SWCU117C February...

Page 299: ...h R 15h Table 4 41 CPUIRQSEL26 Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 15h Read only selection value 15h FLASH controller error event the status flags are FLASH FEDACSTAT FSM_DONE and FLASH FEDACSTAT RVF_INT 299 SWCU117C Fe...

Page 300: ...7 6 5 4 3 2 1 0 RESERVED EV R 0h R 64h Table 4 42 CPUIRQSEL27 Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 64h Read only selection value 64h Software event 0 triggered by SWEV SWEV0 300 Interrupts and Events SWCU117C February 20...

Page 301: ...RVED EV R 0h R Bh Table 4 43 CPUIRQSEL28 Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R Bh Read only selection value Bh AUX combined event the corresponding flag register is here AUX_EVCTL EVTOMCUFLAGS 301 SWCU117C February 2015 R...

Page 302: ... R 1h Table 4 44 CPUIRQSEL29 Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 1h Read only selection value 1h AON programmable event 0 Event selected by AON_EVENT MCU event selector AON_EVENT EVTOMCUSEL AON_PROG0_EV 302 Interrupts a...

Page 303: ... UDMA channel 18 see UDMA0 SOFTREQ 5Eh CRYPTO DMA input done event the corresponding flag is CRYPTO IRQSTAT DMA_IN_DONE Controlled by CRYPTO IRQEN DMA_IN_DONE 5Fh RFC RAT event 4 configured by RFC_RAT RATEV OEVT4 60h RFC RAT event 5 configured by RFC_RAT RATEV OEVT5 69h AON wake up event corresponds flags are here AUX_EVCTL EVTOMCUFLAGS AON_WU_EV 6Bh AUX Compare B event corresponds to AUX_EVCTL EV...

Page 304: ...0 RESERVED EV R 0h R 6Ah Table 4 46 CPUIRQSEL31 Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 6Ah Read only selection value 6Ah AUX Compare A event corresponds to AUX_EVCTL EVTOMCUFLAGS AUX_COMPA 304 Interrupts and Events SWCU117...

Page 305: ...able 4 47 CPUIRQSEL32 Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 73h Read only selection value 73h AUX ADC interrupt event corresponds to AUX_EVCTL EVTOMCUFLAGS ADC_IRQ Status flags are found here AUX_EVCTL EVTOMCUFLAGS 305 SW...

Page 306: ...5 4 3 2 1 0 RESERVED EV R 0h R 68h Table 4 48 CPUIRQSEL33 Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 68h Read only selection value 68h TRNG Interrupt event controlled by TRNG IRQEN EN 306 Interrupts and Events SWCU117C Februar...

Page 307: ... 1 0 RESERVED EV R 0h R 3Dh Table 4 49 RFCSEL0 Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 3Dh Read only selection value 3Dh GPT0A compare event Configured by GPT0 TAMR TCACT 307 SWCU117C February 2015 Revised September 2015 In...

Page 308: ... 1 0 RESERVED EV R 0h R 3Eh Table 4 50 RFCSEL1 Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 3Eh Read only selection value 3Eh GPT0B compare event Configured by GPT0 TBMR TCACT 308 Interrupts and Events SWCU117C February 2015 Rev...

Page 309: ... 1 0 RESERVED EV R 0h R 3Fh Table 4 51 RFCSEL2 Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 3Fh Read only selection value 3Fh GPT1A compare event Configured by GPT1 TAMR TCACT 309 SWCU117C February 2015 Revised September 2015 In...

Page 310: ... 1 0 RESERVED EV R 0h R 40h Table 4 52 RFCSEL3 Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 40h Read only selection value 40h GPT1B compare event Configured by GPT1 TBMR TCACT 310 Interrupts and Events SWCU117C February 2015 Rev...

Page 311: ... 1 0 RESERVED EV R 0h R 41h Table 4 53 RFCSEL4 Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 41h Read only selection value 41h GPT2A compare event Configured by GPT2 TAMR TCACT 311 SWCU117C February 2015 Revised September 2015 In...

Page 312: ... 1 0 RESERVED EV R 0h R 42h Table 4 54 RFCSEL5 Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 42h Read only selection value 42h GPT2B compare event Configured by GPT2 TBMR TCACT 312 Interrupts and Events SWCU117C February 2015 Rev...

Page 313: ... 1 0 RESERVED EV R 0h R 43h Table 4 55 RFCSEL6 Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 43h Read only selection value 43h GPT3A compare event Configured by GPT3 TAMR TCACT 313 SWCU117C February 2015 Revised September 2015 In...

Page 314: ... 1 0 RESERVED EV R 0h R 44h Table 4 56 RFCSEL7 Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 44h Read only selection value 44h GPT3B compare event Configured by GPT3 TBMR TCACT 314 Interrupts and Events SWCU117C February 2015 Rev...

Page 315: ...0 RESERVED EV R 0h R 77h Table 4 57 RFCSEL8 Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 77h Read only selection value 77h RTC periodic event controlled by AON_RTC CTL RTC_UPD_EN 315 SWCU117C February 2015 Revised September 2015...

Page 316: ... 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED EV R 0h R W 2h Table 4 58 RFCSEL9 Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 316 Interrupts and Events SWCU117C February 2015 Revised September 2015 Submit Documentation Feedb...

Page 317: ...e event 0 triggered by SWEV SWEV0 65h Software event 1 triggered by SWEV SWEV1 69h AON wake up event corresponds flags are here AUX_EVCTL EVTOMCUFLAGS AON_WU_EV 6Ah AUX Compare A event corresponds to AUX_EVCTL EVTOMCUFLAGS AUX_COMPA 6Bh AUX Compare B event corresponds to AUX_EVCTL EVTOMCUFLAGS AUX_COMPB 6Ch AUX TDC measurement done event corresponds to the flag AUX_EVCTL EVTOMCUFLAGS TDC_DONE and ...

Page 318: ...20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED EV R 0h R W 55h Table 4 59 GPT0ACAPTSEL Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 318 Interrupts and Events SWCU117C February 2015 Revised September 2015 Submit Documentati...

Page 319: ...ART0 MIS 3Dh GPT0A compare event Configured by GPT0 TAMR TCACT 3Eh GPT0B compare event Configured by GPT0 TBMR TCACT 3Fh GPT1A compare event Configured by GPT1 TAMR TCACT 40h GPT1B compare event Configured by GPT1 TBMR TCACT 41h GPT2A compare event Configured by GPT2 TAMR TCACT 42h GPT2B compare event Configured by GPT2 TBMR TCACT 43h GPT3A compare event Configured by GPT3 TAMR TCACT 44h GPT3B com...

Page 320: ...OMCUFLAGS ADC_FIFO_ALMOST_FULL 72h Loopback of OBSMUX0 through AUX corresponds to AUX_EVCTL EVTOMCUFLAGS OBSMUX0 73h AUX ADC interrupt event corresponds to AUX_EVCTL EVTOMCUFLAGS ADC_IRQ Status flags are found here AUX_EVCTL EVTOMCUFLAGS 77h RTC periodic event controlled by AON_RTC CTL RTC_UPD_EN 79h Always asserted 320 Interrupts and Events SWCU117C February 2015 Revised September 2015 Submit Doc...

Page 321: ...20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED EV R 0h R W 56h Table 4 60 GPT0BCAPTSEL Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 321 SWCU117C February 2015 Revised September 2015 Interrupts and Events Submit Documentati...

Page 322: ...ART0 MIS 3Dh GPT0A compare event Configured by GPT0 TAMR TCACT 3Eh GPT0B compare event Configured by GPT0 TBMR TCACT 3Fh GPT1A compare event Configured by GPT1 TAMR TCACT 40h GPT1B compare event Configured by GPT1 TBMR TCACT 41h GPT2A compare event Configured by GPT2 TAMR TCACT 42h GPT2B compare event Configured by GPT2 TBMR TCACT 43h GPT3A compare event Configured by GPT3 TAMR TCACT 44h GPT3B com...

Page 323: ...OMCUFLAGS ADC_FIFO_ALMOST_FULL 72h Loopback of OBSMUX0 through AUX corresponds to AUX_EVCTL EVTOMCUFLAGS OBSMUX0 73h AUX ADC interrupt event corresponds to AUX_EVCTL EVTOMCUFLAGS ADC_IRQ Status flags are found here AUX_EVCTL EVTOMCUFLAGS 77h RTC periodic event controlled by AON_RTC CTL RTC_UPD_EN 79h Always asserted 323 SWCU117C February 2015 Revised September 2015 Interrupts and Events Submit Doc...

Page 324: ...20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED EV R 0h R W 57h Table 4 61 GPT1ACAPTSEL Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 324 Interrupts and Events SWCU117C February 2015 Revised September 2015 Submit Documentati...

Page 325: ...ART0 MIS 3Dh GPT0A compare event Configured by GPT0 TAMR TCACT 3Eh GPT0B compare event Configured by GPT0 TBMR TCACT 3Fh GPT1A compare event Configured by GPT1 TAMR TCACT 40h GPT1B compare event Configured by GPT1 TBMR TCACT 41h GPT2A compare event Configured by GPT2 TAMR TCACT 42h GPT2B compare event Configured by GPT2 TBMR TCACT 43h GPT3A compare event Configured by GPT3 TAMR TCACT 44h GPT3B com...

Page 326: ...OMCUFLAGS ADC_FIFO_ALMOST_FULL 72h Loopback of OBSMUX0 through AUX corresponds to AUX_EVCTL EVTOMCUFLAGS OBSMUX0 73h AUX ADC interrupt event corresponds to AUX_EVCTL EVTOMCUFLAGS ADC_IRQ Status flags are found here AUX_EVCTL EVTOMCUFLAGS 77h RTC periodic event controlled by AON_RTC CTL RTC_UPD_EN 79h Always asserted 326 Interrupts and Events SWCU117C February 2015 Revised September 2015 Submit Doc...

Page 327: ...20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED EV R 0h R W 58h Table 4 62 GPT1BCAPTSEL Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 327 SWCU117C February 2015 Revised September 2015 Interrupts and Events Submit Documentati...

Page 328: ...UART0 MIS 3Dh GPT0A compare event Configured by GPT0 TAMR TCACT 3Eh GPT0B compare event Configured by GPT0 TBMR TCACT 3Fh GPT1A compare event Configured by GPT1 TAMR TCACT 40h GPT1B compare event Configured by GPT1 TBMR TCACT 41h GPT2A compare event Configured by GPT2 TAMR TCACT 42h GPT2B compare event Configured by GPT2 TBMR TCACT 43h GPT3A compare event Configured by GPT3 TAMR TCACT 44h GPT3B co...

Page 329: ...OMCUFLAGS ADC_FIFO_ALMOST_FULL 72h Loopback of OBSMUX0 through AUX corresponds to AUX_EVCTL EVTOMCUFLAGS OBSMUX0 73h AUX ADC interrupt event corresponds to AUX_EVCTL EVTOMCUFLAGS ADC_IRQ Status flags are found here AUX_EVCTL EVTOMCUFLAGS 77h RTC periodic event controlled by AON_RTC CTL RTC_UPD_EN 79h Always asserted 329 SWCU117C February 2015 Revised September 2015 Interrupts and Events Submit Doc...

Page 330: ...20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED EV R 0h R W 59h Table 4 63 GPT2ACAPTSEL Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 330 Interrupts and Events SWCU117C February 2015 Revised September 2015 Submit Documentati...

Page 331: ...ART0 MIS 3Dh GPT0A compare event Configured by GPT0 TAMR TCACT 3Eh GPT0B compare event Configured by GPT0 TBMR TCACT 3Fh GPT1A compare event Configured by GPT1 TAMR TCACT 40h GPT1B compare event Configured by GPT1 TBMR TCACT 41h GPT2A compare event Configured by GPT2 TAMR TCACT 42h GPT2B compare event Configured by GPT2 TBMR TCACT 43h GPT3A compare event Configured by GPT3 TAMR TCACT 44h GPT3B com...

Page 332: ...OMCUFLAGS ADC_FIFO_ALMOST_FULL 72h Loopback of OBSMUX0 through AUX corresponds to AUX_EVCTL EVTOMCUFLAGS OBSMUX0 73h AUX ADC interrupt event corresponds to AUX_EVCTL EVTOMCUFLAGS ADC_IRQ Status flags are found here AUX_EVCTL EVTOMCUFLAGS 77h RTC periodic event controlled by AON_RTC CTL RTC_UPD_EN 79h Always asserted 332 Interrupts and Events SWCU117C February 2015 Revised September 2015 Submit Doc...

Page 333: ...20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED EV R 0h R W 5Ah Table 4 64 GPT2BCAPTSEL Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 333 SWCU117C February 2015 Revised September 2015 Interrupts and Events Submit Documentati...

Page 334: ...ART0 MIS 3Dh GPT0A compare event Configured by GPT0 TAMR TCACT 3Eh GPT0B compare event Configured by GPT0 TBMR TCACT 3Fh GPT1A compare event Configured by GPT1 TAMR TCACT 40h GPT1B compare event Configured by GPT1 TBMR TCACT 41h GPT2A compare event Configured by GPT2 TAMR TCACT 42h GPT2B compare event Configured by GPT2 TBMR TCACT 43h GPT3A compare event Configured by GPT3 TAMR TCACT 44h GPT3B com...

Page 335: ...OMCUFLAGS ADC_FIFO_ALMOST_FULL 72h Loopback of OBSMUX0 through AUX corresponds to AUX_EVCTL EVTOMCUFLAGS OBSMUX0 73h AUX ADC interrupt event corresponds to AUX_EVCTL EVTOMCUFLAGS ADC_IRQ Status flags are found here AUX_EVCTL EVTOMCUFLAGS 77h RTC periodic event controlled by AON_RTC CTL RTC_UPD_EN 79h Always asserted 335 SWCU117C February 2015 Revised September 2015 Interrupts and Events Submit Doc...

Page 336: ... 2 1 0 RESERVED EV R 0h R 31h Table 4 65 UDMACH1SSEL Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 31h Read only selection value 31h UART0 RX DMA single request controlled by UART0 DMACTL RXDMAE 336 Interrupts and Events SWCU117C...

Page 337: ... 2 1 0 RESERVED EV R 0h R 30h Table 4 66 UDMACH1BSEL Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 30h Read only selection value 30h UART0 RX DMA burst request controlled by UART0 DMACTL RXDMAE 337 SWCU117C February 2015 Revised ...

Page 338: ... 2 1 0 RESERVED EV R 0h R 33h Table 4 67 UDMACH2SSEL Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 33h Read only selection value 33h UART0 TX DMA single request controlled by UART0 DMACTL TXDMAE 338 Interrupts and Events SWCU117C...

Page 339: ... 2 1 0 RESERVED EV R 0h R 32h Table 4 68 UDMACH2BSEL Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 32h Read only selection value 32h UART0 TX DMA burst request controlled by UART0 DMACTL TXDMAE 339 SWCU117C February 2015 Revised ...

Page 340: ...3 2 1 0 RESERVED EV R 0h R 29h Table 4 69 UDMACH3SSEL Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 29h Read only selection value 29h SSI0 RX DMA single request controlled by SSI0 DMACR RXDMAE 340 Interrupts and Events SWCU117C F...

Page 341: ...3 2 1 0 RESERVED EV R 0h R 28h Table 4 70 UDMACH3BSEL Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 28h Read only selection value 28h SSI0 RX DMA burst request controlled by SSI0 DMACR RXDMAE 341 SWCU117C February 2015 Revised Se...

Page 342: ...3 2 1 0 RESERVED EV R 0h R 2Bh Table 4 71 UDMACH4SSEL Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 2Bh Read only selection value 2Bh SSI0 TX DMA single request controlled by SSI0 DMACR TXDMAE 342 Interrupts and Events SWCU117C F...

Page 343: ...3 2 1 0 RESERVED EV R 0h R 2Ah Table 4 72 UDMACH4BSEL Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 2Ah Read only selection value 2Ah SSI0 TX DMA burst request controlled by SSI0 DMACR TXDMAE 343 SWCU117C February 2015 Revised Se...

Page 344: ... 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED R 3Ah Table 4 73 UDMACH5SSEL Register Field Descriptions Bit Field Type Reset Description 31 0 RESERVED R 3Ah Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 344 Interrupts and Events SWCU117C February 2015 Revised September 2015 Submit Documentati...

Page 345: ...23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED R 39h Table 4 74 UDMACH5BSEL Register Field Descriptions Bit Field Type Reset Description 31 0 RESERVED R 39h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 345 SWCU117C February 2015 Revised September 2015 Interrupts and Events Submit Documentatio...

Page 346: ... 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED R 3Ch Table 4 75 UDMACH6SSEL Register Field Descriptions Bit Field Type Reset Description 31 0 RESERVED R 3Ch Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 346 Interrupts and Events SWCU117C February 2015 Revised September 2015 Submit Documentati...

Page 347: ...23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED R 3Bh Table 4 76 UDMACH6BSEL Register Field Descriptions Bit Field Type Reset Description 31 0 RESERVED R 3Bh Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 347 SWCU117C February 2015 Revised September 2015 Interrupts and Events Submit Documentatio...

Page 348: ... 1 0 RESERVED EV R 0h R 75h Table 4 77 UDMACH7SSEL Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 75h Read only selection value 75h DMA single request event from AUX configured by AUX_EVCTL DMACTL 348 Interrupts and Events SWCU117...

Page 349: ... 1 0 RESERVED EV R 0h R 76h Table 4 78 UDMACH7BSEL Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 76h Read only selection value 76h DMA burst request event from AUX configured by AUX_EVCTL DMACTL 349 SWCU117C February 2015 Revised...

Page 350: ...18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED EV R 0h R 74h Table 4 79 UDMACH8SSEL Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 74h Read only selection value 74h AUX observation loopback 350 Interrupts and Events SWCU1...

Page 351: ...1 10 9 8 7 6 5 4 3 2 1 0 RESERVED EV R 0h R 74h Table 4 80 UDMACH8BSEL Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 74h Read only selection value 74h AUX observation loopback 351 SWCU117C February 2015 Revised September 2015 Int...

Page 352: ... value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R W 45h Read write selection value 0h Always inactive 45h Not used tied to 0 4Dh GPT0A DMA trigger event Configured by GPT0 DMAEV 4Eh GPT0B DMA trigger event Configured by GPT0 DMAEV 4Fh GPT1A DMA trigger event Configured by GPT1 DMAEV 50h GPT1B DMA trigger event Configured by GPT1 DMAEV 51h G...

Page 353: ...rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R W 4Dh Read write selection value 0h Always inactive 4Dh GPT0A DMA trigger event Configured by GPT0 DMAEV 4Eh GPT0B DMA trigger event Configured by GPT0 DMAEV 4Fh GPT1A DMA trigger event Configured by GPT1 DMAEV 50h GPT1B DMA trigger event Configured by GPT1 DMAEV 51h GPT2A DMA tri...

Page 354: ...he value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R W 46h Read write selection value 0h Always inactive 46h Not used tied to 0 4Dh GPT0A DMA trigger event Configured by GPT0 DMAEV 4Eh GPT0B DMA trigger event Configured by GPT0 DMAEV 4Fh GPT1A DMA trigger event Configured by GPT1 DMAEV 50h GPT1B DMA trigger event Configured by GPT1 DMAEV 51h...

Page 355: ...t rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R W 4Eh Read write selection value 0h Always inactive 4Dh GPT0A DMA trigger event Configured by GPT0 DMAEV 4Eh GPT0B DMA trigger event Configured by GPT0 DMAEV 4Fh GPT1A DMA trigger event Configured by GPT1 DMAEV 50h GPT1B DMA trigger event Configured by GPT1 DMAEV 51h GPT2A DMA t...

Page 356: ...he value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R W 47h Read write selection value 0h Always inactive 47h Not used tied to 0 4Dh GPT0A DMA trigger event Configured by GPT0 DMAEV 4Eh GPT0B DMA trigger event Configured by GPT0 DMAEV 4Fh GPT1A DMA trigger event Configured by GPT1 DMAEV 50h GPT1B DMA trigger event Configured by GPT1 DMAEV 51h...

Page 357: ...t rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R W 4Fh Read write selection value 0h Always inactive 4Dh GPT0A DMA trigger event Configured by GPT0 DMAEV 4Eh GPT0B DMA trigger event Configured by GPT0 DMAEV 4Fh GPT1A DMA trigger event Configured by GPT1 DMAEV 50h GPT1B DMA trigger event Configured by GPT1 DMAEV 51h GPT2A DMA t...

Page 358: ...he value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R W 48h Read write selection value 0h Always inactive 48h Not used tied to 0 4Dh GPT0A DMA trigger event Configured by GPT0 DMAEV 4Eh GPT0B DMA trigger event Configured by GPT0 DMAEV 4Fh GPT1A DMA trigger event Configured by GPT1 DMAEV 50h GPT1B DMA trigger event Configured by GPT1 DMAEV 51h...

Page 359: ...t rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R W 50h Read write selection value 0h Always inactive 4Dh GPT0A DMA trigger event Configured by GPT0 DMAEV 4Eh GPT0B DMA trigger event Configured by GPT0 DMAEV 4Fh GPT1A DMA trigger event Configured by GPT1 DMAEV 50h GPT1B DMA trigger event Configured by GPT1 DMAEV 51h GPT2A DMA t...

Page 360: ... 0h R 3h Table 4 89 UDMACH13BSEL Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 3h Read only selection value 3h AON programmable event 2 Event selected by AON_EVENT MCU event selector AON_EVENT EVTOMCUSEL AON_PROG2_EV 360 Interrup...

Page 361: ...22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED EV R 0h R W 1h Table 4 90 UDMACH14BSEL Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 361 SWCU117C February 2015 Revised September 2015 Interrupts and Events Submit Docume...

Page 362: ...MA done for software triggered UDMA channel 0 see UDMA0 SOFTREQ 15h FLASH controller error event the status flags are FLASH FEDACSTAT FSM_DONE and FLASH FEDACSTAT RVF_INT 16h DMA done for software triggered UDMA channel 18 see UDMA0 SOFTREQ 18h Watchdog interrupt event controlled by WDT CTL INTEN 19h RFC Doorbell Command Acknowledgment Interrupt equivalent to RFC_DBELL RFACKIFG ACKFLAG 1Ah Combine...

Page 363: ...vent Configured by GPT3 TBMR TCACT 4Dh GPT0A DMA trigger event Configured by GPT0 DMAEV 4Eh GPT0B DMA trigger event Configured by GPT0 DMAEV 4Fh GPT1A DMA trigger event Configured by GPT1 DMAEV 50h GPT1B DMA trigger event Configured by GPT1 DMAEV 51h GPT2A DMA trigger event Configured by GPT2 DMAEV 52h GPT2B DMA trigger event Configured by GPT2 DMAEV 53h GPT3A DMA trigger event Configured by GPT3 ...

Page 364: ...nt corresponds flags are here AUX_EVCTL EVTOMCUFLAGS AON_WU_EV 6Ah AUX Compare A event corresponds to AUX_EVCTL EVTOMCUFLAGS AUX_COMPA 6Bh AUX Compare B event corresponds to AUX_EVCTL EVTOMCUFLAGS AUX_COMPB 6Ch AUX TDC measurement done event corresponds to the flag AUX_EVCTL EVTOMCUFLAGS TDC_DONE and the AUX_TDC status AUX_TDC STAT DONE 6Dh AUX timer 0 event corresponds to AUX_EVCTL EVTOMCUFLAGS T...

Page 365: ... 1 0 RESERVED EV R 0h R 7h Table 4 91 UDMACH15BSEL Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 7h Read only selection value 7h Event from AON_RTC controlled by the AON_RTC CTL COMB_EV_MASK setting 365 SWCU117C February 2015 Rev...

Page 366: ...4 3 2 1 0 RESERVED EV R 0h R 2Dh Table 4 92 UDMACH16SSEL Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 2Dh Read only selection value 2Dh SSI1 RX DMA single request controlled by SSI0 DMACR RXDMAE 366 Interrupts and Events SWCU117...

Page 367: ...4 3 2 1 0 RESERVED EV R 0h R 2Ch Table 4 93 UDMACH16BSEL Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 2Ch Read only selection value 2Ch SSI1 RX DMA burst request controlled by SSI0 DMACR RXDMAE 367 SWCU117C February 2015 Revised...

Page 368: ...4 3 2 1 0 RESERVED EV R 0h R 2Fh Table 4 94 UDMACH17SSEL Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 2Fh Read only selection value 2Fh SSI1 TX DMA single request controlled by SSI0 DMACR TXDMAE 368 Interrupts and Events SWCU117...

Page 369: ...4 3 2 1 0 RESERVED EV R 0h R 2Eh Table 4 95 UDMACH17BSEL Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 2Eh Read only selection value 2Eh SSI1 TX DMA burst request controlled by SSI0 DMACR TXDMAE 369 SWCU117C February 2015 Revised...

Page 370: ... 8 7 6 5 4 3 2 1 0 RESERVED EV R 0h R 64h Table 4 96 UDMACH21SSEL Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 64h Read only selection value 64h Software event 0 triggered by SWEV SWEV0 370 Interrupts and Events SWCU117C Februar...

Page 371: ...8 7 6 5 4 3 2 1 0 RESERVED EV R 0h R 64h Table 4 97 UDMACH21BSEL Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 64h Read only selection value 64h Software event 0 triggered by SWEV SWEV0 371 SWCU117C February 2015 Revised Septembe...

Page 372: ... 8 7 6 5 4 3 2 1 0 RESERVED EV R 0h R 65h Table 4 98 UDMACH22SSEL Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 65h Read only selection value 65h Software event 1 triggered by SWEV SWEV1 372 Interrupts and Events SWCU117C Februar...

Page 373: ...8 7 6 5 4 3 2 1 0 RESERVED EV R 0h R 65h Table 4 99 UDMACH22BSEL Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 65h Read only selection value 65h Software event 1 triggered by SWEV SWEV1 373 SWCU117C February 2015 Revised Septembe...

Page 374: ... 8 7 6 5 4 3 2 1 0 RESERVED EV R 0h R 66h Table 4 100 UDMACH23SSEL Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 66h Read only selection value 66h Software event 2 triggered by SWEV SWEV2 374 Interrupts and Events SWCU117C Februa...

Page 375: ...8 7 6 5 4 3 2 1 0 RESERVED EV R 0h R 66h Table 4 101 UDMACH23BSEL Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 66h Read only selection value 66h Software event 2 triggered by SWEV SWEV2 375 SWCU117C February 2015 Revised Septemb...

Page 376: ... 8 7 6 5 4 3 2 1 0 RESERVED EV R 0h R 67h Table 4 102 UDMACH24SSEL Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 67h Read only selection value 67h Software event 3 triggered by SWEV SWEV3 376 Interrupts and Events SWCU117C Februa...

Page 377: ...8 7 6 5 4 3 2 1 0 RESERVED EV R 0h R 67h Table 4 103 UDMACH24BSEL Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 67h Read only selection value 67h Software event 3 triggered by SWEV SWEV3 377 SWCU117C February 2015 Revised Septemb...

Page 378: ...20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED EV R 0h R W 5Bh Table 4 104 GPT3ACAPTSEL Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 378 Interrupts and Events SWCU117C February 2015 Revised September 2015 Submit Documentat...

Page 379: ...nt Configured by GPT0 TAMR TCACT 3Eh GPT0B compare event Configured by GPT0 TBMR TCACT 3Fh GPT1A compare event Configured by GPT1 TAMR TCACT 40h GPT1B compare event Configured by GPT1 TBMR TCACT 41h GPT2A compare event Configured by GPT2 TAMR TCACT 42h GPT2B compare event Configured by GPT2 TBMR TCACT 43h GPT3A compare event Configured by GPT3 TAMR TCACT 44h GPT3B compare event Configured by GPT3 ...

Page 380: ...FO_ALMOST_FULL 72h Loopback of OBSMUX0 through AUX corresponds to AUX_EVCTL EVTOMCUFLAGS OBSMUX0 73h AUX ADC interrupt event corresponds to AUX_EVCTL EVTOMCUFLAGS ADC_IRQ Status flags are found here AUX_EVCTL EVTOMCUFLAGS 77h RTC periodic event controlled by AON_RTC CTL RTC_UPD_EN 79h Always asserted 380 Interrupts and Events SWCU117C February 2015 Revised September 2015 Submit Documentation Feedb...

Page 381: ... 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED EV R 0h R W 5Ch Table 4 105 GPT3BCAPTSEL Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 381 SWCU117C February 2015 Revised September 2015 Interrupts and Events Submit Documenta...

Page 382: ...nt Configured by GPT0 TAMR TCACT 3Eh GPT0B compare event Configured by GPT0 TBMR TCACT 3Fh GPT1A compare event Configured by GPT1 TAMR TCACT 40h GPT1B compare event Configured by GPT1 TBMR TCACT 41h GPT2A compare event Configured by GPT2 TAMR TCACT 42h GPT2B compare event Configured by GPT2 TBMR TCACT 43h GPT3A compare event Configured by GPT3 TAMR TCACT 44h GPT3B compare event Configured by GPT3 ...

Page 383: ...FO_ALMOST_FULL 72h Loopback of OBSMUX0 through AUX corresponds to AUX_EVCTL EVTOMCUFLAGS OBSMUX0 73h AUX ADC interrupt event corresponds to AUX_EVCTL EVTOMCUFLAGS ADC_IRQ Status flags are found here AUX_EVCTL EVTOMCUFLAGS 77h RTC periodic event controlled by AON_RTC CTL RTC_UPD_EN 79h Always asserted 383 SWCU117C February 2015 Revised September 2015 Interrupts and Events Submit Documentation Feedb...

Page 384: ...ny other value than the reset value may result in undefined behavior 6 0 EV R W 10h Read write selection value 0h Always inactive Ch GPT2A interrupt event controlled by GPT2 TAMR Dh GPT2B interrupt event controlled by GPT2 TBMR Eh GPT3A interrupt event controlled by GPT3 TAMR Fh GPT3B interrupt event controlled by GPT3 TBMR 10h GPT0A interrupt event controlled by GPT0 TAMR 11h GPT0B interrupt even...

Page 385: ... 0 RESERVED EV R 0h R 63h Table 4 107 CM3NMISEL0 Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R 63h Read only selection value 63h Watchdog non maskable interrupt event controlled by WDT CTL INTTYPE 385 SWCU117C February 2015 Revis...

Page 386: ...e Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R W 5Fh Read write selection value 0h Always inactive 5Fh RFC RAT event 4 configured by RFC_RAT RATEV OEVT4 60h RFC RAT event 5 configured by RFC_RAT RATEV OEVT5 61h RFC RAT event 6 configured by RFC_RAT RATEV OEVT6 62h RFC RA...

Page 387: ...2 1 0 RESERVED EV R 0h R W 78h Table 4 109 FRZSEL0 Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 EV R W 78h Read write selection value 0h Always inactive 78h CPU halted 79h Always asserted 387 SWCU117C February 2015 Revised September ...

Page 388: ... triggers the Software 3 event 23 17 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 16 SWEV2 R W 0h Writing 1 to this bit when the value is 0 triggers the Software 2 event 15 9 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undef...

Page 389: ...Level Debug System 391 5 2 cJTAG 394 5 3 ICEPick 399 5 4 ICEMelter 409 5 5 Serial Wire Viewer SWV 409 5 6 Halt In Boot HIB 410 5 7 Debug and Shutdown 410 5 8 Debug Features Supported Through WUC TAP 411 5 9 Profiler Register 412 389 SWCU117C February 2015 Revised September 2015 JTAG Interface Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 390: ...rd Test Access Port and Boundary Scan Architecture Test Access Port TAP 1 This standard is known by the acronym JTAG Class 4 IEEE 1149 7 Standard for Reduced pin and Enhanced functionality Test Access Port and Boundary scan Architecture 2 This is known by acronym cJTAG compact JTAG This standard serializes the IEEE 1149 1 transactions using a variety of compression formats to reduce the number of ...

Page 391: ...ck control status TDI DIO 1149 1 1149 1 1149 1 1149 1 Standby Wakeup TDI MCU voltage domain AON voltage domain CPU status power reset clock control TDO DIO www ti com Top Level Debug System Figure 5 1 Top Level Debug System 391 SWCU117C February 2015 Revised September 2015 JTAG Interface Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 392: ...te machine is in the correct state TDO Test Data Out This signal represents the data shifted out of the test or programming logic of the device and is valid on the falling edge of TCK when the internal state machine is in the correct state There is no dedicated I O pin for TRST The debug subsystem is reset with system wide resets and power on reset The TAP controller a state machine whose transiti...

Page 393: ...ommands Class 2 Adds serial select capability Class 3 Adds JTAG star configuration controller IDs and scan selection directives Class 4 Adds advanced scan protocols Table 5 2 lists the features in IEEE 1149 7 that are supported in CC26xx and CC13xx devices The cJTAG module in the CC26xx and CC13xx devices supports 12 scan formats The scan formats use a variety of compression protocols ranging from...

Page 394: ...can6 Yes Bidirectional transfers pipelined OScan7 Yes Host to target only pipelined SScan0 No Segmented scan SScan1 No Segmented scan supports stalls SScan2 No Segmented scan SScan3 No Segmented scan supports stalls Table 5 3 OScan Scan Packet Contents Scan Nonshift States Shift States Format OScan0 nTDI TMS RDY TDO nTDI TMS RDY TDO OScan1 nTDI TMS TDO nTDI TMS TDO OScan2 TMS nTDI TMS TDO OScan3 T...

Page 395: ...cans and sometimes a third DR scan The number of clocks spent in the Shift DR state is counted for each scan from 0 to 31 clocks The first DR scan command part 0 CP0 forms the opcode of the command The second DR scan command part 1 CP1 provides additional information about the command This may be more opcode bits or a data field depending upon the opcode There are three commands SCNB SCNS and CIDA...

Page 396: ...The pin function becomes the standard pin function APFC 1x The pin function becomes the auxiliary pin function 2 C 0 APFC vv 1 APFC vv if CGM 1 3 Reserved STFMT Store Scan Format Operand nnnnn nnnnn 0 JSCAN0 1 JSCAN1 2 JSCAN2 3 JSCAN3 4 7 Reserved 8 OSCAN0 00011 9 OSCAN1 10 OSCAN2 11 OSCAN3 12 OSCAN4 13 OSCAN5 14 OSCAN6 15 OSCAN7 16 31 Reserved MSS Make Scan Selection Operand miiii m 00100 SGC bit...

Page 397: ... Programming Sequences 5 2 2 1 Opening Command Window Before the cJTAG module accepts any commands the control level must be set to 2 and locked 1 Scan IR bypass end in Pause DR Load benign opcode into the instruction register 2 Goto Scan through Update DR end in Pause DR This is the first ZBS 3 Goto Scan through Update DR end in Pause DR This is the second ZBS 4 Scan DR 1 bit end in Pause DR This...

Page 398: ...ol bits are associated with each secondary TAP within ICEPick Some of these bits apply strictly to the TAP being managed by ICEPick while others apply to the whole subsystem or power domain in which the secondary TAP resides These control bits deal with the TAP selection for inclusion in the scan path secondary TAP test reset management and debug attention needed A number of status bits are associ...

Page 399: ...ve DAP CPU DAP The debug subsystem has only one slave DAP CPU DAP This debug port implements Serial Wire JTAG Debug Port SWJ DP interface which allows external access to an Advanced High performance Bus Access Port AHB AP interface for debug accesses in the CPU The SWJ DP is a standard ARM CoreSight debug port that combines JTAG DP and Serial Wire Debug Port SW DP Even though the SW DP interface i...

Page 400: ...st TAP Secondary Test TAP Register STTR 24 6 instantiated It is used to control STTR selection of each TAP Reserved SUTR 24 1 Reserved Specifies how ICEPick manages the Linking Mode LMR 24 1 TAP selection ICEPick Control IPCR 24 1 General ICEPick control 5 3 2 1 IR Instructions The ICEPick TAP supports the instructions listed in Table 5 7 All unused TAP controller instructions default to the bypas...

Page 401: ...sertion points based on the current TAP state or value in the instruction register 5 3 2 3 Instruction Register This register contains the current TAP instruction The ICEPick IR is 6 bits wide Figure 5 5 Instruction Register See Table 5 7 for valid IR opcodes 5 3 2 4 Bypass Register This register is a 1 bit register Whatever value is scanned in TDI is preserved and scanned out of TDO one TCK cycle...

Page 402: ...r details of this register Figure 5 8 User Code Register Table 5 9 User Code Register Description Field Width Description Revision of the device This field must change each time Version 4 that the logic or mask set of the device is revised The initial value is 0 Variant of chip The decoding of this field is shown in Variant Number 16 FCFG1 USER_ID Reserved 11 0 0 1 Bit 0 is always 1 5 3 2 7 ICEPic...

Page 403: ...to Table 5 12 for more information Figure 5 11 ROUTER DR Scan Chain Table 5 12 ROUTER DR Scan Chain Description Bit Field Width Type Reset Description On scan in 0 Only a read is performed 1 A write to the specified register is performed On scan out If the previous scan resulted in a write to a ROUTER addressed register then when bit 31 is scanned out during the next trip through the Shift DR stat...

Page 404: ...sed and the write failure flag is set to 1 The write failure bit is captured into the Data Shift Register at bit 31 When the value has been captured the WF flag is cleared If bit 31 indicates that a read must be performed the ICEPick register specified is not touched at this point The ICEPick register contents remain undisturbed If the contents of the Data Shift Register remain constant until the ...

Page 405: ...reset requested Writing a 0 has no effect 5 3 4 1 3 Linking Mode Register Table 5 16 ICEPick Linking Mode Register Bit Field Width Type Reset Description 23 4 Reserved 20 R W 0x0 Reserved 3 1 TAPLinkMode 3 R W 0 See Table 5 17 0 ActivateMode 1 R W 0 When a 1 is written to this bit the currently selected TAPLinkMode is activated ICEPick links the TAPs according to these settings when the ICEPick TA...

Page 406: ... Table 5 19 STTR Secondary Test TAP Register Bit Field Width Type Reset Description 23 10 Reserved 14 R W 0 Reserved 9 VisibleTAP 1 R SeeTable 5 21 8 SelectTAP 1 R W 0 SeeTable 5 21 7 2 Reserved 6 R 0 1 TapAccessible 1 R SeeTable 5 21 0 TapPresent 1 R SeeTable 5 21 5 3 4 3 Debug TAP Linking Block The Debug TAP Linking block contains the control and status registers used in the selection of seconda...

Page 407: ...bleTap bit indicates that the TAP which was 9 VisibleTAP 1 R previously selected with the SelectTap bit is now part of the device master scan path The VisibleTap bit is set by ICEPick when the Run Test Idle state has been reached The SelectTap bit allows scan controller software to change which secondary TAPs are included in the device level master scan path When this bit is set to 1 the TAP is se...

Page 408: ... before sending remaining commands to JTAG interface 5 5 Serial Wire Viewer SWV The CPU uses the TPIU macro inside the processor to support the serial wire viewer SWV interface a single line interface The following sequence is needed to enable SWV output on the CPU 1 Enable trace system by setting CPU_SCS DEMCR TRCENA see Section 2 7 4 59 DEMCR Register Offset DFCh reset X 2 Unlock ITM configurati...

Page 409: ...to 1 To exit HIB the external emulator must connect to the device and first HALT then RESUME the CPU through DAP After resuming the program execution continues from the application code 5 7 Debug and Shutdown The debugger cannot stay connected in shutdown mode because the power source for debug subsystem turns off in this mode This means that entering shutdown causes abrupt disconnection from the ...

Page 410: ...it requests reset of the entire chip The DEBUGEN bit IR 0x01 SYS_RESET_REQ remains asserted after this reset which ensures HIB after next Bit 7 in DR 7 0 boot IR 0x0C TMS_PAD_CFG Strength and slew control setting for TMS pad Bits 5 0 in DR 6 0 IR 0x0C 1 If MCU VD is off Force Active powers up the MCU VD MCU_VD_FORCE_ACTIVE Bit 6 in DR 6 0 0 The application controls the MCU VD 1 Prevent JTAG power ...

Page 411: ... 26 4 Reserved AUX power domain state 00 Off 25 24 2 01 Power down 10 Reserved 11 Active State of the sensor controller in the AUX power domain 23 1 0 Suspend 1 Running MCU_VD state 00 Off 22 21 2 01 Power down 10 Reserved 11 Active 1 CPU power domain is on 20 1 0 CPU power domain is off 1 SERIAL power domain is on 19 1 0 SERIAL power domain is off 1 PERIPH power domain is on 18 1 0 PERIPH power d...

Page 412: ...tails the flexible power management and clock control PRCM of the CC26xx and CC13xx devices Topic Page 6 1 Introduction 414 6 2 PRCM Registers 432 412 Power Reset and Clock Management SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 413: ...consumption requires the longest time from initiation to power saving mode as well as wake up time back to active mode Table 6 1 summarizes the power saving features Table 6 1 Power Saving Features Power Saving Feature Description Immediate response no latency Clock gating Offers the least amount of power saved Power domain off Power cycling down and up takes longer time than clock gating Modules ...

Page 414: ...ystem CPU mode so it is important to understand what this means The system CPU has three different operation modes run mode and deepsleep see Table 6 3 Each mode is used to gate internal clocks in the system CPU in addition to peripheral clocks that may be gated in accordance to the current system CPU mode Deepsleep mode is in some cases one of several requirements for powering down voltage and po...

Page 415: ... PRCM PDCTL0 SERIAL_ON PERIPH_PD is SW controlled by PRCM PDCTL0 PERIPH_ON JTAG_PD is SW controlled by AON_WUC JTAGCFG JTAG_PD_FORCE_ON AUX_PD is powered on by AON_WUC AUXCTL AUX_FORCE_ON 1 For power off see AUX section Modules in AON is always powered when CC26xx is not in shutdown mode MCU_VD is controlled by AON_WUC MCUCFG and AON_EVENT MCUWUSEL LDO selected by PRCM VDCTL ULDO Legend www ti com...

Page 416: ... to the VDDR_RF pin The Global LDO must be decoupled by a µF sized capacitor on the VDDR net 6 1 2 2 External Regulator Mode The CC26xx and CC13xx devices have an option to be supplied by an external regulator with a voltage range of 1 65 V to 1 95 V In this mode the VDDS and VDDR pins are tied together To enable external regulator mode the VDDS_DCDC pin and the DCDC_SW pins must be connected to g...

Page 417: ...ontroller Edge detect AON IO mux I O state holder Power SYS CTL MCU Wakeup AUX Wakeup Event Event fabric Peripherals RTC AON Voltage domain Always on logic Power domain Module with retention Module no retention Memory Legend www ti com Introduction 6 1 3 Digital Power Partitioning The CC26xx and CC13xx devices have two voltage domains MCU_VD and AON_VD Both voltage domains contain multiple power d...

Page 418: ...iption of PRCM VDCTL MCU_VD see Section 6 2 4 4 VDCTL Register Offset Ch reset X 6 1 3 1 1 MCU_VD Power Domains Figure 6 2 shows control of MCU_VD power domains and provides descriptions of the registers 6 1 3 2 AON_VD AON_VD contains two power domains and always on logic marked AON in Figure 6 3 Logic in AON is always powered when the CC26xx and CC13xx devices are not in shutdown mode 6 1 3 2 1 A...

Page 419: ...tor Standby Selectable in DDI_0_OSC CTL0 SCLK_LF_SRC_SEL High frequency clock 48 MHz derived from 48 MHz RC oscillator Used by MCU_VD in active and idle 48 MHz derived from 24 MHz XTAL oscillator doubled SCLK_HF modes internally Used by AUX_PD in active mode Selectable in DDI_0_OSC CTL0 SCLK_HF_SRC_SEL Used for low power comparator in SCLK_LF_AUX Same as SCLK_LF AUX_PD COMP_B ACLK_ADC Used as cloc...

Page 420: ... DDI_0_OSC CTL0 ACLK_TDC_SRC_SEL RCOSC 48 MHz 0 1 2 3 XTAL 24 MHz Unused ACLK_TDC 1536 DDI_0_OSC CTL0 SCLK_LF_SRC_SEL 768 XTAL 48 MHz RCOSC 48 MHz RCOSC 32 kHz XTAL 32 768 kHz 0 1 2 3 ACLK_REF ACLK_ADC SCLK_LF_AUX x 2 2 Introduction www ti com Figure 6 5 System Clock Muxing 420 Power Reset and Clock Management SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 20...

Page 421: ...uire bus access The SYSBUS clock may run even when the system CPU is in deepsleep mode when either DMA SEC or RFCORE needs an active interconnect MCU_AON has two clocks an INFRASTRUCTURE clock that always runs and a PERBUSULL clock that is identical to the INFRASTRUCTURE clock whenever the SYSBUS clock is running When the SYSBUS clock is gated the PERBUSULL clock is automatically gated INFRASTRUCT...

Page 422: ...olled by system CPU mode and PRCM I2CCLKGR S DS CLK_EN Conditional clock gate Controlled by system CPU mode and PRCM UARTCLKGR S DS CLK_EN Conditional clock gate Controlled by system CPU mode and PRCM SSICLKGR S DS CLK_EN Conditional clock gate Controlled by system CPU mode and PRCM I2SCLKGR S DS CLK_EN DMA controller CRYPTO core GPT 3 0 GPIO True random number gen SSI1 I2S UART SSI0 I C 2 SYSBUS ...

Page 423: ...use power cycling of a power domain overrides clock gate registers disabling the module clocks before powering down a power domain is not required 6 1 4 2 2 Scalar to GPTs A scalar to GPTs is available to enable GPTs to count at a slower frequency than SYSBUS clock The setting in the PRCM GPTCLKDIV register is valid for all GPTs in the system 6 1 4 2 3 Scalar to WDT There is a scalar with a fixed ...

Page 424: ...y system On On Duty cycled Off Off Application Current Application dependent 1 µA 0 1 µA 0 1 µA dependent Time from CPU active to ready for TBD TBD TBD Wakeup 2 Wakeup time to 25 µs 300 µs 3 1 5 ms 1 5 ms CPU active 2 XOSC_HF or XOSC_HF or High speed clock Off Off Off RCOSC_HF RCOSC_HF XOSC_LF or XOSC_LF or XOSC_LF or Low speed clock Off Off RCOSC_LF RCOSC_LF RCOSC_LF Wakeup on RTC Available Avail...

Page 425: ...is powered including BUS_PD and VIMS_PD see Figure 6 2 In active mode all modules are available and power consumption is highly application dependent Power saving features are Enable the DC DC converter Power only the necessary power domains Enable only the necessary module clocks NOTE Wake up time for a power domain in the CC26xx and CC13xx devices requires approximately 15 µs Because clock gatin...

Page 426: ...output pins see Table 6 6 All parts in MCU_VD with retention as shown in Figure 6 3 are retained in standby mode All other logic in MCU_VD must be reconfigured after wake up from Standby mode Sensor controller is available in autonomous mode when the CC26xx and CC13xx devices are in standby mode Possible wake up sources are events from I O JTAG RTC and the sensor processor The following are prereq...

Page 427: ...No clock No Configure system SRAM retention AON_WUC MCUCFG SRAM_RET_EN Default Retention enabled Turn off JTAG AON_WUC JTAGCFG JTAG_PD_FORCE_ON Yes Configure the wake up source to IOC IOCFG AON_RTC AUX Yes generate an event Request AUX_PD power down AUX_WUC PWRDWNREQ REQ Yes Disconnect AUX from system bus AUX_WUC MCUBUSCTL DISCONNECT_REQ Yes Latch I O state AON_IOC IOCLATCH EN Yes PRCM PDCTL0 Turn...

Page 428: ... VDCTL MCU_VD Yes Synchronize transactions to AON AON_RTC SYNC Yes Read register domain Set the system CPU SLEEPDEEP CPU_SCS SCR SLEEPDEEP Yes bit Stop the system CPU to start the WFI or WFE Yes power down sequence 6 1 6 Reset The CC26xx and CC13xx devices have several sources of reset some are triggered due to errors or unexpected behavior while others are user initiated Resets may result in rese...

Page 429: ... warm reset A warm reset leaves all analog configurations unchanged while the system CPU and all other digital modules in MCU_VD are reset The following sources initiate a warm reset generation The CPU_SCS AIRCR SYSRESETREQ register System CPU LOCKUP Watchdog time out When a warm reset source is triggered MCU_VD is reset through a controlled sequence returning MCU_VD to the same state as when fini...

Page 430: ...UX_PD Reset of AUX_PD can be done by writing to the AON_WUC AUXCTL RESET_REQ register 430 Power Reset and Clock Management SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 431: ...nsation Threashold 1 Section 6 2 1 5 14h AMPCOMPTH2 Amplitude Compensation Threashold 2 Section 6 2 1 6 18h ANABYPASSVAL1 Analog Bypass Values 1 Section 6 2 1 7 1Ch ANABYPASSVAL2 Analog Bypass Values 2 Section 6 2 1 8 20h ATESTCTL Analog Test Control Section 6 2 1 9 24h ADCDOUBLERNANOAMPCTL ADC Doubler Nanoamp Control Section 6 2 1 10 28h XOSCHFCTL XOSCHF Control Section 6 2 1 11 2Ch LFOSCCTL Low ...

Page 432: ...be used through TI provided API K_QUAL 27 26 DOUBLER_START_DUR R W 0h Internal Only to be used through TI provided API ATION 25 DOUBLER_RESET_DUR R W 0h Internal Only to be used through TI provided API ATION 24 23 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 22 FORCE_KICKSTART_EN R W 0h Internal Only...

Page 433: ...in step 1 above This provides a faster clock change 9 CLK_LOSS_EN R W 0h Enable clock loss circuit and hence the indicators to system controller Checks both SCLK_HF and SCLK_LF clock loss indicators 0 Disable 1 Enable Clock loss detection must be disabled when changing the sclk_lf source STAT0 SCLK_LF_SRC can be polled to determine when a change to a new sclk_lf source has completed 8 7 ACLK_TDC_S...

Page 434: ...eset Description 31 23 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 22 18 RCOSCHFCTRIMFRACT R W 0h Internal Only to be used through TI provided API 17 RCOSCHFCTRIMFRACT R W 0h Internal Only to be used through TI provided API _EN 16 2 SPARE2 R W 0h Software must not rely on the value of a reserved Wri...

Page 435: ...d Type Reset Description 31 22 HPM_IBIAS_WAIT_CNT R W 0h Internal Only to be used through TI provided API 21 16 LPM_IBIAS_WAIT_CNT R W 0h Internal Only to be used through TI provided API 15 12 IDAC_STEP R W 0h Internal Only to be used through TI provided API 11 6 RADC_DAC_TH R W 0h Internal Only to be used through TI provided API 5 RADC_MODE_IS_SAR R W 0h Internal Only to be used through TI provid...

Page 436: ... W 0h Internal Only to be used through TI provided API 29 28 AMPCOMP_FSM_UPDAT R W 0h Internal Only to be used through TI provided API E_RATE 27 AMPCOMP_SW_CTRL R W 0h Internal Only to be used through TI provided API 26 AMPCOMP_SW_EN R W 0h Internal Only to be used through TI provided API 25 24 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset...

Page 437: ... Type Reset Description 31 24 SPARE24 R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 23 18 HPMRAMP3_LTH R W 0h Internal Only to be used through TI provided API 17 16 SPARE16 R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 15 ...

Page 438: ...he value of a reserved Writing any other value than the reset value may result in undefined behavior 23 18 LPMUPDATE_HTH R W 0h Internal Only to be used through TI provided API 17 16 SPARE16 R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 15 10 ADC_COMP_AMPTH_LP R W 0h Internal Only to be used through TI provide...

Page 439: ...HF_COLUMN_Q12 R W 0h Table 6 15 ANABYPASSVAL1 Register Field Descriptions Bit Field Type Reset Description 31 20 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 19 16 XOSC_HF_ROW_Q12 R W 0h Internal Only to be used through TI provided API 15 0 XOSC_HF_COLUMN_Q1 R W 0h Internal Only to be used through TI...

Page 440: ... 2 1 0 RESERVED XOSC_HF_IBIASTHERM R W 0h R W 0h Table 6 16 ANABYPASSVAL2 Register Field Descriptions Bit Field Type Reset Description 31 14 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 13 0 XOSC_HF_IBIASTHERM R W 0h Internal Only to be used through TI provided API 440 Power Reset and Clock Managemen...

Page 441: ...ATESTCTL Register Field Descriptions Bit Field Type Reset Description 31 30 SPARE30 R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 29 SCLK_LF_AUX_EN R W 0h Enable 32 kHz clock to AUX_COMPB 28 0 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may res...

Page 442: ...t in undefined behavior 24 NANOAMP_BIAS_ENABL R W 0h Internal Only to be used through TI provided API E 23 SPARE23 R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 22 6 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 5...

Page 443: ... value than the reset value may result in undefined behavior 9 8 PEAK_DET_ITRIM R W 0h Internal Only to be used through TI provided API 7 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 BYPASS R W 0h Internal Only to be used through TI provided API 5 RESERVED R W 0h Software must not rely on the value...

Page 444: ...must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 23 22 XOSCLF_REGULATOR_ R W 0h Internal Only to be used through TI provided API TRIM 21 18 XOSCLF_CMIRRWR_RA R W 0h Internal Only to be used through TI provided API TIO 17 10 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset v...

Page 445: ...tions Bit Field Type Reset Description 31 16 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 15 8 RCOSCHF_CTRIM R W 0h Internal Only to be used through TI provided API 7 0 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefin...

Page 446: ...equency clock derived from High Frequency RCOSC 1h Low frequency clock derived from High Frequency XOSC 2h Low frequency RCOSC 3h Low frequency XOSC 28 SCLK_HF_SRC R 0h Indicates source for the sclk_hf 0h High frequency RCOSC clk 1h High frequency XOSC 27 23 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior...

Page 447: ...BUF_EN R 0h XOSC_HF_HP_BUF_EN 9 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 8 ADC_THMET R 0h ADC_THMET 7 ADC_DATA_READY R 0h indicates when adc_data is ready 6 1 ADC_DATA R 0h adc_data 0 PENDINGSCLKHFSWITC R 0h Indicates when sclk_hf is ready to be swtiched HING 447 SWCU117C February 2015 Revised Sept...

Page 448: ...AMPSTATE R 0h AMPCOMP FSM State 0h RESET 1h INITIALIZATION 2h HPM_RAMP1 3h HPM_RAMP2 4h HPM_RAMP3 5h HPM_UPDATE 6h IDAC_INCREMENT 7h IBIAS_CAP_UPDATE 8h IBIAS_DECREMENT_WITH_MEASURE 9h LPM_UPDATE Ah IBIAS_INCREMENT Bh IDAC_DECREMENT_WITH_MEASURE Ch DUMMY_TO_INIT_1 Dh FAST_START Eh FAST_START_SETTLE 27 22 HMP_UPDATE_AMP R 0h OSC amplitude during HPM_UPDATE state The vaue is an unsigned interger It ...

Page 449: ..._MF_GOOD 5 SCLK_LF_GOOD R 0h SCLK_LF_GOOD 4 ACLK_ADC_GOOD R 0h ACLK_ADC_GOOD 3 ACLK_TDC_GOOD R 0h ACLK_TDC_GOOD 2 ACLK_REF_GOOD R 0h ACLK_REF_GOOD 1 CLK_CHP_GOOD R 0h CLK_CHP_GOOD 0 CLK_DCDC_GOOD R 0h CLK_DCDC_GOOD 449 SWCU117C February 2015 Revised September 2015 Power Reset and Clock Management Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 450: ...et for hpm_ramp2 23 HPM_RAMP3_THMET R 0h Indication of threshhold is met for hpm_ramp3 22 16 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 15 12 RAMPSTATE R 0h xosc_hf amplitude compensation FSM This is identical to STAT1 RAMPSTATE See that description for encoding 11 4 RESERVED R 0h Software must not r...

Page 451: ...ations and the register contents must not be modified Table 6 25 AON_SYSCTL Registers Offset Acronym Register Name Section 0h PWRCTL Power Management Section 6 2 2 1 4h RESETCTL Reset Management Section 6 2 2 2 8h SLEEPCTL Sleep Mode Section 6 2 2 3 451 SWCU117C February 2015 Revised September 2015 Power Reset and Clock Management Submit Documentation Feedback Copyright 2015 Texas Instruments Inco...

Page 452: ...ype Reset Description 31 3 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 2 DCDC_ACTIVE R W 0h Select to use DCDC regulator for VDDR in active mode 0 Use GLDO for regulation of VDDRin active mode 1 Use DCDC for regulation of VDDRin active mode 1 EXT_REG_MODE R 0h Status of source for VDDRsupply 0 DCDC ...

Page 453: ...eset Appears as SYSRESET in RESET_SRC 30 26 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 25 BOOT_DET_1_CLR R W 0h Internal Only to be used through TI provided API 24 BOOT_DET_0_CLR R W 0h Internal Only to be used through TI provided API 23 18 RESERVED R 0h Software must not rely on the value of a reser...

Page 454: ...DD_LOSS_EN 1 1 Brown out detect of VDD generates system reset regardless of VDD_LOSS_EN This bit can be locked 8 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 7 VDDS_LOSS_EN R W 1h Controls reset generation in case VDDS is lost 0 Brown out detect of VDDS is ignored unless VDDS_LOSS_EN_OVR 1 1 Brown out ...

Page 455: ...ource being released If a new reset source is triggered in a window of four 32 kHz periods after the previous has been released this register may indicate Power on reset as source 0h Power on reset 1h Reset pin 2h Brown out detect on VDDS 3h Brown out detect on VDD 4h Brown out detect on VDDR 5h Clock loss detect 6h Software reset via SYSRESET register 7h Software reset via PRCM warm reset request...

Page 456: ... RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 IO_PAD_SLEEP_DIS R W 0h Controls the I O pad sleep mode The boot code will set this bitfield automatically unless waking up from a SHUTDOWN RESETCTL WU_FROM_SD is set 0 I O pad sleep mode is enabled ie all pads are latched and can not toggle 1 I O pad sle...

Page 457: ...G AUX Configuration Section 6 2 3 4 10h AUXCTL AUX Control Section 6 2 3 5 14h PWRSTAT Power Status Section 6 2 3 6 18h SHUTDOWN Shutdown Control Section 6 2 3 7 20h CTL0 Control 0 Section 6 2 3 8 24h CTL1 Control 1 Section 6 2 3 9 30h RECHARGECFG Recharge Controller Configuration Section 6 2 3 10 34h RECHARGESTAT Recharge Controller Status Section 6 2 3 11 38h OSCCFG Oscillator Configuration Sect...

Page 458: ...behavior 2 RCOSC_HF_CAL_DONE R W 0h MCU bootcode will set this bit when RCOSC_HF is calibrated The FLASH can not be used until this bit is set 1 RCOSC_HF is calibrated to 48 MHz allowing FLASH to power up 0 RCOSC_HF is not yet calibrated ie FLASH must not assume that the SCLK_HF is safe 1 0 PWR_DWN_SRC R W 0h Controls the clock source for the entire MCU domain while MCU is requesting powerdown Whe...

Page 459: ...K_HF as source then WUC will switch over to this clock source during powerdown and automatically switch back to SCLK_HF when AUX system is back in active mode 0h No clock in Powerdown 1h Use SCLK_LF in Powerdown 10 8 SCLK_HF_DIV R W 0h Select the AUX clock divider for SCLK_HF NB It is not supported to change the AUX clock divider while SCLK_HF is active source for AUX 0h Divide by 2 1h Divide by 4...

Page 460: ...ult in undefined behavior 17 VIRT_OFF R W 0h Internal Only to be used through TI provided API 16 FIXED_WU_EN R W 0h Internal Only to be used through TI provided API 15 4 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 3 0 SRAM_RET_EN R W Fh MCU SRAM is partitioned into 4 banks This register controls which...

Page 461: ... Table 6 33 AUXCFG Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 RAM_RET_EN R W 1h This bit controls retention mode for the AUX_RAM BANK0 0 Retention is disabled 1 Retention is enabled NB If retention is disabled the AUX_RAM will be p...

Page 462: ...t AUX_SCE execution starts as soon as AUX power domain is woken up AUX_SCE CTL CLK_EN will be reset to 0 if AUX power domain has been off 0 AUX_SCE execution will be disabled if AUX_SCE CTL CLK_EN is 0 1 AUX_SCE execution is enabled 1 SWEV R W 0h Writing 1 sets the software event to the AUX domain which can be read through AUX_WUC WUEVFLAGS AON_SW This event is normally cleared by AUX_SCE through ...

Page 463: ...ted 8 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 JTAG_PD_ON R 0h Indicates JTAG power state 0 JTAG is powered off 1 JTAG is powered on 5 AUX_PD_ON R 0h Indicates AUX power state 0 AUX is not ready for use may be powered off or in power state transition 1 AUX is powered on connected to bus and rea...

Page 464: ...riting any other value than the reset value may result in undefined behavior 0 EN R W 0h Writing a 1 to this bit forces a shutdown request to be registered and all I O values to be latched in the PAD ring possibly enabling I O wakeup Writing 0 will cancel a registered shutdown request and open th I O latches residing in the PAD ring A registered shutdown request takes effect the next time power do...

Page 465: ...g any other value than the reset value may result in undefined behavior 8 PWR_DWN_DIS R W 0h Controls whether MCU and AUX requesting to be powered off will enable a transition to powerdown 0 Enabled 1 Disabled 7 4 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 3 AUX_SRAM_ERASE W 0h Internal Only to be ...

Page 466: ...RVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 1 MCU_RESET_SRC R W1C 0h Indicates source of last MCU Voltage Domain warm reset request 0 MCU SW reset 1 JTAG reset This bit can only be cleared by writing a 1 to it 0 MCU_WARM_RESET R W1C 0h Indicates type of last MCU Voltage Domain reset 0 Last MCU reset was...

Page 467: ...m period_new period 1 2 C1 2 C2 Valid values for C1 is 1 to 10 Note Rounding may cause adaptive recharge not to start for very small values of both Gain and Initial period Criteria for algorithm to start is MAX PERIOD 2 C1 PERIOD 2 C2 1 15 11 MAX_PER_M R W 0h This register defines the maximum period that the recharge algorithm can take i e it defines the maximum number of cycles between 2 recharge...

Page 468: ...IOD is the initial period when entering powerdown mode The adaptive recharge algorithm will not change this register PERIOD will effectively be a 16 bit value coded in a 5 bit mantissa and 3 bit exponent This field sets the Exponent of the Period PERIOD PER_M 16 15 2PER_E 468 Power Reset and Clock Management SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015...

Page 469: ...VDDR samples bit 0 being the newest The register is being updated in every recharge period with a shift left and bit 0 is updated with the last VDDR sample ie a 1 is shiftet in in case VDDR VDDR_threshold just before recharge starts Otherwise a 0 will be shifted in 15 0 MAX_USED_PER R W 0h The maximum value of recharge period seen with VDDR threshold The VDDR voltage is compared against the thresh...

Page 470: ...When this counter expires in Powerdown mode an internal flag is set such that the amplitude compensation is postponed until the next recharge occurs The Period will effectively be a 16 bit value coded in a 5 bit mantissa and 3 bit exponent PERIOD PER_M 16 15 2PER_E This field sets the mantissa Note Oscillator amplitude calibration is turned of when both this bitfield and PER_E are set to 0 2 0 PER...

Page 471: ...on the value of a reserved Writing any other value than the reset value may result in undefined behavior 8 JTAG_PD_FORCE_ON R W 1h Controls JTAG PowerDomain power state 0 Controlled exclusively by debug subsystem JTAG Powerdomain will be powered off unless a debugger is attached 1 JTAG Power Domain is forced on independent of debug subsystem NB The reset value causes JTAG Power Domain to be powere...

Page 472: ...AGUSERCODE Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 USER_CODE R W B99A02Fh Table 6 43 JTAGUSERCODE Register Field Descriptions Bit Field Type Reset Description 31 0 USER_CODE R W B99A02Fh 32 bit JTAG USERCODE register feeding main JTAG TAP NB This field can be locked 472 Power Reset and Clock Management SWCU117C February 2015 Revised September ...

Page 473: ...e Section 6 2 4 17 64h I2CCLKGS I2C Clock Gate For Sleep Mode Section 6 2 4 18 68h I2CCLKGDS I2C Clock Gate For Deep Sleep Mode Section 6 2 4 19 6Ch UARTCLKGR UART Clock Gate For Run Mode Section 6 2 4 20 70h UARTCLKGS UART Clock Gate For Sleep Mode Section 6 2 4 21 74h UARTCLKGDS UART Clock Gate For Deep Sleep Mode Section 6 2 4 22 78h SSICLKGR SSI Clock Gate For Run Mode Section 6 2 4 23 7Ch SSI...

Page 474: ...trol Section 6 2 4 48 18Ch PDCTL1VIMS VIMS Power Domain Control Section 6 2 4 49 194h PDSTAT1 Power Domain Status Section 6 2 4 50 198h PDSTAT1BUS BUS Power Domain Status Section 6 2 4 51 19Ch PDSTAT1RFC RFC Power Domain Status Section 6 2 4 52 1A0h PDSTAT1CPU CPU Power Domain Status Section 6 2 4 53 1A4h PDSTAT1VIMS VIMS Power Domain Status Section 6 2 4 54 1D0h RFCMODESEL Selected RFC Mode Secti...

Page 475: ...scriptions Bit Field Type Reset Description 31 2 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 1 0 RATIO R W 0h Division rate for clocks driving modules in the MCU_AON domain when system CPU is in run mode Division ratio affects both infrastructure clock and perbusull clock 0h Divide by 1 1h Divide by 2...

Page 476: ...scriptions Bit Field Type Reset Description 31 2 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 1 0 RATIO R W 0h Division rate for clocks driving modules in the MCU_AON domain when system CPU is in sleep mode Division ratio affects both infrastructure clock and perbusull clock 0h Divide by 1 1h Divide by...

Page 477: ...Descriptions Bit Field Type Reset Description 31 2 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 1 0 RATIO R W 0h Division rate for clocks driving modules in the MCU_AON domain when system CPU is in seepsleep mode Division ratio affects both infrastructure clock and perbusull clock 0h Divide by 1 1h Div...

Page 478: ...effect before the following requirements are met 1 PDCTL1 CPU_ON 0 2 PDCTL1 VIMS_MODE 0 3 SECDMACLKGDS DMA_CLK_EN 0 Note Setting must be loaded with CLKLOADCTL LOAD 4 SECDMACLKGDS CRYPTO_CLK_EN 0 Note Setting must be loaded with CLKLOADCTL LOAD 5 RFC do no request access to BUS 6 System CPU in deepsleep 1 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value tha...

Page 479: ...ESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 1 LOAD_DONE R 1h Status of LOAD Will be cleared to 0 when any of the registers requiring a LOAD is written to and be set to 1 when a LOAD is done Note that writing no change to a register will result in the LOAD_DONE being cleared 0 One or more registers have...

Page 480: ...ting updates Registers that needs to be followed by LOAD before settings being applied are RFCCLKG VIMSCLKG SECDMACLKGR SECDMACLKGS SECDMACLKGDS GPIOCLKGR GPIOCLKGS GPIOCLKGDS GPTCLKGR GPTCLKGS GPTCLKGDS GPTCLKDIV I2CCLKGR I2CCLKGS I2CCLKGDS SSICLKGR SSICLKGS SSICLKGDS UARTCLKGR UARTCLKGS UARTCLKGDS I2SCLKGR I2SCLKGS I2SCLKGDS I2SBCLKSEL I2SCLKCTL I2SMCLKDIV I2SBCLKDIV I2SWCLKDIV 480 Power Reset a...

Page 481: ... W 1h Table 6 50 RFCCLKG Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 CLK_EN R W 1h 0 Disable clock 1 Enable clock if RFC power domain is on For changes to take effect CLKLOADCTL LOAD needs to be written 481 SWCU117C February 2015 Revi...

Page 482: ... Register Field Descriptions Bit Field Type Reset Description 31 2 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 1 0 CLK_EN R W 3h 00 Disable clock 01 Disable clock when SYSBUS clock is disabled 11 Enable clock For changes to take effect CLKLOADCTL LOAD needs to be written 482 Power Reset and Clock Mana...

Page 483: ...he value of a reserved Writing any other value than the reset value may result in undefined behavior 8 DMA_CLK_EN R W 0h 0 Disable clock 1 Enable clock For changes to take effect CLKLOADCTL LOAD needs to be written 7 2 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 1 TRNG_CLK_EN R W 0h 0 Disable clock 1 ...

Page 484: ...the value of a reserved Writing any other value than the reset value may result in undefined behavior 8 DMA_CLK_EN R W 0h 0 Disable clock 1 Enable clock For changes to take effect CLKLOADCTL LOAD needs to be written 7 2 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 1 TRNG_CLK_EN R W 0h 0 Disable clock 1...

Page 485: ...y on the value of a reserved Writing any other value than the reset value may result in undefined behavior 8 DMA_CLK_EN R W 0h 0 Disable clock 1 Enable clock For changes to take effect CLKLOADCTL LOAD needs to be written 7 2 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 1 TRNG_CLK_EN R W 0h 0 Disable cl...

Page 486: ...RESERVED CLK_EN R 0h R W 0h Table 6 55 GPIOCLKGR Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 CLK_EN R W 0h 0 Disable clock 1 Enable clock For changes to take effect CLKLOADCTL LOAD needs to be written 486 Power Reset and Clock Managem...

Page 487: ... RESERVED CLK_EN R 0h R W 0h Table 6 56 GPIOCLKGS Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 CLK_EN R W 0h 0 Disable clock 1 Enable clock For changes to take effect CLKLOADCTL LOAD needs to be written 487 SWCU117C February 2015 Revis...

Page 488: ... 1 0 RESERVED CLK_EN R 0h R W 0h Table 6 57 GPIOCLKGDS Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 CLK_EN R W 0h 0 Disable clock 1 Enable clock For changes to take effect CLKLOADCTL LOAD needs to be written 488 Power Reset and Clock M...

Page 489: ...escription 31 4 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 3 0 CLK_EN R W 0h Each bit below has the following meaning 0 Disable clock 1 Enable clock ENUMs can be combined For changes to take effect CLKLOADCTL LOAD needs to be written 1h Enable clock for GPT0 2h Enable clock for GPT1 4h Enable clock f...

Page 490: ...Description 31 4 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 3 0 CLK_EN R W 0h Each bit below has the following meaning 0 Disable clock 1 Enable clock ENUMs can be combined For changes to take effect CLKLOADCTL LOAD needs to be written 1h Enable clock for GPT0 2h Enable clock for GPT1 4h Enable clock ...

Page 491: ...eset Description 31 4 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 3 0 CLK_EN R W 0h Each bit below has the following meaning 0 Disable clock 1 Enable clock ENUMs can be combined For changes to take effect CLKLOADCTL LOAD needs to be written 1h Enable clock for GPT0 2h Enable clock for GPT1 4h Enable c...

Page 492: ...RESERVED CLK_EN R W 0h R W 0h Table 6 61 I2CCLKGR Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 CLK_EN R W 0h 0 Disable clock 1 Enable clock For changes to take effect CLKLOADCTL LOAD needs to be written 492 Power Reset and Clock Mana...

Page 493: ... RESERVED CLK_EN R W 0h R W 0h Table 6 62 I2CCLKGS Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 CLK_EN R W 0h 0 Disable clock 1 Enable clock For changes to take effect CLKLOADCTL LOAD needs to be written 493 SWCU117C February 2015 Re...

Page 494: ...1 0 RESERVED CLK_EN R W 0h R W 0h Table 6 63 I2CCLKGDS Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 CLK_EN R W 0h 0 Disable clock 1 Enable clock For changes to take effect CLKLOADCTL LOAD needs to be written 494 Power Reset and Clock...

Page 495: ... RESERVED CLK_EN R W 0h R W 0h Table 6 64 UARTCLKGR Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 CLK_EN R W 0h 0 Disable clock 1 Enable clock For changes to take effect CLKLOADCTL LOAD needs to be written 495 SWCU117C February 2015 R...

Page 496: ...0 RESERVED CLK_EN R W 0h R W 0h Table 6 65 UARTCLKGS Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 CLK_EN R W 0h 0 Disable clock 1 Enable clock For changes to take effect CLKLOADCTL LOAD needs to be written 496 Power Reset and Clock M...

Page 497: ...2 1 0 RESERVED CLK_EN R W 0h R W 0h Table 6 66 UARTCLKGDS Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 CLK_EN R W 0h 0 Disable clock 1 Enable clock For changes to take effect CLKLOADCTL LOAD needs to be written 497 SWCU117C February ...

Page 498: ...ICLKGR Register Field Descriptions Bit Field Type Reset Description 31 2 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 1 0 CLK_EN R W 0h 0 Disable clock 1 Enable clock For changes to take effect CLKLOADCTL LOAD needs to be written 1h Enable clock for SSI0 2h Enable clock for SSI1 498 Power Reset and Clo...

Page 499: ...SICLKGS Register Field Descriptions Bit Field Type Reset Description 31 2 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 1 0 CLK_EN R W 0h 0 Disable clock 1 Enable clock For changes to take effect CLKLOADCTL LOAD needs to be written 1h Enable clock for SSI0 2h Enable clock for SSI1 499 SWCU117C February ...

Page 500: ...9 SSICLKGDS Register Field Descriptions Bit Field Type Reset Description 31 2 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 1 0 CLK_EN R W 0h 0 Disable clock 1 Enable clock For changes to take effect CLKLOADCTL LOAD needs to be written 1h Enable clock for SSI0 2h Enable clock for SSI1 500 Power Reset an...

Page 501: ...ESERVED CLK_EN R 0h R W 0h Table 6 70 I2SCLKGR Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 CLK_EN R W 0h 0 Disable clock 1 Enable clock For changes to take effect CLKLOADCTL LOAD needs to be written 501 SWCU117C February 2015 Revised ...

Page 502: ...RESERVED CLK_EN R 0h R W 0h Table 6 71 I2SCLKGS Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 CLK_EN R W 0h 0 Disable clock 1 Enable clock For changes to take effect CLKLOADCTL LOAD needs to be written 502 Power Reset and Clock Manageme...

Page 503: ... 0 RESERVED CLK_EN R 0h R W 0h Table 6 72 I2SCLKGDS Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 CLK_EN R W 0h 0 Disable clock 1 Enable clock For changes to take effect CLKLOADCTL LOAD needs to be written 503 SWCU117C February 2015 Rev...

Page 504: ... 17 16 RESERVED R 0h 15 14 13 12 11 10 9 8 RESERVED R 0h 7 6 5 4 3 2 1 0 RESERVED RATIO R 0h R W 0h Table 6 73 CPUCLKDIV Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R 0h Internal Only to be used through TI provided API 0 RATIO R W 0h Internal Only to be used through TI provided API 504 Power Reset and Clock Management SWCU117C February 2015 Revised September 2015 Sub...

Page 505: ...2SBCLKSEL Register Field Descriptions Bit Field Type Reset Description 31 1 SPARE R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 SRC R W 0h BCLK source selector 0 Use external BCLK 1 Use internally generated clock For changes to take effect CLKLOADCTL LOAD needs to be written 505 SWCU117C February 2015 Revise...

Page 506: ...not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 3 0 RATIO R W 0h Scalar used for GPTs The division rate will be constant and ungated for Run Sleep DeepSleep mode For changes to take effect CLKLOADCTL LOAD needs to be written Other values are not supported 0h Divide by 1 1h Divide by 2 2h Divide by 4 3h Divide by 8 4h Divide by 16 5h...

Page 507: ...LK is sampled and clocked out on opposite edges of BCLK 0 data and WCLK are sampled on the negative edge and clocked out on the positive edge 1 data and WCLK are sampled on the positive edge and clocked out on the negative edge For changes to take effect CLKLOADCTL LOAD needs to be written 2 1 WCLK_PHASE R W 0h Decides how the WCLK division ratio is calculated and used to generate different duty c...

Page 508: ...iting any other value than the reset value may result in undefined behavior 9 0 MDIV R W 0h An unsigned factor of the division ratio used to generate MCLK 2 1024 MCLK MCUCLK MDIV Hz MCUCLK is 48MHz in normal mode For powerdown mode the frequency is defined by AON_WUC MCUCLK PWR_DWN_SRC A value of 0 is interpreted as 1024 A value of 1 is invalid If MDIV is odd the low phase of the clock is one MCUC...

Page 509: ... BDIV R W 0h An unsigned factor of the division ratio used to generate I2S BCLK 2 1024 BCLK MCUCLK BDIV Hz MCUCLK is 48MHz in normal mode For powerdown mode the frequency is defined by AON_WUC MCUCLK PWR_DWN_SRC A value of 0 is interpreted as 1024 A value of 1 is invalid If BDIV is odd and I2SCLKCTL SMPL_ON_POSEDGE 0 the low phase of the clock is one MCUCLK period longer than the high phase If BDI...

Page 510: ...PHASE 0 Single phase WCLK is high one BCLK period and low WDIV 9 0 unsigned 1 1023 BCLK periods WCLK MCUCLK BDIV WDIV 9 0 1 Hz MCUCLK is 48MHz in normal mode For powerdown mode the frequency is defined by AON_WUC MCUCLK PWR_DWN_SRC If I2SCLKCTL WCLK_PHASE 1 Dual phase Each phase on WCLK 50 duty cycle is WDIV 9 0 unsigned 1 1023 BCLK periods WCLK MCUCLK BDIV 2 WDIV 9 0 Hz If I2SCLKCTL WCLK_PHASE 2 ...

Page 511: ...gister Field Descriptions Bit Field Type Reset Description 31 3 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 2 MCU W 0h Internal Only to be used through TI provided API 1 0 RESERVED W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefin...

Page 512: ... pin reset Warm reset sources included ICEPick sysreset System CPU reset request CPU_SCS AIRCR SYSRESETREQ System CPU Lockup WDT timeout An active ICEPick block system reset will gate all sources except ICEPick sysreset SW can read AON_SYSCTL RESETCTL RESET_SRC to find the source of the last reset resulting in a full power up sequence WARMRESET in this register is set in the scenario that WR_TO_PI...

Page 513: ...cription 31 3 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 2 PERIPH_ON R W 0h PERIPH Power domain 0 PERIPH power domain is powered down 1 PERIPH power domain is powered up 1 SERIAL_ON R W 0h SERIAL Power domain 0 SERIAL power domain is powered down 1 SERIAL power domain is powered up 0 RFC_ON R W 0h 0 ...

Page 514: ... 10 9 8 7 6 5 4 3 2 1 0 RESERVED ON R 0h R W 0h Table 6 83 PDCTL0RFC Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 ON R W 0h Alias for PDCTL0 RFC_ON 514 Power Reset and Clock Management SWCU117C February 2015 Revised September 2015 Subm...

Page 515: ... 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED ON R 0h R W 0h Table 6 84 PDCTL0SERIAL Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 ON R W 0h Alias for PDCTL0 SERIAL_ON 515 SWCU117C February 2015 Revised September 2015 Power Reset and Clock Manage...

Page 516: ... 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED ON R 0h R W 0h Table 6 85 PDCTL0PERIPH Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 ON R W 0h Alias for PDCTL0 PERIPH_ON 516 Power Reset and Clock Management SWCU117C February 2015 Revised September ...

Page 517: ...Field Type Reset Description 31 3 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 2 PERIPH_ON R 0h PERIPH Power domain 0 Domain may be powered down 1 Domain powered up guaranteed 1 SERIAL_ON R 0h SERIAL Power domain 0 Domain may be powered down 1 Domain powered up guaranteed 0 RFC_ON R 0h RFC Power domain...

Page 518: ...11 10 9 8 7 6 5 4 3 2 1 0 RESERVED ON R 0h R 0h Table 6 87 PDSTAT0RFC Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 ON R 0h Alias for PDSTAT0 RFC_ON 518 Power Reset and Clock Management SWCU117C February 2015 Revised September 2015 Subm...

Page 519: ...12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED ON R 0h R 0h Table 6 88 PDSTAT0SERIAL Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 ON R 0h Alias for PDSTAT0 SERIAL_ON 519 SWCU117C February 2015 Revised September 2015 Power Reset and Clock Manage...

Page 520: ...12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED ON R 0h R 0h Table 6 89 PDSTAT0PERIPH Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 ON R 0h Alias for PDSTAT0 PERIPH_ON 520 Power Reset and Clock Management SWCU117C February 2015 Revised September ...

Page 521: ...n the reset value may result in undefined behavior 3 VIMS_MODE R W 1h 0 VIMS power domain is only powered when CPU power domain is powered 1 VIMS power domain is powered whenever the BUS power domain is powered 2 RFC_ON R W 0h 0 RFC power domain powered off if also PDCTL0 RFC_ON 0 1 RFC power domain powered on Bit shall be used by RFC in autonomus mode but there is no HW restrictions fom system CP...

Page 522: ...8 7 6 5 4 3 2 1 0 RESERVED ON R 0h R W 1h Table 6 91 PDCTL1CPU Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 ON R W 1h This is an alias for PDCTL1 CPU_ON 522 Power Reset and Clock Management SWCU117C February 2015 Revised September 2015...

Page 523: ...8 7 6 5 4 3 2 1 0 RESERVED ON R 0h R W 0h Table 6 92 PDCTL1RFC Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 ON R W 0h This is an alias for PDCTL1 RFC_ON 523 SWCU117C February 2015 Revised September 2015 Power Reset and Clock Management...

Page 524: ...8 7 6 5 4 3 2 1 0 RESERVED ON R 0h R W 1h Table 6 93 PDCTL1VIMS Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 ON R W 1h This is an alias for PDCTL1 VIMS_MODE 524 Power Reset and Clock Management SWCU117C February 2015 Revised September ...

Page 525: ...eserved Writing any other value than the reset value may result in undefined behavior 4 BUS_ON R 1h 0 BUS domain not accessible 1 BUS domain is currently accessible 3 VIMS_MODE R 1h 0 VIMS domain not accessible 1 VIMS domain is currently accessible 2 RFC_ON R 0h 0 RFC domain not accessible 1 RFC domain is currently accessible 1 CPU_ON R 1h 0 CPU and BUS domain not accessible 1 CPU and BUS domains ...

Page 526: ...9 8 7 6 5 4 3 2 1 0 RESERVED ON R 0h R 1h Table 6 95 PDSTAT1BUS Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 ON R 1h This is an alias for PDSTAT1 BUS_ON 526 Power Reset and Clock Management SWCU117C February 2015 Revised September 2015...

Page 527: ...9 8 7 6 5 4 3 2 1 0 RESERVED ON R 0h R 0h Table 6 96 PDSTAT1RFC Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 ON R 0h This is an alias for PDSTAT1 RFC_ON 527 SWCU117C February 2015 Revised September 2015 Power Reset and Clock Management...

Page 528: ...9 8 7 6 5 4 3 2 1 0 RESERVED ON R 0h R 1h Table 6 97 PDSTAT1CPU Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 ON R 1h This is an alias for PDSTAT1 CPU_ON 528 Power Reset and Clock Management SWCU117C February 2015 Revised September 2015...

Page 529: ...9 8 7 6 5 4 3 2 1 0 RESERVED ON R 0h R 1h Table 6 98 PDSTAT1VIMS Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 ON R 1h This is an alias for PDSTAT1 VIMS_MODE 529 SWCU117C February 2015 Revised September 2015 Power Reset and Clock Manage...

Page 530: ...ield Type Reset Description 31 3 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 2 0 CURR R W 0h Written by MCU Outputs to RFC Only modes permitted by RFCMODEHWOPT AVAIL are writeable 0h Select Mode 0 1h Select Mode 1 2h Select Mode 2 3h Select Mode 3 4h Select Mode 4 5h Select Mode 5 6h Select Mode 6 7h ...

Page 531: ...sult in undefined behavior 2 RFC R W 0h 0 Retention for RFC SRAM disabled 1 Retention for RFC SRAM enabled 1 0 VIMS R W 3h 0 Memory retention disabled 1 Memory retention enabled Bit 0 VIMS_TRAM Bit 1 VIMS_CRAM Legal modes depend on settings in VIMS CTL MODE 00 VIMS CTL MODE must be OFF before DEEPSLEEP is asserted must be set to CACHE or SPLIT mode after waking up again 01 VIMS CTL MODE must be GP...

Page 532: ...ule Figure 7 1 VIMS Overview The VIMS module forwards CPU accesses icode dcode and system bus accesses to the addressed memories the VIMS module also arbitrates access between the CPU and the system bus The VIMS module runs on the 48 MHz system clock The flash memory is programmable from user software from the debug interface and from the ROM bootloader The RAM block can be used as a cache for the...

Page 533: ... ROM 540 7 4 FLASH 540 7 5 Power Management Requirements 541 7 6 ROM Functions 543 7 7 SRAM 544 7 8 VIMS Registers 545 533 SWCU117C February 2015 Revised September 2015 Versatile Instruction Memory System VIMS Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 534: ... MODE register Lines in brown are hardware initiated changes The invalidating state is a transition state controlled by hardware Invalidation clears the entire content of the RAM block and takes 1029 clock periods to perform Figure 7 2 VIMS Mode Switching Flowchart Once a mode change is initiated shown in the VIMS STATUS MODE_CHANGING register the mode change must complete before another mode chan...

Page 535: ...lash block has no cache support and all accesses to the flash are routed directly to the Flash block Figure 7 3 VIMS Module in GPRAM Mode 7 1 1 2 Off Mode In off mode the RAM block is disabled and cannot be accessed by the CPU or by the system bus The Flash block has no cache support and all accesses to the flash are routed directly to the Flash block Figure 7 4 VIMS Module in Off Mode 535 SWCU117...

Page 536: ... the input address in the internal tag RAM to determine whether the access is a cache hit or a cache miss In the case of a cache miss the access is forwarded to the Flash block The response from the Flash block is routed back to the cache then the cache is updated In the case of a cache hit the data is fetched directly from the cache RAM The cache also contains a line buffer because the cache RAM ...

Page 537: ...register 7 1 3 VIMS Arbitration The VIMS provides arbitration between the CPU bus and the system bus The arbitration is configurable between round robin and static through the VIMS CTL ARB_CFG register The static arbitration is enabled by default and gives the CPU priority over system bus accesses The system arbiter allows accesses to occur simultaneously provided that the CPU bus and the system b...

Page 538: ... internal TAG RAM or cache RAM are kept in retention together with VIMS logic NOTE If the whole MCU domain is powered off the VIMS domain does not support retention Table 7 1 specifies the valid retention combination for VIMS memory Table 7 1 Valid Retention Combination for VIMS Memory Retention Enabled Mode Comment TAG RAM CACHE RAM VIMS Logic Software must compensate for loss of data 1 No No Yes...

Page 539: ...to 0 In addition a write buffer provides the ability to program 32 continuous words in flash memory in half the time of programming the words individually Erasing a block causes the entire contents of the block to be reset to all 1s The 4 KB blocks are paired with sets of 8 KB blocks that can be individually protected The protection allows blocks to be marked as read only or execute only thus prov...

Page 540: ...n the Flash memory must not be read If instruction execution is required during a flash memory operation the executing code must be placed in SRAM and executed from SRAM while the flash operation is in progress 7 5 Power Management Requirements The module implements the following power reducing functionalities Voltage Off The module logic VDD is turned off Pump and bank is kept in deep sleep This ...

Page 541: ...nagement Voltage Off is like initial power on Power Off requires a restore of retention and internal sequencers must power up and configure the bank and charge pump Leaving Deep Standby can start from the following PRCM By writing a register in the MMR By starting a read access to the flash Switching between Idle Reading and Reading is done automatically when a read has ended The switching can be ...

Page 542: ...ge in flash Bootloader disable JTAG DAP TAP disable TI FA analysis disable Customer configuration area write or erase protection Other configuration not related to security Configuration memory RO OTP 1 KB read interface write through FMC RO ENGR 1 KB read interface write through FMC CCFG FLASH sector 4 KB read interface write through FMC RO EFUSE only accessible through MMR interface The ROM is p...

Page 543: ...e Cortex M3 processor With a bit band enabled processor certain regions in the memory map SRAM and peripheral space can use address aliases to access individual bits in one atomic operation Data can also be transferred to and from the SRAM using the micro direct memory access controller μDMA The Cortex M0 in the RF Core also has access to the system RAM 543 SWCU117C February 2015 Revised September...

Page 544: ...7 102Ch EFUSEPINS Efuse Pins Section 7 8 1 18 1030h EFUSECRA Efuse Column Repair Address Section 7 8 1 19 1034h EFUSEREAD Efuse Read Section 7 8 1 20 1038h EFUSEPROGRAM Efuse Program Section 7 8 1 21 103Ch EFUSEERROR Efuse Error Section 7 8 1 22 1040h SINGLEBIT Single Bit Error Status Section 7 8 1 23 1044h TWOBIT Two Bit Error Status Section 7 8 1 24 1048h SELFTESTCYC Self Test Cycles Section 7 8...

Page 545: ... 7 8 1 65 213Ch FWPWRITE7 FMC Flash Wide Programming Write Data 7 Section 7 8 1 66 2140h FWPWRITE_ECC FMC Flash Wide Programming ECC Section 7 8 1 67 2144h FSWSTAT FMC Software Interface Status Section 7 8 1 68 2200h FSM_GLBCTL FMC FSM Global Control Section 7 8 1 69 2204h FSM_STATE FMC FSM State Status Section 7 8 1 70 2208h FSM_STAT FMC FSM Status Section 7 8 1 71 220Ch FSM_CMD FMC FSM Command S...

Page 546: ...106 22C4h FSM_SECTOR2 FMC FSM Sector Erased 2 Section 7 8 1 107 22E0h FSM_BSLE0 FMC FSM Bank Sector Lock Erase 0 Section 7 8 1 108 22E4h FSM_BSLE1 FMC FSM Bank Sector Lock Erase 1 Section 7 8 1 109 22F0h FSM_BSLP0 FMC FSM Bank Sector Lock Program 0 Section 7 8 1 110 22F4h FSM_BSLP1 FMC FSM Bank Sector Lock Program 1 Section 7 8 1 111 2400h FCFG_BANK FMC Flash Configuration Bank Section 7 8 1 112 2...

Page 547: ...anning resulted in timeout error 0 No Timeout error 1 Timeout Error 13 EFUSE_CRC_ERROR R 0h Efuse scanning resulted in scan chain CRC error 0 No CRC error 1 CRC Error 12 8 EFUSE_ERRCODE R 0h Same as EFUSEERROR CODE 7 3 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 2 SAMHOLD_DIS R 0h Status indicator of ...

Page 548: ...provided API 8 STANDBY_MODE_SEL R W 0h Internal Only to be used through TI provided API 7 6 STANDBY_PW_SEL R W 0h Internal Only to be used through TI provided API 5 DIS_EFUSECLK R W 0h Internal Only to be used through TI provided API 4 DIS_READACCESS R W 0h Internal Only to be used through TI provided API 3 ENABLE_SWINTF R W 0h Internal Only to be used through TI provided API 2 RESERVED R W 0h Sof...

Page 549: ...SERVED R 0h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED SYSCODE_START R 0h R W 0h Table 7 6 SYSCODE_START Register Field Descriptions Bit Field Type Reset Description 31 5 RESERVED R 0h Internal Only to be used through TI provided API 4 0 SYSCODE_START R W 0h Internal Only to be used through TI provided API 549 SWCU117C February 2015 Revised September 2015 Versatile Instruction Memory System VI...

Page 550: ...8 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED SECTORS R 0h R W 0h Table 7 7 FLASH_SIZE Register Field Descriptions Bit Field Type Reset Description 31 8 RESERVED R 0h Internal Only to be used through TI provided API 7 0 SECTORS R W 0h Internal Only to be used through TI provided API 550 Versatile Instruction Memory System VIMS SWCU117C February 2015 Revised September 2015 Submit Documenta...

Page 551: ...SERVED R 0h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED FWLOCK R 0h R W 0h Table 7 8 FWLOCK Register Field Descriptions Bit Field Type Reset Description 31 3 RESERVED R 0h Internal Only to be used through TI provided API 2 0 FWLOCK R W 0h Internal Only to be used through TI provided API 551 SWCU117C February 2015 Revised September 2015 Versatile Instruction Memory System VIMS Submit Documentati...

Page 552: ...SERVED R 0h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED FWFLAG R 0h R W 0h Table 7 9 FWFLAG Register Field Descriptions Bit Field Type Reset Description 31 3 RESERVED R 0h Internal Only to be used through TI provided API 2 0 FWFLAG R W 0h Internal Only to be used through TI provided API 552 Versatile Instruction Memory System VIMS SWCU117C February 2015 Revised September 2015 Submit Documentati...

Page 553: ...UMPWORD R W 0h Table 7 10 EFUSE Register Field Descriptions Bit Field Type Reset Description 31 29 RESERVED R 0h Internal Only to be used through TI provided API 28 24 INSTRUCTION R W 0h Internal Only to be used through TI provided API 23 16 RESERVED R 0h Internal Only to be used through TI provided API 15 0 DUMPWORD R W 0h Internal Only to be used through TI provided API 553 SWCU117C February 201...

Page 554: ...3 2 1 0 RESERVED BLOCK ROW R 0h R W 0h R W 0h Table 7 11 EFUSEADDR Register Field Descriptions Bit Field Type Reset Description 31 16 RESERVED R 0h Internal Only to be used through TI provided API 15 11 BLOCK R W 0h Internal Only to be used through TI provided API 10 0 ROW R W 0h Internal Only to be used through TI provided API 554 Versatile Instruction Memory System VIMS SWCU117C February 2015 Re...

Page 555: ...h 0h Table 7 12 DATAUPPER Register Field Descriptions Bit Field Type Reset Description 31 8 RESERVED R 0h Internal Only to be used through TI provided API 7 3 SPARE R W 0h Internal Only to be used through TI provided API 2 P R W 0h Internal Only to be used through TI provided API 1 R R W 0h Internal Only to be used through TI provided API 0 EEN R W 0h Internal Only to be used through TI provided A...

Page 556: ...ter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA R W 0h Table 7 13 DATALOWER Register Field Descriptions Bit Field Type Reset Description 31 0 DATA R W 0h Internal Only to be used through TI provided API 556 Versatile Instruction Memory System VIMS SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Texas Instrume...

Page 557: ...CFG Register Field Descriptions Bit Field Type Reset Description 31 9 RESERVED R 0h Internal Only to be used through TI provided API 8 IDLEGATING R W 0h Internal Only to be used through TI provided API 7 5 RESERVED R 0h Internal Only to be used through TI provided API 4 3 SLAVEPOWER R W 0h Internal Only to be used through TI provided API 2 1 RESERVED R 0h Internal Only to be used through TI provid...

Page 558: ...6 RESERVED R 0h 15 14 13 12 11 10 9 8 RESERVED R 0h 7 6 5 4 3 2 1 0 RESERVED RESETDONE R 0h R 1h Table 7 15 EFUSESTAT Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R 0h Internal Only to be used through TI provided API 0 RESETDONE R 1h Internal Only to be used through TI provided API 558 Versatile Instruction Memory System VIMS SWCU117C February 2015 Revised September 2...

Page 559: ...5 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED ACCUMULATOR R 0h R 0h Table 7 16 ACC Register Field Descriptions Bit Field Type Reset Description 31 24 RESERVED R 0h Internal Only to be used through TI provided API 23 0 ACCUMULATOR R 0h Internal Only to be used through TI provided API 559 SWCU117C February 2015 Revised September 2015 Versatile Instruction Memory System VIMS Submit Documentation Feed...

Page 560: ... through TI provided API 21 EFC_SELF_TEST_ERRO R W 0h Internal Only to be used through TI provided API R 20 EFC_INSTRUCTION_INF R W 0h Internal Only to be used through TI provided API O 19 EFC_INSTRUCTION_ER R W 0h Internal Only to be used through TI provided API ROR 18 EFC_AUTOLOAD_ERRO R W 0h Internal Only to be used through TI provided API R 17 14 OUTPUTENABLE R W 0h Internal Only to be used th...

Page 561: ...8 17 16 RESERVED R 0h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED KEY R 0h R 0h Table 7 18 EFUSEFLAG Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R 0h Internal Only to be used through TI provided API 0 KEY R 0h Internal Only to be used through TI provided API 561 SWCU117C February 2015 Revised September 2015 Versatile Instruction Memory System VIMS Submit Documenta...

Page 562: ...er 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CODE R W 0h Table 7 19 EFUSEKEY Register Field Descriptions Bit Field Type Reset Description 31 0 CODE R W 0h Internal Only to be used through TI provided API 562 Versatile Instruction Memory System VIMS SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Texas Instrument...

Page 563: ...r Field Descriptions Bit Field Type Reset Description 31 25 ODPYEAR R X Internal Only to be used through TI provided API 24 21 ODPMONTH R X Internal Only to be used through TI provided API 20 16 ODPDAY R X Internal Only to be used through TI provided API 15 9 EFUSEYEAR R X Internal Only to be used through TI provided API 8 5 EFUSEMONTH R X Internal Only to be used through TI provided API 4 0 EFUSE...

Page 564: ...hrough TI provided API 14 EFC_SELF_TEST_ERRO R X Internal Only to be used through TI provided API R 13 SYS_ECC_SELF_TEST_ R X Internal Only to be used through TI provided API EN 12 EFC_INSTRUCTION_INF R X Internal Only to be used through TI provided API O 11 EFC_INSTRUCTION_ER R X Internal Only to be used through TI provided API ROR 10 EFC_AUTOLOAD_ERRO R X Internal Only to be used through TI prov...

Page 565: ... 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED DATA R 0h R W 0h Table 7 22 EFUSECRA Register Field Descriptions Bit Field Type Reset Description 31 6 RESERVED R 0h Internal Only to be used through TI provided API 5 0 DATA R W 0h Internal Only to be used through TI provided API 565 SWCU117C February 2015 Revised September 2015 Versatile Instruction Memory System VIMS Submit Documentation ...

Page 566: ...EREAD Register Field Descriptions Bit Field Type Reset Description 31 10 RESERVED R 0h Internal Only to be used through TI provided API 9 8 DATABIT R W 0h Internal Only to be used through TI provided API 7 4 READCLOCK R W 0h Internal Only to be used through TI provided API 3 DEBUG R W 0h Internal Only to be used through TI provided API 2 SPARE R W 0h Internal Only to be used through TI provided AP...

Page 567: ...Table 7 24 EFUSEPROGRAM Register Field Descriptions Bit Field Type Reset Description 31 RESERVED R 0h Internal Only to be used through TI provided API 30 COMPAREDISABLE R W 0h Internal Only to be used through TI provided API 29 14 CLOCKSTALL R W 0h Internal Only to be used through TI provided API 13 VPPTOVDD R W 0h Internal Only to be used through TI provided API 12 9 ITERATIONS R W 0h Internal On...

Page 568: ...9 8 RESERVED R 0h 7 6 5 4 3 2 1 0 RESERVED DONE CODE R 0h R W 0h R W 0h Table 7 25 EFUSEERROR Register Field Descriptions Bit Field Type Reset Description 31 6 RESERVED R 0h Internal Only to be used through TI provided API 5 DONE R W 0h Internal Only to be used through TI provided API 4 0 CODE R W 0h Internal Only to be used through TI provided API 568 Versatile Instruction Memory System VIMS SWCU...

Page 569: ...9 18 17 16 FROMN R 0h 15 14 13 12 11 10 9 8 FROMN R 0h 7 6 5 4 3 2 1 0 FROMN FROM0 R 0h R 0h Table 7 26 SINGLEBIT Register Field Descriptions Bit Field Type Reset Description 31 1 FROMN R 0h Internal Only to be used through TI provided API 0 FROM0 R 0h Internal Only to be used through TI provided API 569 SWCU117C February 2015 Revised September 2015 Versatile Instruction Memory System VIMS Submit ...

Page 570: ...8 17 16 FROMN R 0h 15 14 13 12 11 10 9 8 FROMN R 0h 7 6 5 4 3 2 1 0 FROMN FROM0 R 0h R 0h Table 7 27 TWOBIT Register Field Descriptions Bit Field Type Reset Description 31 1 FROMN R 0h Internal Only to be used through TI provided API 0 FROM0 R 0h Internal Only to be used through TI provided API 570 Versatile Instruction Memory System VIMS SWCU117C February 2015 Revised September 2015 Submit Docume...

Page 571: ...ter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CYCLES R W 0h Table 7 28 SELFTESTCYC Register Field Descriptions Bit Field Type Reset Description 31 0 CYCLES R W 0h Internal Only to be used through TI provided API 571 SWCU117C February 2015 Revised September 2015 Versatile Instruction Memory System VIMS Submit Documentation Feedback Copyright 2015 Texas In...

Page 572: ...r 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SIGNATURE R W 0h Table 7 29 SELFTESTSIGN Register Field Descriptions Bit Field Type Reset Description 31 0 SIGNATURE R W 0h Internal Only to be used through TI provided API 572 Versatile Instruction Memory System VIMS SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Tex...

Page 573: ...8 7 6 5 4 3 2 1 0 RESERVED RWAIT RM R 0h R W 2h R 0h Table 7 30 FRDCTL Register Field Descriptions Bit Field Type Reset Description 31 12 RESERVED R 0h Internal Only to be used through TI provided API 11 8 RWAIT R W 2h Internal Only to be used through TI provided API 7 0 RM R 0h Internal Only to be used through TI provided API 573 SWCU117C February 2015 Revised September 2015 Versatile Instruction...

Page 574: ... 31 FSPRD Register Field Descriptions Bit Field Type Reset Description 31 16 DIS_PREEMPT R 0h Internal Only to be used through TI provided API 15 8 RMBSEM R W 0h Internal Only to be used through TI provided API 7 2 RESERVED R 0h Internal Only to be used through TI provided API 1 RM1 R W 0h Internal Only to be used through TI provided API 0 RM0 R W 0h Internal Only to be used through TI provided AP...

Page 575: ... 14 13 12 11 10 9 8 EDACEN R 0h 7 6 5 4 3 2 1 0 EDACEN R 0h Table 7 32 FEDACCTL1 Register Field Descriptions Bit Field Type Reset Description 31 25 RESERVED R 0h Internal Only to be used through TI provided API 24 SUSP_IGNR R W 0h Internal Only to be used through TI provided API 23 0 EDACEN R 0h Internal Only to be used through TI provided API 575 SWCU117C February 2015 Revised September 2015 Vers...

Page 576: ... R 0h 7 6 5 4 3 2 1 0 ERR_PRF_FLG R 0h Table 7 33 FEDACSTAT Register Field Descriptions Bit Field Type Reset Description 31 26 RESERVED R 0h Internal Only to be used through TI provided API 25 RVF_INT R W1C 0h Internal Only to be used through TI provided API 24 FSM_DONE R W1C 0h Internal Only to be used through TI provided API 23 0 ERR_PRF_FLG R 0h Internal Only to be used through TI provided API ...

Page 577: ...ERVED R 0h 15 14 13 12 11 10 9 8 RESERVED R 0h 7 6 5 4 3 2 1 0 RESERVED PROTL1DIS R 0h R W 0h Table 7 34 FBPROT Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R 0h Internal Only to be used through TI provided API 0 PROTL1DIS R W 0h Internal Only to be used through TI provided API 577 SWCU117C February 2015 Revised September 2015 Versatile Instruction Memory System VIMS ...

Page 578: ...17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED BSE R 0h R W 0h Table 7 35 FBSE Register Field Descriptions Bit Field Type Reset Description 31 16 RESERVED R 0h Internal Only to be used through TI provided API 15 0 BSE R W 0h Internal Only to be used through TI provided API 578 Versatile Instruction Memory System VIMS SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback...

Page 579: ... 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED BUSY R 0h R FEh Table 7 36 FBBUSY Register Field Descriptions Bit Field Type Reset Description 31 8 RESERVED R 0h Internal Only to be used through TI provided API 7 0 BUSY R FEh Internal Only to be used through TI provided API 579 SWCU117C February 2015 Revised September 2015 Versatile Instruction Memory System VIMS Submit Documentation Feed...

Page 580: ...4 3 2 1 0 VREADS R W Fh Table 7 37 FBAC Register Field Descriptions Bit Field Type Reset Description 31 17 RESERVED R 0h Internal Only to be used through TI provided API 16 OTPPROTDIS R W 0h Internal Only to be used through TI provided API 15 8 BAGP R W 0h Internal Only to be used through TI provided API 7 0 VREADS R W Fh Internal Only to be used through TI provided API 580 Versatile Instruction M...

Page 581: ... be used through TI provided API 23 20 RESERVED R 0h Internal Only to be used through TI provided API 19 16 REG_PWRSAV R W 5h Internal Only to be used through TI provided API 15 14 BANKPWR7 R W 3h Internal Only to be used through TI provided API 13 12 BANKPWR6 R W 3h Internal Only to be used through TI provided API 11 10 BANKPWR5 R W 3h Internal Only to be used through TI provided API 9 8 BANKPWR4...

Page 582: ...R 7Fh R 0h Table 7 39 FBPRDY Register Field Descriptions Bit Field Type Reset Description 31 17 RESERVED R 7Fh Internal Only to be used through TI provided API 16 BANKBUSY R 1h Internal Only to be used through TI provided API 15 PUMPRDY R 0h Internal Only to be used through TI provided API 14 1 RESERVED R 7Fh Internal Only to be used through TI provided API 0 BANKRDY R 0h Internal Only to be used ...

Page 583: ...h R 0h R W 1h Table 7 40 FPAC1 Register Field Descriptions Bit Field Type Reset Description 31 28 RESERVED R 0h Internal Only to be used through TI provided API 27 16 PSLEEPTDIS R W 208h Internal Only to be used through TI provided API 15 4 PUMPRESET_PW R W 208h Internal Only to be used through TI provided API 3 2 RESERVED R 0h Internal Only to be used through TI provided API 1 0 PUMPPWR R W 1h In...

Page 584: ...17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED PAGP R 0h R W 0h Table 7 41 FPAC2 Register Field Descriptions Bit Field Type Reset Description 31 16 RESERVED R 0h Internal Only to be used through TI provided API 15 0 PAGP R W 0h Internal Only to be used through TI provided API 584 Versatile Instruction Memory System VIMS SWCU117C February 2015 Revised September 2015 Submit Documentation Feedb...

Page 585: ...ESERVED R 0h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED BANK R 0h R W 0h Table 7 42 FMAC Register Field Descriptions Bit Field Type Reset Description 31 3 RESERVED R 0h Internal Only to be used through TI provided API 2 0 BANK R W 0h Internal Only to be used through TI provided API 585 SWCU117C February 2015 Revised September 2015 Versatile Instruction Memory System VIMS Submit Documentation F...

Page 586: ...nly to be used through TI provided API 13 DBF R 0h Internal Only to be used through TI provided API 12 PGV R 0h Internal Only to be used through TI provided API 11 PCV R 0h Internal Only to be used through TI provided API 10 EV R 0h Internal Only to be used through TI provided API 9 CV R 0h Internal Only to be used through TI provided API 8 BUSY R 0h Internal Only to be used through TI provided AP...

Page 587: ... 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED ENCOM R 0h R W 55AAh Table 7 44 FLOCK Register Field Descriptions Bit Field Type Reset Description 31 16 RESERVED R 0h Internal Only to be used through TI provided API 15 0 ENCOM R W 55AAh Internal Only to be used through TI provided API 587 SWCU117C February 2015 Revised September 2015 Versatile Instruction Memory System VIMS Submit Documentation...

Page 588: ...RESERVED R 0h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED VREADCT R 0h R W 8h Table 7 45 FVREADCT Register Field Descriptions Bit Field Type Reset Description 31 4 RESERVED R 0h Internal Only to be used through TI provided API 3 0 VREADCT R W 8h Internal Only to be used through TI provided API 588 Versatile Instruction Memory System VIMS SWCU117C February 2015 Revised September 2015 Submit Docu...

Page 589: ... Descriptions Bit Field Type Reset Description 31 24 RESERVED R 0h Internal Only to be used through TI provided API 23 20 TRIM13_E R W 8h Internal Only to be used through TI provided API 19 16 VHVCT_E R W 4h Internal Only to be used through TI provided API 15 8 RESERVED R 0h Internal Only to be used through TI provided API 7 4 TRIM13_PV R W 8h Internal Only to be used through TI provided API 3 0 V...

Page 590: ...2 1 0 RESERVED R 0h Table 7 47 FVHVCT2 Register Field Descriptions Bit Field Type Reset Description 31 24 RESERVED R 0h Internal Only to be used through TI provided API 23 20 TRIM13_P R W Ah Internal Only to be used through TI provided API 19 16 VHVCT_P R W 2h Internal Only to be used through TI provided API 15 0 RESERVED R 0h Internal Only to be used through TI provided API 590 Versatile Instruct...

Page 591: ...CT_READ R 0h R W 0h Table 7 48 FVHVCT3 Register Field Descriptions Bit Field Type Reset Description 31 20 RESERVED R 0h Internal Only to be used through TI provided API 19 16 WCT R W Fh Internal Only to be used through TI provided API 15 4 RESERVED R 0h Internal Only to be used through TI provided API 3 0 VHVCT_READ R W 0h Internal Only to be used through TI provided API 591 SWCU117C February 2015...

Page 592: ...T R 0h R W 8h R 0h R W 0h Table 7 49 FVNVCT Register Field Descriptions Bit Field Type Reset Description 31 13 RESERVED R 0h Internal Only to be used through TI provided API 12 8 VCG2P5CT R W 8h Internal Only to be used through TI provided API 7 5 RESERVED R 0h Internal Only to be used through TI provided API 4 0 VIN_CT R W 0h Internal Only to be used through TI provided API 592 Versatile Instruct...

Page 593: ... 7 6 5 4 3 2 1 0 VSL_P RESERVED R W 8h R 0h Table 7 50 FVSLP Register Field Descriptions Bit Field Type Reset Description 31 16 RESERVED R 0h Internal Only to be used through TI provided API 15 12 VSL_P R W 8h Internal Only to be used through TI provided API 11 0 RESERVED R 0h Internal Only to be used through TI provided API 593 SWCU117C February 2015 Revised September 2015 Versatile Instruction M...

Page 594: ...SERVED R 0h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED VWLCT_P R 0h R W 8h Table 7 51 FVWLCT Register Field Descriptions Bit Field Type Reset Description 31 5 RESERVED R 0h Internal Only to be used through TI provided API 4 0 VWLCT_P R W 8h Internal Only to be used through TI provided API 594 Versatile Instruction Memory System VIMS SWCU117C February 2015 Revised September 2015 Submit Document...

Page 595: ... TI provided API 26 24 CHAIN_SEL R W 7h Internal Only to be used through TI provided API 23 18 RESERVED R 0h Internal Only to be used through TI provided API 17 WRITE_EN R W 0h Internal Only to be used through TI provided API 16 BP_SEL R W 1h Internal Only to be used through TI provided API 15 9 RESERVED R 0h Internal Only to be used through TI provided API 8 EF_CLRZ R W 1h Internal Only to be use...

Page 596: ...SERVED R 0h 15 14 13 12 11 10 9 8 RESERVED R 0h 7 6 5 4 3 2 1 0 RESERVED SHIFT_DONE R 0h R W1C 0h Table 7 53 FEFUSESTAT Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R 0h Internal Only to be used through TI provided API 0 SHIFT_DONE R W1C 0h Internal Only to be used through TI provided API 596 Versatile Instruction Memory System VIMS SWCU117C February 2015 Revised Sept...

Page 597: ...1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FEFUSEDATA R W 0h Table 7 54 FEFUSEDATA Register Field Descriptions Bit Field Type Reset Description 31 0 FEFUSEDATA R W 0h Internal Only to be used through TI provided API 597 SWCU117C February 2015 Revised September 2015 Versatile Instruction Memory System VIMS Submit Documentation Feedback Copyright 2015 Texas ...

Page 598: ...ovided API 27 24 TRIM_3P4 R W 5h Internal Only to be used through TI provided API 23 22 RESERVED R 0h Internal Only to be used through TI provided API 21 20 TRIM_1P7 R W 0h Internal Only to be used through TI provided API 19 16 TRIM_0P8 R W 8h Internal Only to be used through TI provided API 15 RESERVED R 0h Internal Only to be used through TI provided API 14 12 VIN_AT_X R W 0h Internal Only to be...

Page 599: ...through TI provided API 18 RWAIT2_FLCLK R W 0h Internal Only to be used through TI provided API 17 RWAIT_FLCLK R W 0h Internal Only to be used through TI provided API 16 FLCLKEN R W 0h Internal Only to be used through TI provided API 15 9 RESERVED R 0h Internal Only to be used through TI provided API 8 CTRLENZ R W 1h Internal Only to be used through TI provided API 7 RESERVED R 0h Internal Only to...

Page 600: ...R W 1h R W 1h Table 7 57 FPSTROBES Register Field Descriptions Bit Field Type Reset Description 31 9 RESERVED R 0h Internal Only to be used through TI provided API 8 EXECUTEZ R W 1h Internal Only to be used through TI provided API 7 2 RESERVED R 0h Internal Only to be used through TI provided API 1 V3PWRDNZ R W 1h Internal Only to be used through TI provided API 0 V5PWRDNZ R W 1h Internal Only to ...

Page 601: ... RESERVED R 0h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED MODE R 0h R W 0h Table 7 58 FBMODE Register Field Descriptions Bit Field Type Reset Description 31 3 RESERVED R 0h Internal Only to be used through TI provided API 2 0 MODE R W 0h Internal Only to be used through TI provided API 601 SWCU117C February 2015 Revised September 2015 Versatile Instruction Memory System VIMS Submit Documentati...

Page 602: ... 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED TCR R 0h R W 0h Table 7 59 FTCR Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Internal Only to be used through TI provided API 6 0 TCR R W 0h Internal Only to be used through TI provided API 602 Versatile Instruction Memory System VIMS SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback ...

Page 603: ...1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FADDR R W 0h Table 7 60 FADDR Register Field Descriptions Bit Field Type Reset Description 31 0 FADDR R W 0h Internal Only to be used through TI provided API 603 SWCU117C February 2015 Revised September 2015 Versatile Instruction Memory System VIMS Submit Documentation Feedback Copyright 2015 Texas Instruments Inc...

Page 604: ...0h R 0h Table 7 61 FTCTL Register Field Descriptions Bit Field Type Reset Description 31 17 RESERVED R 0h Internal Only to be used through TI provided API 16 WDATA_BLK_CLR R W 0h Internal Only to be used through TI provided API 15 2 RESERVED R 0h Internal Only to be used through TI provided API 1 TEST_EN R W 0h Internal Only to be used through TI provided API 0 RESERVED R 0h Internal Only to be us...

Page 605: ... 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FWPWRITE0 R W FFFFFFFFh Table 7 62 FWPWRITE0 Register Field Descriptions Bit Field Type Reset Description 31 0 FWPWRITE0 R W FFFFFFFFh Internal Only to be used through TI provided API 605 SWCU117C February 2015 Revised September 2015 Versatile Instruction Memory System VIMS Submit Documentation Feedback Copyright 2015...

Page 606: ... 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FWPWRITE1 R W FFFFFFFFh Table 7 63 FWPWRITE1 Register Field Descriptions Bit Field Type Reset Description 31 0 FWPWRITE1 R W FFFFFFFFh Internal Only to be used through TI provided API 606 Versatile Instruction Memory System VIMS SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015...

Page 607: ... 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FWPWRITE2 R W FFFFFFFFh Table 7 64 FWPWRITE2 Register Field Descriptions Bit Field Type Reset Description 31 0 FWPWRITE2 R W FFFFFFFFh Internal Only to be used through TI provided API 607 SWCU117C February 2015 Revised September 2015 Versatile Instruction Memory System VIMS Submit Documentation Feedback Copyright 2015...

Page 608: ... 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FWPWRITE3 R W FFFFFFFFh Table 7 65 FWPWRITE3 Register Field Descriptions Bit Field Type Reset Description 31 0 FWPWRITE3 R W FFFFFFFFh Internal Only to be used through TI provided API 608 Versatile Instruction Memory System VIMS SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015...

Page 609: ... 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FWPWRITE4 R W FFFFFFFFh Table 7 66 FWPWRITE4 Register Field Descriptions Bit Field Type Reset Description 31 0 FWPWRITE4 R W FFFFFFFFh Internal Only to be used through TI provided API 609 SWCU117C February 2015 Revised September 2015 Versatile Instruction Memory System VIMS Submit Documentation Feedback Copyright 2015...

Page 610: ... 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FWPWRITE5 R W FFFFFFFFh Table 7 67 FWPWRITE5 Register Field Descriptions Bit Field Type Reset Description 31 0 FWPWRITE5 R W FFFFFFFFh Internal Only to be used through TI provided API 610 Versatile Instruction Memory System VIMS SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015...

Page 611: ... 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FWPWRITE6 R W FFFFFFFFh Table 7 68 FWPWRITE6 Register Field Descriptions Bit Field Type Reset Description 31 0 FWPWRITE6 R W FFFFFFFFh Internal Only to be used through TI provided API 611 SWCU117C February 2015 Revised September 2015 Versatile Instruction Memory System VIMS Submit Documentation Feedback Copyright 2015...

Page 612: ... 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FWPWRITE7 R W FFFFFFFFh Table 7 69 FWPWRITE7 Register Field Descriptions Bit Field Type Reset Description 31 0 FWPWRITE7 R W FFFFFFFFh Internal Only to be used through TI provided API 612 Versatile Instruction Memory System VIMS SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015...

Page 613: ...BYTES31_24 R W FFh R W FFh Table 7 70 FWPWRITE_ECC Register Field Descriptions Bit Field Type Reset Description 31 24 ECCBYTES07_00 R W FFh Internal Only to be used through TI provided API 23 16 ECCBYTES15_08 R W FFh Internal Only to be used through TI provided API 15 8 ECCBYTES23_16 R W FFh Internal Only to be used through TI provided API 7 0 ECCBYTES31_24 R W FFh Internal Only to be used through...

Page 614: ...16 RESERVED R 0h 15 14 13 12 11 10 9 8 RESERVED R 0h 7 6 5 4 3 2 1 0 RESERVED SAFELV R 0h R 1h Table 7 71 FSWSTAT Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R 0h Internal Only to be used through TI provided API 0 SAFELV R 1h Internal Only to be used through TI provided API 614 Versatile Instruction Memory System VIMS SWCU117C February 2015 Revised September 2015 Sub...

Page 615: ...17 16 RESERVED R 0h 15 14 13 12 11 10 9 8 RESERVED R 0h 7 6 5 4 3 2 1 0 RESERVED CLKSEL R 0h R 1h Table 7 72 FSM_GLBCTL Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R 0h Internal Only to be used through TI provided API 0 CLKSEL R 1h Internal Only to be used through TI provided API 615 SWCU117C February 2015 Revised September 2015 Versatile Instruction Memory System VI...

Page 616: ...Reset Description 31 12 RESERVED R 0h Internal Only to be used through TI provided API 11 CTRLENZ R 1h Internal Only to be used through TI provided API 10 EXECUTEZ R 1h Internal Only to be used through TI provided API 9 RESERVED R 0h Internal Only to be used through TI provided API 8 FSM_ACT R 0h Internal Only to be used through TI provided API 7 TIOTP_ACT R 0h Internal Only to be used through TI ...

Page 617: ...N_OP OVR_PUL_CN INV_DAT T R 0h R 1h R 0h R 0h Table 7 74 FSM_STAT Register Field Descriptions Bit Field Type Reset Description 31 3 RESERVED R 0h Internal Only to be used through TI provided API 2 NON_OP R 1h Internal Only to be used through TI provided API 1 OVR_PUL_CNT R 0h Internal Only to be used through TI provided API 0 INV_DAT R 0h Internal Only to be used through TI provided API 617 SWCU11...

Page 618: ... 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED FSMCMD R 0h R W 0h Table 7 75 FSM_CMD Register Field Descriptions Bit Field Type Reset Description 31 6 RESERVED R 0h Internal Only to be used through TI provided API 5 0 FSMCMD R W 0h Internal Only to be used through TI provided API 618 Versatile Instruction Memory System VIMS SWCU117C February 2015 Revised September 2015 Submit Documentation ...

Page 619: ... 1 0 RESERVED PGM_OSU ERA_OSU R 0h R W 0h R W 0h Table 7 76 FSM_PE_OSU Register Field Descriptions Bit Field Type Reset Description 31 16 RESERVED R 0h Internal Only to be used through TI provided API 15 8 PGM_OSU R W 0h Internal Only to be used through TI provided API 7 0 ERA_OSU R W 0h Internal Only to be used through TI provided API 619 SWCU117C February 2015 Revised September 2015 Versatile In...

Page 620: ... 7 6 5 4 3 2 1 0 VSTAT_CNT RESERVED R W 3h R 0h Table 7 77 FSM_VSTAT Register Field Descriptions Bit Field Type Reset Description 31 16 RESERVED R 0h Internal Only to be used through TI provided API 15 12 VSTAT_CNT R W 3h Internal Only to be used through TI provided API 11 0 RESERVED R 0h Internal Only to be used through TI provided API 620 Versatile Instruction Memory System VIMS SWCU117C Februar...

Page 621: ... 1 0 RESERVED PGM_VSU ERA_VSU R 0h R W 0h R W 0h Table 7 78 FSM_PE_VSU Register Field Descriptions Bit Field Type Reset Description 31 16 RESERVED R 0h Internal Only to be used through TI provided API 15 8 PGM_VSU R W 0h Internal Only to be used through TI provided API 7 0 ERA_VSU R W 0h Internal Only to be used through TI provided API 621 SWCU117C February 2015 Revised September 2015 Versatile In...

Page 622: ...9 8 7 6 5 4 3 2 1 0 ADD_EXZ RESERVED R W 0h R 0h Table 7 79 FSM_CMP_VSU Register Field Descriptions Bit Field Type Reset Description 31 16 RESERVED R 0h Internal Only to be used through TI provided API 15 12 ADD_EXZ R W 0h Internal Only to be used through TI provided API 11 0 RESERVED R 0h Internal Only to be used through TI provided API 622 Versatile Instruction Memory System VIMS SWCU117C Februa...

Page 623: ... 1 0 RESERVED REP_VSU EXE_VALD R 0h R W 3h R W 1h Table 7 80 FSM_EX_VAL Register Field Descriptions Bit Field Type Reset Description 31 16 RESERVED R 0h Internal Only to be used through TI provided API 15 8 REP_VSU R W 3h Internal Only to be used through TI provided API 7 0 EXE_VALD R W 1h Internal Only to be used through TI provided API 623 SWCU117C February 2015 Revised September 2015 Versatile ...

Page 624: ... 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RD_H R 0h R W 5Ah Table 7 81 FSM_RD_H Register Field Descriptions Bit Field Type Reset Description 31 8 RESERVED R 0h Internal Only to be used through TI provided API 7 0 RD_H R W 5Ah Internal Only to be used through TI provided API 624 Versatile Instruction Memory System VIMS SWCU117C February 2015 Revised September 2015 Submit Documentatio...

Page 625: ...2 1 0 RESERVED PGM_OH RESERVED R 0h R W 1h R 0h Table 7 82 FSM_P_OH Register Field Descriptions Bit Field Type Reset Description 31 16 RESERVED R 0h Internal Only to be used through TI provided API 15 8 PGM_OH R W 1h Internal Only to be used through TI provided API 7 0 RESERVED R 0h Internal Only to be used through TI provided API 625 SWCU117C February 2015 Revised September 2015 Versatile Instruc...

Page 626: ...18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED ERA_OH R 0h R W 1h Table 7 83 FSM_ERA_OH Register Field Descriptions Bit Field Type Reset Description 31 16 RESERVED R 0h Internal Only to be used through TI provided API 15 0 ERA_OH R W 1h Internal Only to be used through TI provided API 626 Versatile Instruction Memory System VIMS SWCU117C February 2015 Revised September 2015 Submit Documen...

Page 627: ... 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED SAV_P_PUL R 0h R 0h Table 7 84 FSM_SAV_PPUL Register Field Descriptions Bit Field Type Reset Description 31 12 RESERVED R 0h Internal Only to be used through TI provided API 11 0 SAV_P_PUL R 0h Internal Only to be used through TI provided API 627 SWCU117C February 2015 Revised September 2015 Versatile Instruction Memory System VIMS Submit Do...

Page 628: ... 3 2 1 0 RESERVED PGM_VH ERA_VH R 0h R W 1h R 0h Table 7 85 FSM_PE_VH Register Field Descriptions Bit Field Type Reset Description 31 16 RESERVED R 0h Internal Only to be used through TI provided API 15 8 PGM_VH R W 1h Internal Only to be used through TI provided API 7 0 ERA_VH R 0h Internal Only to be used through TI provided API 628 Versatile Instruction Memory System VIMS SWCU117C February 2015...

Page 629: ... 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED PROG_PUL_WIDTH R 0h R W 0h Table 7 86 FSM_PRG_PW Register Field Descriptions Bit Field Type Reset Description 31 16 RESERVED R 0h Internal Only to be used through TI provided API 15 0 PROG_PUL_WIDTH R W 0h Internal Only to be used through TI provided API 629 SWCU117C February 2015 Revised September 2015 Versatile Instruction Memory System VIMS Submit...

Page 630: ...1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FSM_ERA_PW R W 0h Table 7 87 FSM_ERA_PW Register Field Descriptions Bit Field Type Reset Description 31 0 FSM_ERA_PW R W 0h Internal Only to be used through TI provided API 630 Versatile Instruction Memory System VIMS SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Texas ...

Page 631: ...9 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED SAV_ERA_PUL R 0h R 0h Table 7 88 FSM_SAV_ERA_PUL Register Field Descriptions Bit Field Type Reset Description 31 12 RESERVED R 0h Internal Only to be used through TI provided API 11 0 SAV_ERA_PUL R 0h Internal Only to be used through TI provided API 631 SWCU117C February 2015 Revised September 2015 Versatile Instruction Memory System VIMS S...

Page 632: ... 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FSM_TIMER R 0h Table 7 89 FSM_TIMER Register Field Descriptions Bit Field Type Reset Description 31 0 FSM_TIMER R 0h Internal Only to be used through TI provided API 632 Versatile Instruction Memory System VIMS SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Texas Instr...

Page 633: ... Internal Only to be used through TI provided API 19 18 RDV_SUBMODE R 0h Internal Only to be used through TI provided API 17 16 PGM_SUBMODE R 0h Internal Only to be used through TI provided API 15 14 ERA_SUBMODE R 0h Internal Only to be used through TI provided API 13 12 SUBMODE R 0h Internal Only to be used through TI provided API 11 9 SAV_PGM_CMD R 0h Internal Only to be used through TI provided...

Page 634: ...15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PGM_ADDR R 0h Table 7 91 FSM_PGM Register Field Descriptions Bit Field Type Reset Description 31 26 RESERVED R 0h Internal Only to be used through TI provided API 25 23 PGM_BANK R 0h Internal Only to be used through TI provided API 22 0 PGM_ADDR R 0h Internal Only to be used through TI provided API 634 Versatile Instruction Memory System VIMS SWCU117C February...

Page 635: ...15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ERA_ADDR R 0h Table 7 92 FSM_ERA Register Field Descriptions Bit Field Type Reset Description 31 26 RESERVED R 0h Internal Only to be used through TI provided API 25 23 ERA_BANK R 0h Internal Only to be used through TI provided API 22 0 ERA_ADDR R 0h Internal Only to be used through TI provided API 635 SWCU117C February 2015 Revised September 2015 Versatile In...

Page 636: ...X_PRG_PUL R 0h R W 32h Table 7 93 FSM_PRG_PUL Register Field Descriptions Bit Field Type Reset Description 31 20 RESERVED R 0h Internal Only to be used through TI provided API 19 16 BEG_EC_LEVEL R W 4h Internal Only to be used through TI provided API 15 12 RESERVED R 0h Internal Only to be used through TI provided API 11 0 MAX_PRG_PUL R W 32h Internal Only to be used through TI provided API 636 Ve...

Page 637: ...X_ERA_PUL R 0h R W BB8h Table 7 94 FSM_ERA_PUL Register Field Descriptions Bit Field Type Reset Description 31 20 RESERVED R 0h Internal Only to be used through TI provided API 19 16 MAX_EC_LEVEL R W 4h Internal Only to be used through TI provided API 15 12 RESERVED R 0h Internal Only to be used through TI provided API 11 0 MAX_ERA_PUL R W BB8h Internal Only to be used through TI provided API 637 ...

Page 638: ...15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED R 0h Table 7 95 FSM_STEP_SIZE Register Field Descriptions Bit Field Type Reset Description 31 25 RESERVED R 0h Internal Only to be used through TI provided API 24 16 EC_STEP_SIZE R W 0h Internal Only to be used through TI provided API 15 0 RESERVED R 0h Internal Only to be used through TI provided API 638 Versatile Instruction Memory System VIMS SWCU1...

Page 639: ...VED PUL_CNTR R 0h R 0h Table 7 96 FSM_PUL_CNTR Register Field Descriptions Bit Field Type Reset Description 31 25 RESERVED R 0h Internal Only to be used through TI provided API 24 16 CUR_EC_LEVEL R 0h Internal Only to be used through TI provided API 15 12 RESERVED R 0h Internal Only to be used through TI provided API 11 0 PUL_CNTR R 0h Internal Only to be used through TI provided API 639 SWCU117C ...

Page 640: ... 16 RESERVED R 0h 15 14 13 12 11 10 9 8 RESERVED R 0h 7 6 5 4 3 2 1 0 RESERVED EC_STEP_HEIGHT R 0h R W 0h Table 7 97 FSM_EC_STEP_HEIGHT Register Field Descriptions Bit Field Type Reset Description 31 4 RESERVED R 0h Internal Only to be used through TI provided API 3 0 EC_STEP_HEIGHT R W 0h Internal Only to be used through TI provided API 640 Versatile Instruction Memory System VIMS SWCU117C Februa...

Page 641: ... Only to be used through TI provided API 19 RANDOM R W 0h Internal Only to be used through TI provided API 18 RV_SEC_EN R W 0h Internal Only to be used through TI provided API 17 RV_RES R W 0h Internal Only to be used through TI provided API 16 RV_INT_EN R W 0h Internal Only to be used through TI provided API 15 RESERVED R 0h Internal Only to be used through TI provided API 14 ONE_TIME_GOOD R W 0h...

Page 642: ... 3 2 1 0 RESERVED BLK_TIOTP BLK_OTP R 0h R W 0h R W 0h Table 7 99 FSM_FLES Register Field Descriptions Bit Field Type Reset Description 31 12 RESERVED R 0h Internal Only to be used through TI provided API 11 8 BLK_TIOTP R W 0h Internal Only to be used through TI provided API 7 0 BLK_OTP R W 0h Internal Only to be used through TI provided API 642 Versatile Instruction Memory System VIMS SWCU117C Fe...

Page 643: ... 16 RESERVED R 0h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED WR_ENA R 0h R W 2h Table 7 100 FSM_WR_ENA Register Field Descriptions Bit Field Type Reset Description 31 3 RESERVED R 0h Internal Only to be used through TI provided API 2 0 WR_ENA R W 2h Internal Only to be used through TI provided API 643 SWCU117C February 2015 Revised September 2015 Versatile Instruction Memory System VIMS Submit...

Page 644: ...r 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FSM_ACC_PP R 0h Table 7 101 FSM_ACC_PP Register Field Descriptions Bit Field Type Reset Description 31 0 FSM_ACC_PP R 0h Internal Only to be used through TI provided API 644 Versatile Instruction Memory System VIMS SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Texas ...

Page 645: ...19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED ACC_EP R 0h R 0h Table 7 102 FSM_ACC_EP Register Field Descriptions Bit Field Type Reset Description 31 16 RESERVED R 0h Internal Only to be used through TI provided API 15 0 ACC_EP R 0h Internal Only to be used through TI provided API 645 SWCU117C February 2015 Revised September 2015 Versatile Instruction Memory System VIMS Submit Documen...

Page 646: ... 0h 15 14 13 12 11 10 9 8 CUR_ADDR R 0h 7 6 5 4 3 2 1 0 CUR_ADDR R 0h Table 7 103 FSM_ADDR Register Field Descriptions Bit Field Type Reset Description 31 RESERVED R 0h Internal Only to be used through TI provided API 30 28 BANK R 0h Internal Only to be used through TI provided API 27 0 CUR_ADDR R 0h Internal Only to be used through TI provided API 646 Versatile Instruction Memory System VIMS SWCU...

Page 647: ...TOR SEC_OUT R 0h R 0h R 0h Table 7 104 FSM_SECTOR Register Field Descriptions Bit Field Type Reset Description 31 16 SECT_ERASED R W FFFFh Internal Only to be used through TI provided API 15 8 FSM_SECTOR_EXTENSI R 0h Internal Only to be used through TI provided API ON 7 4 SECTOR R 0h Internal Only to be used through TI provided API 3 0 SEC_OUT R 0h Internal Only to be used through TI provided API ...

Page 648: ... 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MOD_VERSION CONFIG_CRC R X R X Table 7 105 FMC_REV_ID Register Field Descriptions Bit Field Type Reset Description 31 12 MOD_VERSION R X Internal Only to be used through TI provided API 11 0 CONFIG_CRC R X Internal Only to be used through TI provided API 648 Versatile Instruction Memory System VIMS SWCU117C February 2015 Revised September 2015 Submit Do...

Page 649: ...5 4 3 2 1 0 FSM_ERR_ADDR RESERVED FSM_ERR_BANK R 0h R 0h R 0h Table 7 106 FSM_ERR_ADDR Register Field Descriptions Bit Field Type Reset Description 31 8 FSM_ERR_ADDR R 0h Internal Only to be used through TI provided API 7 4 RESERVED R 0h Internal Only to be used through TI provided API 3 0 FSM_ERR_BANK R 0h Internal Only to be used through TI provided API 649 SWCU117C February 2015 Revised Septemb...

Page 650: ...6 RESERVED R 0h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED FSM_PGM_MAXPUL R 0h R 0h Table 7 107 FSM_PGM_MAXPUL Register Field Descriptions Bit Field Type Reset Description 31 12 RESERVED R 0h Internal Only to be used through TI provided API 11 0 FSM_PGM_MAXPUL R 0h Internal Only to be used through TI provided API 650 Versatile Instruction Memory System VIMS SWCU117C February 2015 Revised Septe...

Page 651: ...ED FSMEXECUTE R 0h R W Ah Table 7 108 FSM_EXECUTE Register Field Descriptions Bit Field Type Reset Description 31 20 RESERVED R 0h Internal Only to be used through TI provided API 19 16 SUSPEND_NOW R W Ah Internal Only to be used through TI provided API 15 5 RESERVED R 0h Internal Only to be used through TI provided API 4 0 FSMEXECUTE R W Ah Internal Only to be used through TI provided API 651 SWC...

Page 652: ...30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FSM_SECTOR1 R W FFFFFFFFh Table 7 109 FSM_SECTOR1 Register Field Descriptions Bit Field Type Reset Description 31 0 FSM_SECTOR1 R W FFFFFFFFh Internal Only to be used through TI provided API 652 Versatile Instruction Memory System VIMS SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyr...

Page 653: ...31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FSM_SECTOR2 R W 0h Table 7 110 FSM_SECTOR2 Register Field Descriptions Bit Field Type Reset Description 31 0 FSM_SECTOR2 R W 0h Internal Only to be used through TI provided API 653 SWCU117C February 2015 Revised September 2015 Versatile Instruction Memory System VIMS Submit Documentation Feedback Copyright 2015 T...

Page 654: ...31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FSM_BSLE0 R W 0h Table 7 111 FSM_BSLE0 Register Field Descriptions Bit Field Type Reset Description 31 0 FSM_BSLE0 R W 0h Internal Only to be used through TI provided API 654 Versatile Instruction Memory System VIMS SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Texas I...

Page 655: ... 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FSM_BSL1 R W 0h Table 7 112 FSM_BSLE1 Register Field Descriptions Bit Field Type Reset Description 31 0 FSM_BSL1 R W 0h Internal Only to be used through TI provided API 655 SWCU117C February 2015 Revised September 2015 Versatile Instruction Memory System VIMS Submit Documentation Feedback Copyright 2015 Texas In...

Page 656: ...31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FSM_BSLP0 R W 0h Table 7 113 FSM_BSLP0 Register Field Descriptions Bit Field Type Reset Description 31 0 FSM_BSLP0 R W 0h Internal Only to be used through TI provided API 656 Versatile Instruction Memory System VIMS SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Texas I...

Page 657: ... 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FSM_BSL1 R W 0h Table 7 114 FSM_BSLP1 Register Field Descriptions Bit Field Type Reset Description 31 0 FSM_BSL1 R W 0h Internal Only to be used through TI provided API 657 SWCU117C February 2015 Revised September 2015 Versatile Instruction Memory System VIMS Submit Documentation Feedback Copyright 2015 Texas In...

Page 658: ...0 MAIN_BANK_WIDTH MAIN_NUM_BANK R 40h R 1h Table 7 115 FCFG_BANK Register Field Descriptions Bit Field Type Reset Description 31 20 EE_BANK_WIDTH R 0h Internal Only to be used through TI provided API 19 16 EE_NUM_BANK R 0h Internal Only to be used through TI provided API 15 4 MAIN_BANK_WIDTH R 40h Internal Only to be used through TI provided API 3 0 MAIN_NUM_BANK R 1h Internal Only to be used thro...

Page 659: ...ernal Only to be used through TI provided API 20 MEM_MAP R 0h Internal Only to be used through TI provided API 19 16 CPU2 R 0h Internal Only to be used through TI provided API 15 12 EE_IN_MAIN R 9h Internal Only to be used through TI provided API 11 ROM R 0h Internal Only to be used through TI provided API 10 IFLUSH R 0h Internal Only to be used through TI provided API 9 SIL3 R 0h Internal Only to...

Page 660: ...ion 31 28 B7_TYPE R 0h Internal Only to be used through TI provided API 27 24 B6_TYPE R 0h Internal Only to be used through TI provided API 23 20 B5_TYPE R 0h Internal Only to be used through TI provided API 19 16 B4_TYPE R 0h Internal Only to be used through TI provided API 15 12 B3_TYPE R 0h Internal Only to be used through TI provided API 11 8 B2_TYPE R 0h Internal Only to be used through TI pr...

Page 661: ... 14 13 12 11 10 9 8 B0_START_ADDR R 0h 7 6 5 4 3 2 1 0 B0_START_ADDR R 0h Table 7 118 FCFG_B0_START Register Field Descriptions Bit Field Type Reset Description 31 28 B0_MAX_SECTOR R 0h Internal Only to be used through TI provided API 27 24 B0_MUX_FACTOR R 2h Internal Only to be used through TI provided API 23 0 B0_START_ADDR R 0h Internal Only to be used through TI provided API 661 SWCU117C Febru...

Page 662: ... 13 12 11 10 9 8 B1_START_ADDR R 0h 7 6 5 4 3 2 1 0 B1_START_ADDR R 0h Table 7 119 FCFG_B1_START Register Field Descriptions Bit Field Type Reset Description 31 28 B1_MAX_SECTOR R 0h Internal Only to be used through TI provided API 27 24 B1_MUX_FACTOR R 0h Internal Only to be used through TI provided API 23 0 B1_START_ADDR R 0h Internal Only to be used through TI provided API 662 Versatile Instruc...

Page 663: ... 13 12 11 10 9 8 B2_START_ADDR R 0h 7 6 5 4 3 2 1 0 B2_START_ADDR R 0h Table 7 120 FCFG_B2_START Register Field Descriptions Bit Field Type Reset Description 31 28 B2_MAX_SECTOR R 0h Internal Only to be used through TI provided API 27 24 B2_MUX_FACTOR R 0h Internal Only to be used through TI provided API 23 0 B2_START_ADDR R 0h Internal Only to be used through TI provided API 663 SWCU117C February...

Page 664: ... 13 12 11 10 9 8 B3_START_ADDR R 0h 7 6 5 4 3 2 1 0 B3_START_ADDR R 0h Table 7 121 FCFG_B3_START Register Field Descriptions Bit Field Type Reset Description 31 28 B3_MAX_SECTOR R 0h Internal Only to be used through TI provided API 27 24 B3_MUX_FACTOR R 0h Internal Only to be used through TI provided API 23 0 B3_START_ADDR R 0h Internal Only to be used through TI provided API 664 Versatile Instruc...

Page 665: ... 13 12 11 10 9 8 B4_START_ADDR R 0h 7 6 5 4 3 2 1 0 B4_START_ADDR R 0h Table 7 122 FCFG_B4_START Register Field Descriptions Bit Field Type Reset Description 31 28 B4_MAX_SECTOR R 0h Internal Only to be used through TI provided API 27 24 B4_MUX_FACTOR R 0h Internal Only to be used through TI provided API 23 0 B4_START_ADDR R 0h Internal Only to be used through TI provided API 665 SWCU117C February...

Page 666: ... 13 12 11 10 9 8 B5_START_ADDR R 0h 7 6 5 4 3 2 1 0 B5_START_ADDR R 0h Table 7 123 FCFG_B5_START Register Field Descriptions Bit Field Type Reset Description 31 28 B5_MAX_SECTOR R 0h Internal Only to be used through TI provided API 27 24 B5_MUX_FACTOR R 0h Internal Only to be used through TI provided API 23 0 B5_START_ADDR R 0h Internal Only to be used through TI provided API 666 Versatile Instruc...

Page 667: ... 13 12 11 10 9 8 B6_START_ADDR R 0h 7 6 5 4 3 2 1 0 B6_START_ADDR R 0h Table 7 124 FCFG_B6_START Register Field Descriptions Bit Field Type Reset Description 31 28 B6_MAX_SECTOR R 0h Internal Only to be used through TI provided API 27 24 B6_MUX_FACTOR R 0h Internal Only to be used through TI provided API 23 0 B6_START_ADDR R 0h Internal Only to be used through TI provided API 667 SWCU117C February...

Page 668: ... 13 12 11 10 9 8 B7_START_ADDR R 0h 7 6 5 4 3 2 1 0 B7_START_ADDR R 0h Table 7 125 FCFG_B7_START Register Field Descriptions Bit Field Type Reset Description 31 28 B7_MAX_SECTOR R 0h Internal Only to be used through TI provided API 27 24 B7_MUX_FACTOR R 0h Internal Only to be used through TI provided API 23 0 B7_START_ADDR R 0h Internal Only to be used through TI provided API 668 Versatile Instruc...

Page 669: ...ERVED B0_SECT_SIZE R 0h R 4h Table 7 126 FCFG_B0_SSIZE0 Register Field Descriptions Bit Field Type Reset Description 31 28 RESERVED R 0h Internal Only to be used through TI provided API 27 16 B0_NUM_SECTORS R 20h Internal Only to be used through TI provided API 15 4 RESERVED R 0h Internal Only to be used through TI provided API 3 0 B0_SECT_SIZE R 4h Internal Only to be used through TI provided API...

Page 670: ...considered as reserved locations and the register contents must not be modified Table 7 127 VIMS Registers Offset Acronym Register Name Section 0h STAT Status Section 7 8 2 1 4h CTL Control Section 7 8 2 2 670 Versatile Instruction Memory System VIMS SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 671: ...he reset value may result in undefined behavior 5 IDCODE_LB_DIS R 0h Icode Dcode flash line buffer status 0 Enabled or in transition to disabled 1 Disabled and flushed 4 SYSBUS_LB_DIS R 0h Sysbus flash line buffer control 0 Enabled or in transition to disabled 1 Disabled and flushed 3 MODE_CHANGING R 0h VIMS mode change status 0 VIMS is in the mode defined by MODE 1 VIMS is in the process of chang...

Page 672: ...t clock gate functionality is bypassed 1 The in built clock gate functionality is enabled automatically gating the clock when not needed 28 6 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 5 IDCODE_LB_DIS R W 0h Icode Dcode flash line buffer control 0 Enable 1 Disable 4 SYSBUS_LB_DIS R W 0h Sysbus flash ...

Page 673: ... This section describes the CC26xx and CC13xx bootloader Topic Page 8 1 Bootloader Functionality 675 8 2 Bootloader Interfaces 675 673 SWCU117C February 2015 Revised September 2015 Bootloader Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 674: ...kdoor is implemented The CCFG parameter BL_ENABLE can enable this backdoor The backdoor functionality uses a configurable I O pin CCFG parameter BL_PIN_NO and a configurable I O pin level CCFG parameter BL_LEVEL If backdoor functionality is enabled externally applying a configurable signal level on a configurable I O pin can force a ROM bootloader entry upon reset If the backdoor is enabled and a ...

Page 675: ...the size of the packet to be sent to the device The size is always the size of the data 2 with truncation to 8 bits 2 Send the checksum of the data buffer to ensure proper transmission of the command The checksum algorithm is a sum of the data bytes 3 Send the actual data bytes 4 Wait for a single byte acknowledgment from the device that the data was properly received or that a transmission error ...

Page 676: ...ed to send zeros until a nonzero response is received that is necessary for SSI and is allowed by the UART The receiver is allowed to return zeros until it is ready to ACK or NAK the packet that is being sent Neither device transfers a nonzero byte until it has received a response after transmitting a packet Figure 8 2 Serial Bus Packet Format 8 2 1 1 Packet Acknowledge and Not Acknowledge Bytes T...

Page 677: ...ons required to use the UART port are the following two pins UART0 TX and UART0 RX The device communicating with the bootloader drives the UART0 RX pin on the CC26xx and CC13xx while the CC26xx and CC13xx devices drive the UART0 TX pin While the baud rate is flexible the UART serial format is fixed at 8 data bits no parity and 1 stop bit The bootloader automatically detects the baud rate for commu...

Page 678: ...he SSI0 TX output pin 8 2 3 Serial Bus Commands Table 8 3 lists the commands supported by the custom protocol on the UART0 and SSI0 bootloader interfaces Each command is transferred within a protocol packet The first 2 bytes within a packet are the size byte followed by the checksum byte The third byte holds the command value that identifies the command the values for all the supported commands ar...

Page 679: ...er with MSB first The ID is returned within a protocol packet Reads a specified number of elements with a specified access width 8 bits or 32 bits from a COMMAND_MEMORY_READ 0x2A 9 specified memory mapped start address The requested amount of data must be less than the maximum size of a communication packet Writes the received data in accesses with a specified width 8 or 32 bits from a specified C...

Page 680: ... be followed by a COMMAND_GET_STATUS command to ensure that the program address and program size are valid for the device On the CC26xx and CC13xx devices the flash starts at address 0x0000 0000 The command does not perform any kind of erase operation it only prepares for the following flash programming performed by COMMAND_SEND_DATA commands Required flash erase can be done by the COMMAND_BANK_ER...

Page 681: ...mmand 6 Data byte to be programmed 3 ucCommand 7 Data byte to be programmed 4 ucCommand size 1 Data byte to be programmed size 4 8 2 3 4 COMMAND_SECTOR_ERASE The COMMAND_SECTOR_ERASE command erases a specified flash sector One flash sector has the size of 4KB The command consists of one 32 bit value that is transferred MSB first The 32 bit value is the start address of the flash sector to be erase...

Page 682: ...command Status for invalid command in other words COMMAND_RET_INVALID_CMD 0x42 incorrect packet size COMMAND_RET_INVALID_ADR 0x43 Status for invalid input address COMMAND_RET_FLASH_FAIL 0x44 Status for failing flash erase or program operation 8 2 3 6 COMMAND_RESET The COMMAND_RESET command tells the bootloader to perform a system reset Use this command after downloading a new flash image to the CC...

Page 683: ...er of read repeats for each data location A read repeat count of 0x0000 0000 causes the checksum to be generated by a read of all data locations only once The command sends the ACK signal in response to the command after the actual CRC32 calculation The result is finally returned as 4 bytes MSB first in a 6 byte packet The bootloader then waits for an ACK signal from the host as a confirmation tha...

Page 684: ...0 COMMAND_MEMORY_READ This command reads a specified number of elements with a specified access type 8 or 32 bits from a specified memory mapped start address and returns the read data in a separate communication packet The requested amount of data must be less than the max size of a communication packet The specified Access Type must be either 0 or 1 The value of 0 forces 8 bits read accesses The...

Page 685: ...te Max number of data bytes for access width 0 is 247 and 244 for access width 1 NOTE This command will not succeed writing to any flash memory The format of the packet including the command is as follows unsigned char ucCommand from 9 to 255 ucCommand 0 size from 9 to 255 ucCommand 1 checksum ucCommand 2 COMMAND_MEMORY_WRITE ucCommand 3 Memory Map Address 31 24 ucCommand 4 Memory Map Address 23 1...

Page 686: ...1 to 0 Attempting to change any bit from 0 to 1 results in an error status that can be observed by a following COMMAND_GET_STATUS command The only way to change CCFG parameter value bits from 0 to 1 is by erasing the complete CCFG flash sector The command sends the ACK signal in response to the command after the actual flash programming has terminated The programming operation fails if the CCFG ar...

Page 687: ...ments during device production and contains device specific trim values and configuration The CCFG must be set by the application and contains configuration parameters for the ROM bootcode device hardware and device firmware Topic Page 9 1 Customer Configuration CCFG 689 9 2 Factory Configuration FCFG 718 687 SWCU117C February 2015 Revised September 2015 Device Configuration Submit Documentation F...

Page 688: ...cess to these module through JTAG 4 The CCFG_TAP_DAP_1 register must be set to 0x0000 0000 to disallow access to these modules through JTAG 5 The IMAGE_VALID_CONF IMAGE_VALID register must be set to 0x0000 0000 to pass control to the programmed image in Flash at boot 6 Optionally the ERASE_CONF CHIP_ERASE_DIS_N register can be set to 0x0 to disallow erasing of the Flash 7 Use the CCFG_PROT_n regis...

Page 689: ...tion 9 1 1 8 FC8h IEEE_MAC_0 IEEE MAC Address 0 Section 9 1 1 9 FCCh IEEE_MAC_1 IEEE MAC Address 1 Section 9 1 1 10 FD0h IEEE_BLE_0 IEEE BLE Address 0 Section 9 1 1 11 FD4h IEEE_BLE_1 IEEE BLE Address 1 Section 9 1 1 12 FD8h BL_CONFIG Bootloader Configuration Section 9 1 1 13 FDCh ERASE_CONF Erase Configuration Section 9 1 1 14 FE0h CCFG_TI_OPTIONS TI Options Section 9 1 1 15 FE4h CCFG_TAP_DAP_0 T...

Page 690: ... selecting the DIO to supply external 32 kHz clock as SCLK_LF when MODE_CONF SCLK_LF_OPTION is set to EXTERNAL The selected DIO will be marked as reserved by the pin driver and must therefore be set to 255 0xFF when unused 23 0 RTC_INCREMENT R W FFFFFFh Unsigned integer defining the input frequency of the external clock and is written to AON_RTC SUBSECINC VALUEINC Defined as follows EXT_LF_CLK RTC...

Page 691: ...sCtrl_DCDC_VoltageConditionalControl must be called regularly to apply this field handled automatically if using TI RTOS 19 ALT_DCDC_DITHER_EN R W 1h Enable DC DC dithering if alternate DC DC setting is enabled SIZE_AND_DIS_FLAGS DIS_ALT_DCDC_SETTING 0 0 Dither disable 1 Dither enable 18 16 ALT_DCDC_IPEAK R W 3h Inductor peak current if alternate DC DC setting is enabled SIZE_AND_DIS_FLAGS DIS_ALT...

Page 692: ...ware must not rely on the value of a reserved Writing any other value than the reset default value may result in undefined behavior 1 DIS_ALT_DCDC_SETTIN R W 1h Disable alternate DC DC settings G 0 Enable alternate DC DC settings 1 Disable alternate DC DC settings See MODE_CONF_1 ALT_DCDC_VMIN MODE_CONF_1 ALT_DCDC_DITHER_EN MODE_CONF_1 ALT_DCDC_IPEAK NOTE The DriverLib function SysCtrl_DCDC_Voltag...

Page 693: ...ower down 0 Use the DC DC during recharge in power down 1 Do not use the DC DC during recharge in power down default NOTE The DriverLib function SysCtrl_DCDC_VoltageConditionalControl must be called regularly to apply this field handled automatically if using TI RTOS 26 DCDC_ACTIVE R W 1h DC DC in active mode 0 Use the DC DC during active mode 1 Do not use the DC DC during active mode default NOTE...

Page 694: ...ved for future use Software must not rely on the value of a reserved Writing any other value than the reset default value may result in undefined behavior 17 XOSC_CAP_MOD R W 1h Enable modification delta to XOSC cap array Value specified in XOSC_CAPARRAY_DELTA 0 Apply cap array delta 1 Do not apply cap array delta default 16 HF_COMP R W 1h Reserved for future use Software must not rely on the valu...

Page 695: ...ved Writing any other value than the reset default value may result in undefined behavior 23 16 VDDR_EXT_TP25 R W FFh Reserved for future use Software must not rely on the value of a reserved Writing any other value than the reset default value may result in undefined behavior 15 8 VDDR_EXT_TP5 R W FFh Reserved for future use Software must not rely on the value of a reserved Writing any other valu...

Page 696: ...rved Writing any other value than the reset default value may result in undefined behavior 23 16 VDDR_EXT_TP105 R W FFh Reserved for future use Software must not rely on the value of a reserved Writing any other value than the reset default value may result in undefined behavior 15 8 VDDR_EXT_TP85 R W FFh Reserved for future use Software must not rely on the value of a reserved Writing any other v...

Page 697: ...0 R W FFFFh Reserved for future use Software must not rely on the value of a reserved Writing any other value than the reset default value may result in undefined behavior 15 8 RTC_COMP_P1 R W FFh Reserved for future use Software must not rely on the value of a reserved Writing any other value than the reset default value may result in undefined behavior 7 0 RTC_COMP_P2 R W FFh Reserved for future...

Page 698: ...ved for future use Software must not rely on the value of a reserved Writing any other value than the reset default value may result in undefined behavior 15 8 HF_COMP_P1 R W FFh Reserved for future use Software must not rely on the value of a reserved Writing any other value than the reset default value may result in undefined behavior 7 0 HF_COMP_P2 R W FFh Reserved for future use Software must ...

Page 699: ...14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR R W FFFFFFFFh Table 9 10 IEEE_MAC_0 Register Field Descriptions Bit Field Type Reset Description 31 0 ADDR R W FFFFFFFFh Bits 31 0 of the 64 bits custom IEEE MAC address If different from 0xFFFFFFFF then the value of this field is applied otherwise use the value from FCFG 699 SWCU117C February 2015 Revised September 2015 Device Configuration Submit Documenta...

Page 700: ...15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR R W FFFFFFFFh Table 9 11 IEEE_MAC_1 Register Field Descriptions Bit Field Type Reset Description 31 0 ADDR R W FFFFFFFFh Bits 63 32 of the 64 bits custom IEEE MAC address If different from 0xFFFFFFFF then the value of this field is applied otherwise use value from FCFG 700 Device Configuration SWCU117C February 2015 Revised September 2015 Submit Documenta...

Page 701: ... 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR R W FFFFFFFFh Table 9 12 IEEE_BLE_0 Register Field Descriptions Bit Field Type Reset Description 31 0 ADDR R W FFFFFFFFh Bits 31 0 of the 64 bits custom IEEE BLE address If different from 0xFFFFFFFF then the value of this field is applied otherwise use value from FCFG 701 SWCU117C February 2015 Revised September 2015 Device Configuration Submit Documenta...

Page 702: ...15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR R W FFFFFFFFh Table 9 13 IEEE_BLE_1 Register Field Descriptions Bit Field Type Reset Description 31 0 ADDR R W FFFFFFFFh Bits 63 32 of the 64 bits custom IEEE BLE address If different from 0xFFFFFFFF then the value of this field is applied otherwise use value from FCFG 702 Device Configuration SWCU117C February 2015 Revised September 2015 Submit Documenta...

Page 703: ...r can be accessed if IMAGE_VALID_CONF IMAGE_VALID is nonzero or BL_ENABLE is enabled and conditions for boot loader backdoor are met 0xC5 Boot loader is enabled Any other value Boot loader is disabled 23 17 RESERVED R W 7Fh Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 16 BL_LEVEL R W 1h Sets the active level of the ...

Page 704: ...a following boot caused by a reset of the MCU VD A successful chip erase operation will force the content of the flash main bank back to the state as it was when delivered by TI 0 Disable Any chip erase request detected during boot will be ignored 1 Enable Any chip erase request detected during boot will be performed by the boot FW 7 1 RESERVED R W 7Fh Software must not rely on the value of a rese...

Page 705: ...ister Field Descriptions Bit Field Type Reset Description 31 8 RESERVED R W FFFFFFh Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 7 0 TI_FA_ENABLE R W C5h TI Failure Analysis 0xC5 Enable the functionality of unlocking the TI FA TI Failure Analysis option with the unlock code All other values Disable the functionality...

Page 706: ...Enable CPU DAP 0xC5 Main CPU DAP access is enabled during power up system reset by ROM boot FW Any other value Main CPU DAP access will remain disabled out of power up system reset 15 8 PRCM_TAP_ENABLE R W C5h Enable PRCM TAP 0xC5 PRCM TAP access is enabled during power up system reset by ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI Any other value PRCM TAP ac...

Page 707: ...access is enabled during power up system reset by ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI Any other value PBIST2 TAP access will remain disabled out of power up system reset 15 8 PBIST1_TAP_ENABLE R W C5h Enable PBIST1 TAP 0xC5 PBIST1 TAP access is enabled during power up system reset by ROM boot FW if enabled by corresponding configuration value in FCFG1...

Page 708: ...7 6 5 4 3 2 1 0 IMAGE_VALID R W FFFFFFFFh Table 9 19 IMAGE_VALID_CONF Register Field Descriptions Bit Field Type Reset Description 31 0 IMAGE_VALID R W FFFFFFFFh This field must have a value of 0x00000000 in order for enabling the boot sequence to transfer control to a flash image A nonzero value forces the boot sequence to call the boot loader 708 Device Configuration SWCU117C February 2015 Revis...

Page 709: ...WRT_PROT_S WRT_PROT_S EC_7 EC_6 EC_5 EC_4 EC_3 EC_2 EC_1 EC_0 R W 1h R W 1h R W 1h R W 1h R W 1h R W 1h R W 1h R W 1h Table 9 20 CCFG_PROT_31_0 Register Field Descriptions Bit Field Type Reset Description 31 WRT_PROT_SEC_31 R W 1h 0 Sector protected 30 WRT_PROT_SEC_30 R W 1h 0 Sector protected 29 WRT_PROT_SEC_29 R W 1h 0 Sector protected 28 WRT_PROT_SEC_28 R W 1h 0 Sector protected 27 WRT_PROT_SEC...

Page 710: ...SEC_7 R W 1h 0 Sector protected 6 WRT_PROT_SEC_6 R W 1h 0 Sector protected 5 WRT_PROT_SEC_5 R W 1h 0 Sector protected 4 WRT_PROT_SEC_4 R W 1h 0 Sector protected 3 WRT_PROT_SEC_3 R W 1h 0 Sector protected 2 WRT_PROT_SEC_2 R W 1h 0 Sector protected 1 WRT_PROT_SEC_1 R W 1h 0 Sector protected 0 WRT_PROT_SEC_0 R W 1h 0 Sector protected 710 Device Configuration SWCU117C February 2015 Revised September 2...

Page 711: ..._S WRT_PROT_S WRT_PROT_S WRT_PROT_S EC_39 EC_38 EC_37 EC_36 EC_35 EC_34 EC_33 EC_32 R W 1h R W 1h R W 1h R W 1h R W 1h R W 1h R W 1h R W 1h Table 9 21 CCFG_PROT_63_32 Register Field Descriptions Bit Field Type Reset Description 31 WRT_PROT_SEC_63 R W 1h 0 Sector protected 30 WRT_PROT_SEC_62 R W 1h 0 Sector protected 29 WRT_PROT_SEC_61 R W 1h 0 Sector protected 28 WRT_PROT_SEC_60 R W 1h 0 Sector pr...

Page 712: ...C_39 R W 1h 0 Sector protected 6 WRT_PROT_SEC_38 R W 1h 0 Sector protected 5 WRT_PROT_SEC_37 R W 1h 0 Sector protected 4 WRT_PROT_SEC_36 R W 1h 0 Sector protected 3 WRT_PROT_SEC_35 R W 1h 0 Sector protected 2 WRT_PROT_SEC_34 R W 1h 0 Sector protected 1 WRT_PROT_SEC_33 R W 1h 0 Sector protected 0 WRT_PROT_SEC_32 R W 1h 0 Sector protected 712 Device Configuration SWCU117C February 2015 Revised Septe...

Page 713: ... WRT_PROT_S WRT_PROT_S WRT_PROT_S EC_71 EC_70 EC_69 EC_68 EC_67 EC_66 EC_65 EC_64 R W 1h R W 1h R W 1h R W 1h R W 1h R W 1h R W 1h R W 1h Table 9 22 CCFG_PROT_95_64 Register Field Descriptions Bit Field Type Reset Description 31 WRT_PROT_SEC_95 R W 1h 0 Sector protected 30 WRT_PROT_SEC_94 R W 1h 0 Sector protected 29 WRT_PROT_SEC_93 R W 1h 0 Sector protected 28 WRT_PROT_SEC_92 R W 1h 0 Sector prot...

Page 714: ...C_71 R W 1h 0 Sector protected 6 WRT_PROT_SEC_70 R W 1h 0 Sector protected 5 WRT_PROT_SEC_69 R W 1h 0 Sector protected 4 WRT_PROT_SEC_68 R W 1h 0 Sector protected 3 WRT_PROT_SEC_67 R W 1h 0 Sector protected 2 WRT_PROT_SEC_66 R W 1h 0 Sector protected 1 WRT_PROT_SEC_65 R W 1h 0 Sector protected 0 WRT_PROT_SEC_64 R W 1h 0 Sector protected 714 Device Configuration SWCU117C February 2015 Revised Septe...

Page 715: ...S WRT_PROT_S WRT_PROT_S WRT_PROT_S EC_103 EC_102 EC_101 EC_100 EC_99 EC_98 EC_97 EC_96 R W 1h R W 1h R W 1h R W 1h R W 1h R W 1h R W 1h R W 1h Table 9 23 CCFG_PROT_127_96 Register Field Descriptions Bit Field Type Reset Description 31 WRT_PROT_SEC_127 R W 1h 0 Sector protected 30 WRT_PROT_SEC_126 R W 1h 0 Sector protected 29 WRT_PROT_SEC_125 R W 1h 0 Sector protected 28 WRT_PROT_SEC_124 R W 1h 0 S...

Page 716: ...C_103 R W 1h 0 Sector protected 6 WRT_PROT_SEC_102 R W 1h 0 Sector protected 5 WRT_PROT_SEC_101 R W 1h 0 Sector protected 4 WRT_PROT_SEC_100 R W 1h 0 Sector protected 3 WRT_PROT_SEC_99 R W 1h 0 Sector protected 2 WRT_PROT_SEC_98 R W 1h 0 Sector protected 1 WRT_PROT_SEC_97 R W 1h 0 Sector protected 0 WRT_PROT_SEC_96 R W 1h 0 Sector protected 716 Device Configuration SWCU117C February 2015 Revised S...

Page 717: ...e used by TI bootcode RF core ROM code or are provided by TI software automatically Some of the more useful fields in FCFG are MAC_15_4_n fields which give the preprogrammed IEEE address of the chipset and the MAC_BLE_n fields that give the Bluetooth Smart address of the chipset 717 SWCU117C February 2015 Revised September 2015 Device Configuration Submit Documentation Feedback Copyright 2015 Texa...

Page 718: ...iguration of IFADC in Divide by 10 Mode Section 9 2 1 16 100h CONFIG_MISC_ADC_DIV12 Configuration of IFADC in Divide by 12 Mode Section 9 2 1 17 104h CONFIG_MISC_ADC_DIV15 Configuration of IFADC in Divide by 15 Mode Section 9 2 1 18 108h CONFIG_MISC_ADC_DIV30 Configuration of IFADC in Divide by 30 Mode Section 9 2 1 19 118h SHDW_DIE_ID_0 Shadow of JTAG_TAP EFUSE DIE_ID_0 Section 9 2 1 20 11Ch SHDW...

Page 719: ...erature Offsets in Absolute Reference Section 9 2 1 60 Mode 36Ch SOC_ADC_REF_TRIM_AND_OFFSET_E AUX_ADC Reference Trim and Offset for External Section 9 2 1 61 XT Reference Mode 370h AMPCOMP_TH1 Ampltude Compensation Threashold 1 Section 9 2 1 62 374h AMPCOMP_TH2 Ampltude Compensation Threashold 2 Section 9 2 1 63 378h AMPCOMP_CTRL1 Amplitude Compensation Control Section 9 2 1 64 37Ch ANABYPASS_VAL...

Page 720: ...Field Descriptions Bit Field Type Reset Description 31 8 RESERVED R FFFFFFh Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 7 0 DEVICE_MINOR_REV R X HW minor revision number a value of 0xFF shall be treated equally to 0x00 Any test of this field by SW must be implemented as a greater or equal comparison as signed integ...

Page 721: ...I_0_RF IFAMPCTL3 IB Value is read by RF Core ROM FW during RF Core initialization 27 24 LNA_IB R Fh Trim value for ADI_0_RF LNACTL2 IB Value is read by RF Core ROM FW during RF Core initialization 23 19 IFAMP_TRIM R 1Fh Trim value for ADI_0_RF IFAMPCTL0 TRIM Value is read by RF Core ROM FW during RF Core initialization 18 14 CTL_PA0_TRIM R 1Fh Trim value for ADI_0_RF PACTL0 TRIM Value is read by R...

Page 722: ...I_0_RF IFAMPCTL3 IB Value is read by RF Core ROM FW during RF Core initialization 27 24 LNA_IB R Fh Trim value for ADI_0_RF LNACTL2 IB Value is read by RF Core ROM FW during RF Core initialization 23 19 IFAMP_TRIM R 1Fh Trim value for ADI_0_RF IFAMPCTL0 TRIM Value is read by RF Core ROM FW during RF Core initialization 18 14 CTL_PA0_TRIM R 1Fh Trim value for ADI_0_RF PACTL0 TRIM Value is read by R...

Page 723: ... ADI_0_RF IFAMPCTL3 IB Value is read by RF Core ROM FW during RF Core initialization 27 24 LNA_IB R Fh Trim value for ADI_0_RF LNACTL2 IB Value is read by RF Core ROM FW during RF Core initialization 23 19 IFAMP_TRIM R 1Fh Trim value for ADI_0_RF IFAMPCTL0 TRIM Value is read by RF Core ROM FW during RF Core initialization 18 14 CTL_PA0_TRIM R 1Fh Trim value for ADI_0_RF PACTL0 TRIM Value is read b...

Page 724: ... ADI_0_RF IFAMPCTL3 IB Value is read by RF Core ROM FW during RF Core initialization 27 24 LNA_IB R Fh Trim value for ADI_0_RF LNACTL2 IB Value is read by RF Core ROM FW during RF Core initialization 23 19 IFAMP_TRIM R 1Fh Trim value for ADI_0_RF IFAMPCTL0 TRIM Value is read by RF Core ROM FW during RF Core initialization 18 14 CTL_PA0_TRIM R 1Fh Trim value for ADI_0_RF PACTL0 TRIM Value is read b...

Page 725: ... ADI_0_RF IFAMPCTL3 IB Value is read by RF Core ROM FW during RF Core initialization 27 24 LNA_IB R Fh Trim value for ADI_0_RF LNACTL2 IB Value is read by RF Core ROM FW during RF Core initialization 23 19 IFAMP_TRIM R 1Fh Trim value for ADI_0_RF IFAMPCTL0 TRIM Value is read by RF Core ROM FW during RF Core initialization 18 14 CTL_PA0_TRIM R 1Fh Trim value for ADI_0_RF PACTL0 TRIM Value is read b...

Page 726: ... ADI_0_RF IFAMPCTL3 IB Value is read by RF Core ROM FW during RF Core initialization 27 24 LNA_IB R Fh Trim value for ADI_0_RF LNACTL2 IB Value is read by RF Core ROM FW during RF Core initialization 23 19 IFAMP_TRIM R 1Fh Trim value for ADI_0_RF IFAMPCTL0 TRIM Value is read by RF Core ROM FW during RF Core initialization 18 14 CTL_PA0_TRIM R 1Fh Trim value for ADI_0_RF PACTL0 TRIM Value is read b...

Page 727: ...ield Type Reset Description 31 28 RESERVED R Fh Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 27 12 RFC_MDM_DEMIQMC0 R FFFFh Trim value for RFC_MDM DEMIQMC0 GAINFACTOR and RFC_MDM DEMIQMC0 PHASEFACTOR Value is read by RF Core ROM FW during RF Core initialization 11 6 LDOVCO_TRIM_OUTPU R 3Fh Trim value for ADI_1_SYNTH...

Page 728: ...ield Type Reset Description 31 28 RESERVED R Fh Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 27 12 RFC_MDM_DEMIQMC0 R FFFFh Trim value for RFC_MDM DEMIQMC0 GAINFACTOR and RFC_MDM DEMIQMC0 PHASEFACTOR Value is read by RF Core ROM FW during RF Core initialization 11 6 LDOVCO_TRIM_OUTPU R 3Fh Trim value for ADI_1_SYNTH...

Page 729: ...it Field Type Reset Description 31 28 RESERVED R Fh Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 27 12 RFC_MDM_DEMIQMC0 R FFFFh Trim value for RFC_MDM DEMIQMC0 GAINFACTOR and RFC_MDM DEMIQMC0 PHASEFACTOR Value is read by RF Core ROM FW during RF Core initialization 11 6 LDOVCO_TRIM_OUTPU R 3Fh Trim value for ADI_1_S...

Page 730: ...it Field Type Reset Description 31 28 RESERVED R Fh Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 27 12 RFC_MDM_DEMIQMC0 R FFFFh Trim value for RFC_MDM DEMIQMC0 GAINFACTOR and RFC_MDM DEMIQMC0 PHASEFACTOR Value is read by RF Core ROM FW during RF Core initialization 11 6 LDOVCO_TRIM_OUTPU R 3Fh Trim value for ADI_1_S...

Page 731: ...it Field Type Reset Description 31 28 RESERVED R Fh Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 27 12 RFC_MDM_DEMIQMC0 R FFFFh Trim value for RFC_MDM DEMIQMC0 GAINFACTOR and RFC_MDM DEMIQMC0 PHASEFACTOR Value is read by RF Core ROM FW during RF Core initialization 11 6 LDOVCO_TRIM_OUTPU R 3Fh Trim value for ADI_1_S...

Page 732: ...it Field Type Reset Description 31 28 RESERVED R Fh Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 27 12 RFC_MDM_DEMIQMC0 R FFFFh Trim value for RFC_MDM DEMIQMC0 GAINFACTOR and RFC_MDM DEMIQMC0 PHASEFACTOR Value is read by RF Core ROM FW during RF Core initialization 11 6 LDOVCO_TRIM_OUTPU R 3Fh Trim value for ADI_1_S...

Page 733: ...C_ADC_DIV5 Register Field Descriptions Bit Field Type Reset Description 31 17 RESERVED R 7FFFh Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 16 9 RSSI_OFFSET R FFh Value for RSSI measured in production test Value is read by RF Core ROM FW during RF Core initialization 8 6 QUANTCTLTHRES R 7h Trim value for ADI_0_RF IF...

Page 734: ...C_ADC_DIV6 Register Field Descriptions Bit Field Type Reset Description 31 17 RESERVED R 7FFFh Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 16 9 RSSI_OFFSET R FFh Value for RSSI measured in production test Value is read by RF Core ROM FW during RF Core initialization 8 6 QUANTCTLTHRES R 7h Trim value for ADI_0_RF IF...

Page 735: ...ISC_ADC_DIV10 Register Field Descriptions Bit Field Type Reset Description 31 17 RESERVED R 7FFFh Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 16 9 RSSI_OFFSET R FFh Value for RSSI measured in production test Value is read by RF Core ROM FW during RF Core initialization 8 6 QUANTCTLTHRES R 7h Trim value for ADI_0_RF...

Page 736: ...MISC_ADC_DIV12 Register Field Descriptions Bit Field Type Reset Description 31 17 RESERVED R 7FFFh Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 16 9 RSSI_OFFSET R FFh Value for RSSI measured in production test Value is read by RF Core ROM FW during RF Core initialization 8 6 QUANTCTLTHRES R 7h Trim value for ADI_0_R...

Page 737: ...MISC_ADC_DIV15 Register Field Descriptions Bit Field Type Reset Description 31 17 RESERVED R 7FFFh Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 16 9 RSSI_OFFSET R FFh Value for RSSI measured in production test Value is read by RF Core ROM FW during RF Core initialization 8 6 QUANTCTLTHRES R 7h Trim value for ADI_0_R...

Page 738: ...MISC_ADC_DIV30 Register Field Descriptions Bit Field Type Reset Description 31 17 RESERVED R 7FFFh Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 16 9 RSSI_OFFSET R FFh Value for RSSI measured in production test Value is read by RF Core ROM FW during RF Core initialization 8 6 QUANTCTLTHRES R 7h Trim value for ADI_0_R...

Page 739: ...9 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID_31_0 R X Table 9 44 SHDW_DIE_ID_0 Register Field Descriptions Bit Field Type Reset Description 31 0 ID_31_0 R X Shadow of EFUSE DIE_ID_0 ie efuse row number 3 Default value depends on eFuse value 739 SWCU117C February 2015 Revised September 2015 Device Configuration Submit Documentation Feedback Copyright 2015 Texas ...

Page 740: ... 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID_63_32 R X Table 9 45 SHDW_DIE_ID_1 Register Field Descriptions Bit Field Type Reset Description 31 0 ID_63_32 R X Shadow of EFUSE DIE_ID_1 ie efuse row number 4 Default value depends on eFuse value 740 Device Configuration SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Texas...

Page 741: ... 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID_95_64 R X Table 9 46 SHDW_DIE_ID_2 Register Field Descriptions Bit Field Type Reset Description 31 0 ID_95_64 R X Shadow of EFUSE DIE_ID_2 ie efuse row number 5 Default value depends on eFuse value 741 SWCU117C February 2015 Revised September 2015 Device Configuration Submit Documentation Feedback Copyright 2015 Texas...

Page 742: ...28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID_127_96 R X Table 9 47 SHDW_DIE_ID_3 Register Field Descriptions Bit Field Type Reset Description 31 0 ID_127_96 R X Shadow of EFUSE DIE_ID_3 ie efuse row number 6 Default value depends on eFuse value 742 Device Configuration SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Texa...

Page 743: ..._BIAS_LDO_TRIM SET_RCOSC_HF_COARSE_RESI STOR ie in efuse row number 11 Default value depends on eFuse value 26 23 TRIMMAG R X Shadow of EFUSE OSC_BIAS_LDO_TRIM TRIMMAG ie in efuse row number 11 Default value depends on eFuse value 22 18 TRIMIREF R X Shadow of EFUSE OSC_BIAS_LDO_TRIM TRIMIREF ie in efuse row number 11 Default value depends on eFuse value 17 16 ITRIM_DIG_LDO R X Shadow of EFUSE OSC_...

Page 744: ...mber 12 Default value depends on eFuse value 24 VDDR_ENABLE_PG1 R X Shadow of EFUSE ANA_TRIM VDDR_ENABLE_PG1 ie in efuse row number 12 Default value depends on eFuse value 23 VDDR_OK_HYS R X Shadow of EFUSE ANA_TRIM VDDR_OK_HYS ie in efuse row number 12 Default value depends on eFuse value 22 21 IPTAT_TRIM R X Shadow of EFUSE ANA_TRIM IPTAT_TRIM ie in efuse row number 12 Default value depends on e...

Page 745: ... 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LOT_NUMBER R X Table 9 50 FLASH_NUMBER Register Field Descriptions Bit Field Type Reset Description 31 0 LOT_NUMBER R X Number of the manufacturing lot that produced this unit Default value holds log information from production test 745 SWCU117C February 2015 Revised September 2015 Device Configuration Submit Documentation Feedback Copyright 2015 Tex...

Page 746: ...NATE YCOORDINATE R X R X Table 9 51 FLASH_COORDINATE Register Field Descriptions Bit Field Type Reset Description 31 16 XCOORDINATE R X X coordinate of this unit on the wafer Default value holds log information from production test 15 0 YCOORDINATE R X Y coordinate of this unit on the wafer Default value holds log information from production test 746 Device Configuration SWCU117C February 2015 Rev...

Page 747: ...by the flash device driver when an erase program operation is initiated 23 16 ESU R 33h Erase setup time in cycles Value will be written to FLASH FSM_PE_OSU ERA_OSU by the flash device driver when an erase program operation is initiated 15 8 PVSU R 1Ah Program verify setup time in cycles Value will be written to FLASH FSM_PE_VSU PGM_VSU by the flash device driver when an erase program operation is...

Page 748: ...lue will be written to FLASH FSM_EX_VAL REP_VSU by the flash device driver when an erase program operation is initiated 23 16 PV_ACCESS R Ah Program verify EXECUTEZ data valid time in half microseconds Value will be converted to number of FCLK cycles by by flash device driver and the converted value is written to FLASH FSM_EX_VAL EXE_VALD when an erase program operation is initiated 15 12 A_EXEZ_S...

Page 749: ...he converted value is written to FLASH FSM_P_OH PGM_OH when an erase program operation is initiated 23 16 RH R 6Eh Read hold mode transition time in cycles Value will be written to the RD_H field bits 7 0 of the FSM_RD_H register in the flash module by the flash device driver when an erase program operation is initiated 15 8 PVH R 2h Program verify hold time in half microseconds after SAFELV goes ...

Page 750: ...d time in half microseconds after SAFELV goes low Value will be converted to number of FCLK cycles by the flash device driver and the converted value is written to FLASH FSM_ERA_OH ERA_OH when an erase program operation is initiated 23 16 SEQ R 0h Pump sequence control 15 12 VSTAT R Fh Max number of HCLK cycles allowed for pump brown out Value will be written to FLASH FSM_VSTAT VSTAT_CNT when an e...

Page 751: ...n 31 16 VHV_E_START R 0h Starting VHV Erase CT for stairstep erase Value will be written to FLASH FSM_PRG_PUL BEG_EC_LEVEL when an erase program operation is initiated 15 0 VHV_E_STEP_HIGHT R 1h Number of VHV CTs to step after each erase pulse up to the max The actual FMC register value must be one less than this since the FMC starts counting from zero Value will be written to FLASH FSM_EC_STEP_HE...

Page 752: ...1 24 PUMP_SU R 0h Pump read non read mode transition time in half microseconds mainly for FPES 23 16 RESERVED R X Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior Default value holds trim value from production test 15 0 MAX_PP R 14h Max program pulse limit per program operation Value will be written to FLASH FSM_PRG_PUL...

Page 753: ...ns Bit Field Type Reset Description 31 16 MAX_EP R FA0h Max erase pulse limit per erase operation Value will be written to FLASH FSM_ERA_PUL MAX_ERA_PUL when an erase program operation is initiated 15 0 PROGRAM_PW R 10h Program pulse width in half microseconds Value will be converted to number of FCLK cycles by the flash device driver and the converted value is written to FLASH FSM_PRG_PW PROG_PUL...

Page 754: ... 1 0 ERASE_PW R FA0h Table 9 59 FLASH_ERA_PW Register Field Descriptions Bit Field Type Reset Description 31 0 ERASE_PW R FA0h Erase pulse width in half microseconds Value will be converted to number of FCLK cycles by the flash device driver and the converted value is written to FLASH FSM_ERA_PW FSM_ERA_PW when a erase program operation is initiated 754 Device Configuration SWCU117C February 2015 ...

Page 755: ... value of a reserved Writing any other value than the reset value may result in undefined behavior 19 16 VHV_P R X Value will be written to FLASH FVHVCT2 VHVCT_P by the flash device driver when an erase program operation is initiated Default value holds trim value from production test 15 12 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value...

Page 756: ...the flash device driver when an erase program operation is initiated Default value holds trim value from production test 23 20 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 19 16 VHV_PV R 8h Value will be written to FLASH FVHVCT1 VHVCT_PV by the flash device driver when an erase program operation is ini...

Page 757: ...6 VWL_P R X Wordline voltage applied to the selected half row during programming Value will be written to FLASH FVWLCT VWLCT_P by the flash device driver when an erase program operation is initiated Default value holds trim value from production test 15 8 V_READ R X Wordline voltage applied to the selected block during reads and verifies Value will be written to FLASH FVREADCT VREADCT by the flash...

Page 758: ...ending on partnumber 25 23 RESERVED R X Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior Default value differs depending on partnumber 22 19 SEQUENCE R X Sequence Used to differentiate between marketing orderable product where other fields of USER_ID is the same temp range flash size voltage range etc Default value diff...

Page 759: ...ase program operation is initiated Note that during a Total Erase operation the flash bank will always be erased with Precondition enabled independent of the value of this FCFG1 bit field 21 18 MAX_EC_LEVEL R 4h Value will be written to FLASH FSM_ERA_PUL MAX_EC_LEVEL by the flash device driver when a erase program operation is initiated 17 16 TRIM_1P7 R 1h Value will be written to FLASH FSEQPMP TR...

Page 760: ...e than the reset value may result in undefined behavior 24 23 SET_RCOSC_HF_FINE_ R 0h Value will be written to RESISTOR DDI_0_OSC ATESTCTL SET_RCOSC_HF_FINE_RESISTOR by boot FW while in safezone 22 ATESTLF_UDIGLDO_IBI R 1h Value will be written AS_TRIM DDI_0_OSC ATESTCTL ATESTLF_UDIGLDO_IBIAS_TRIM by boot FW while in safezone 21 16 NANOAMP_RES_TRIM R X Value will be written to DDI_0_OSC ADCDOUBLER...

Page 761: ...ed Bit Field Type Reset Description 2 0 DCDC_HIGH_EN_SEL R 7h Value will be written to ADI_3_REFSYS DCDCCTL4 HIGH_EN_SEL by boot FW while in safezone 761 SWCU117C February 2015 Revised September 2015 Device Configuration Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 762: ...D R 1Fh Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 18 16 GLDO_CURSRC R 0h Value will be written to ADI_3_REFSYS DCDCCTL0 GLDO_ISRC by boot FW while in safezone 15 13 RESERVED R 7h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 12 11 I...

Page 763: ...23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR_0_31 R X Table 9 67 MAC_BLE_0 Register Field Descriptions Bit Field Type Reset Description 31 0 ADDR_0_31 R X The first 32 bits of the 64 bit MAC BLE address Default value holds trim value from production test 763 SWCU117C February 2015 Revised September 2015 Device Configuration Submit Documentation Feedback Copyright 2015 Texas I...

Page 764: ...3 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR_32_63 R X Table 9 68 MAC_BLE_1 Register Field Descriptions Bit Field Type Reset Description 31 0 ADDR_32_63 R X The last 32 bits of the 64 bit MAC BLE address Default value holds trim value from production test 764 Device Configuration SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Texas I...

Page 765: ...5 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR_0_31 R X Table 9 69 MAC_15_4_0 Register Field Descriptions Bit Field Type Reset Description 31 0 ADDR_0_31 R X The first 32 bits of the 64 bit MAC 15 4 address Default value holds trim value from production test 765 SWCU117C February 2015 Revised September 2015 Device Configuration Submit Documentation Feedback Copyright 2015 ...

Page 766: ...5 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR_32_63 R X Table 9 70 MAC_15_4_1 Register Field Descriptions Bit Field Type Reset Description 31 0 ADDR_32_63 R X The last 32 bits of the 64 bit MAC 15 4 address Default value holds trim value from production test 766 Device Configuration SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015...

Page 767: ...ite operation is initiated 28 DIS_STANDBY_INT_WR R 1h If AON_SYSCTL PWRCTL EXT_REG_MODE 0 this value will be T written to FLASH CFG DIS_STANDBY by flash device driver FW when a flash write operation is initiated 27 DIS_IDLE_INT_WRT R 1h If AON_SYSCTL PWRCTL EXT_REG_MODE 0 this value will be written to FLASH CFG DIS_IDLE by flash device driver FW when a flash write operation is initiated 26 24 VIN_...

Page 768: ..._SYSCTL PWRCTL EXT_REG_MODE 0 this value will be written to FLASH FSEQPMP VIN_AT_X both by boot FW while in safezone and by flash device driver FW after completion of a flash write operation 7 STANDBY_MODE_SEL_ R 1h If AON_SYSCTL PWRCTL EXT_REG_MODE 1 this value will be EXT_RD written to FLASH CFG STANDBY_MODE_SEL both by boot FW while in safezone and by flash device driver FW after completion of ...

Page 769: ...MPVSLOPE R FFFFFFh R 33h Table 9 72 MISC_TRIM Register Field Descriptions Bit Field Type Reset Description 31 8 RESERVED R FFFFFFh Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 7 0 TEMPVSLOPE R 33h Signed byte value representing the TEMP slope with battery voltage in degrees C V with four fractional bits 769 SWCU117C...

Page 770: ...5 4 3 2 1 0 CTRIMFRACT_QUAD CTRIMFRACT_SLOPE R 0h R 3h Table 9 73 RCOSC_HF_TEMPCOMP Register Field Descriptions Bit Field Type Reset Description 31 24 FINE_RESISTOR R 0h Change in FINE_RESISTOR trim 23 16 CTRIM R 0h Change in CTRIM trim 15 8 CTRIMFRACT_QUAD R 0h Temp compensation quadratic CTRIMFRACT 7 0 CTRIMFRACT_SLOPE R 3h Number of CTRIMFRACT codes per 20 degrees C from default temperature 770...

Page 771: ...23 22 21 20 19 18 17 16 PG_REV WAFER_ID R 8h R B99Ah 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WAFER_ID MANUFACTURER_ID R B99Ah R 2Fh Table 9 74 ICEPICK_DEVICE_ID Register Field Descriptions Bit Field Type Reset Description 31 28 PG_REV R 8h Field used to distinguish revisions of the device 27 12 WAFER_ID R B99Ah Field used to identify silicon die 11 0 MANUFACTURER_ID R 2Fh Manufacturer code 0x02F Tex...

Page 772: ...ster Field Descriptions Bit Field Type Reset Description 31 0 REV R 23h The revision number of the FCFG1 layout This value will be read by application SW in order to determine which FCFG1 parameters that have valid values This revision number must be incremented by 1 before any devices are to be produced if the FCFG1 layout has changed since the previous production of devices Value migth change wi...

Page 773: ...se for cc26xx PG2 2 and cc13xx PG2 0 Trim value for DDI_0_OSC RCOSCHFCTL RCOSCHF_ITUNE_TRIM 27 20 RCOSC_HF_CRIM R 0h Trim value that migth become into use for cc26xx PG2 2 and cc13xx PG2 0 Trim value for DDI_0_OSC RCOSCHFCTL RCOSCHF_CTRIM 19 15 PER_M R 1h Trim value for AON_WUC OSCCFG PER_M 14 12 PER_E R 4h Trim value for AON_WUC OSCCFG PER_E 11 8 PO_TAIL_RES_TRIM R 6h Trim value for DLO_DTX PLLCT...

Page 774: ...00h R X Table 9 77 IOCONF Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R FFFFFF00h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 GPIO_CNT R X This value is written to IOC CFG GPIO_CNT by boot FW while in safezone Default value differs depending on partnumber 774 Device Configuration ...

Page 775: ...J R 6h Trim value for ADI_0_RF IFADCLFCFG0 INT3ADJ Value is read by RF Core ROM FW during RF Core initialization 19 16 FF1ADJ R 0h Trim value for ADI_0_RF IFADCLFCFG0 FF1ADJ Value is read by RF Core ROM FW during RF Core initialization 15 14 AAFCAP R 3h Trim value for ADI_0_RF IFADCCTL0 AAFCAP Value is read by RF Core ROM FW during RF Core initialization 13 10 INT2ADJ R Dh Trim value for ADI_0_RF ...

Page 776: ...escriptions Bit Field Type Reset Description 31 30 RESERVED R 3h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 29 26 XOSC_HF_ROW_Q12 R Fh Trim value for DDI_0_OSC ANABYPASSVAL1 XOSC_HF_ROW_Q12 25 10 XOSC_HF_COLUMN_Q1 R 3Fh Trim value for 2 DDI_0_OSC ANABYPASSVAL1 XOSC_HF_COLUMN_Q12 9 2 RCOSCLF_CTUNE_TRIM R X Trim val...

Page 777: ... ROM FW during RF Core initialization Default value holds trim value from production test 23 19 IFAMP_TRIM R 0h Trim value for ADI_0_RF IFAMPCTL0 TRIM Value is read by RF Core ROM FW during RF Core initialization 18 14 CTL_PA0_TRIM R X Trim value for ADI_0_RF PACTL0 TRIM Value is read by RF Core ROM FW during RF Core initialization Default value holds trim value from production test 13 PATRIMCOMPL...

Page 778: ...ed Writing any other value than the reset value may result in undefined behavior 27 12 RFC_MDM_DEMIQMC0 R FFFFh Trim value for RFC_MDM DEMIQMC0 GAINFACTOR and RFC_MDM DEMIQMC0 PHASEFACTOR Value is read by RF Core ROM FW during RF Core initialization only on cc13xx 11 6 LDOVCO_TRIM_OUTPU R X Trim value for ADI_1_SYNTH VCOLDOCTL1 TRIM_OUT T Value is read by RF Core ROM FW during RF Core initializati...

Page 779: ...N Register Field Descriptions Bit Field Type Reset Description 31 16 RESERVED R X Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior Default value holds log information from production test 15 0 SOC_ADC_ABS_GAIN_T R X SOC_ADC gain in absolute reference mode at temperature 1 30C EMP1 Calculated in production test Default v...

Page 780: ...L_GAIN Register Field Descriptions Bit Field Type Reset Description 31 16 RESERVED R X Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior Default value holds trim value from production test 15 0 SOC_ADC_REL_GAIN_T R X SOC_ADC gain in relative reference mode at temperature 1 30C EMP1 Calculated in production test Default v...

Page 781: ...lue may result in undefined behavior Default value holds trim value from production test 23 16 SOC_ADC_REL_OFFSET R X SOC_ADC offset in relative reference mode at temperature 1 30C _TEMP1 Signed 8 bit number Calculated in production test Default value holds trim value from production test 15 8 RESERVED R X Software must not rely on the value of a reserved Writing any other value than the reset val...

Page 782: ...2h 7 6 5 4 3 2 1 0 RESERVED SOC_ADC_REF_VOLTAGE_TRIM_TEMP1 R C002h R X Table 9 85 SOC_ADC_REF_TRIM_AND_OFFSET_EXT Register Field Descriptions Bit Field Type Reset Description 31 6 RESERVED R C002h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 5 0 SOC_ADC_REF_VOLTA R X Value to write in ADI_4_AUX ADCREF1 VTRIM at temp...

Page 783: ...plitude threshhold In HPM_RAMP3 if amp HPMRAMP3_LTH amp HPMRAMP3_HTH then move on HPM_UPDATE 17 16 RESERVED R 3h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 15 10 HPMRAMP3_HTH R 20h In HPM_RAMP3 if amp HPMRAMP3_LTH amp HPMRAMP3_HTH then move on to HPM_UPDATE 9 6 IBIASCAP_LPTOHP_OL_ R Ah During XOSC mode transition ...

Page 784: ...mp LPMUPDATE_HTH then move on 17 16 RESERVED R 3h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 15 10 ADC_COMP_AMPTH_LP R 0h When ADC is forced in comparator mode this value is used as M OPAMP s threshold during LPM_UPDATE mode Actual amplitude is compared against this threshhold to generate 1 bit adc_threshholdmet i...

Page 785: ...R 1h Offset values of XOSC IBIAS trim IBIAS trim value would always be greater than or equal to this offset in both HPM and LPM 19 16 IBIAS_INIT R 8h Initial value of XOSC IBIAS trim During ramping up IBIAS is set to IBIAS_OFFSET IBIAS_INIT 15 8 LPM_IBIAS_WAIT_CNT_ R 3Fh FSM waits for ddi_lpm_ibias_wait_cnt_final clock cycles in FINAL IDAC_DECREMENT_WITH_MEASURE states in order to compensate slow ...

Page 786: ...6 5 4 3 2 1 0 RESERVED XOSC_HF_IBIASTHERM R 3FFFFh R 3FFh Table 9 89 ANABYPASS_VALUE2 Register Field Descriptions Bit Field Type Reset Description 31 14 RESERVED R 3FFFFh Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 13 0 XOSC_HF_IBIASTHERM R 3FFh Value of xosc_hf_ibiastherm when oscdig is bypassed 786 Device Configu...

Page 787: ... rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 17 RSSITRIMCOMPLETE_N R X Status of RSSI trim 0 Trimmed 1 Not trimmed Default value holds trim value from production test 16 9 RSSI_OFFSET R X Value for RSSI measured in production test Value is read by RF Core ROM FW during RF Core initialization Default value holds trim value from produ...

Page 788: ...nly 23 21 RESERVED R 7h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 20 16 VDDR_TRIM_H R 1Fh Trim value for 1 85V VDDR found in production test for external VDDR load mode 15 13 RESERVED R 7h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavi...

Page 789: ...SC ADCDOUBLERNANOAMPCTL ADC_SH_VBUF_EN 28 ADC_SH_MODE_EN R 1h Trim value for DDI_0_OSC ADCDOUBLERNANOAMPCTL ADC_SH_MODE_EN 27 ATESTLF_RCOSCLF_IBI R 0h Trim value for AS_TRIM DDI_0_OSC ATESTCTL ATESTLF_RCOSCLF_IBIAS_TRIM 26 25 XOSCLF_REGULATOR_ R 0h Trim value for TRIM DDI_0_OSC LFOSCCTL XOSCLF_REGULATOR_TRIM 24 21 XOSCLF_CMIRRWR_RA R 0h Trim value for TIO DDI_0_OSC LFOSCCTL XOSCLF_CMIRRWR_RATIO 20...

Page 790: ...3 2 1 0 FLUX_CAP_0P4_TRIM R FFFFh Table 9 93 CAP_TRIM Register Field Descriptions Bit Field Type Reset Description 31 16 FLUX_CAP_0P28_TRIM R FFFFh Reserved storage of measurement value on 0 28um pitch FLUX CAP measured in production test 15 0 FLUX_CAP_0P4_TRIM R FFFFh Reserved storage of measurement value on 0 4um pitch FLUX CAP measured in production test 790 Device Configuration SWCU117C Februa...

Page 791: ...are must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 28 27 PEAK_DET_ITRIM R 0h Trim value for DDI_0_OSC XOSCHFCTL PEAK_DET_ITRIM 26 24 HP_BUF_ITRIM R 0h Trim value for DDI_0_OSC XOSCHFCTL HP_BUF_ITRIM 23 22 LP_BUF_ITRIM R 0h Trim value for DDI_0_OSC XOSCHFCTL LP_BUF_ITRIM 21 20 DBLR_LOOP_FILTER_R R 0h Trim value for ESET_VOLTAGE...

Page 792: ...9 95 PWD_CURR_20C Register Field Descriptions Bit Field Type Reset Description 31 24 DELTA_CACHE_REF R 8h Additional maximum current in units of 1uA with cache retention 23 16 DELTA_RFMEM_RET R Bh Additional maximum current in 1 µA units with RF memory retention 15 8 DELTA_XOSC_LPM R A6h Additional maximum current in units of 1 µA with XOSC_HF on in low power mode 7 0 BASELINE R 8h Worst case base...

Page 793: ...9 96 PWD_CURR_35C Register Field Descriptions Bit Field Type Reset Description 31 24 DELTA_CACHE_REF R Ch Additional maximum current in units of 1 µA with cache retention 23 16 DELTA_RFMEM_RET R 10h Additional maximum current in 1 µA units with RF memory retention 15 8 DELTA_XOSC_LPM R A5h Additional maximum current in units of 1 µA with XOSC_HF on in low power mode 7 0 BASELINE R Ah Worst case ba...

Page 794: ...9 97 PWD_CURR_50C Register Field Descriptions Bit Field Type Reset Description 31 24 DELTA_CACHE_REF R 12h Additional maximum current in units of 1 µA with cache retention 23 16 DELTA_RFMEM_RET R 18h Additional maximum current in 1 µA units with RF memory retention 15 8 DELTA_XOSC_LPM R A2h Additional maximum current in units of 1 µA with XOSC_HF on in low power mode 7 0 BASELINE R Dh Worst case b...

Page 795: ...9 98 PWD_CURR_65C Register Field Descriptions Bit Field Type Reset Description 31 24 DELTA_CACHE_REF R 1Ch Additional maximum current in units of 1 µA with cache retention 23 16 DELTA_RFMEM_RET R 25h Additional maximum current in 1 µA units with RF memory retention 15 8 DELTA_XOSC_LPM R 9Ch Additional maximum current in units of 1 µA with XOSC_HF on in low power mode 7 0 BASELINE R 14h Worst case ...

Page 796: ...9 99 PWD_CURR_80C Register Field Descriptions Bit Field Type Reset Description 31 24 DELTA_CACHE_REF R 2Eh Additional maximum current in units of 1 µA with cache retention 23 16 DELTA_RFMEM_RET R 3Bh Additional maximum current in 1 µA units with RF memory retention 15 8 DELTA_XOSC_LPM R 90h Additional maximum current in units of 1 µA with XOSC_HF on in low power mode 7 0 BASELINE R 21h Worst case ...

Page 797: ...9 100 PWD_CURR_95C Register Field Descriptions Bit Field Type Reset Description 31 24 DELTA_CACHE_REF R 4Ch Additional maximum current in units of 1 µA with cache retention 23 16 DELTA_RFMEM_RET R 62h Additional maximum current in 1 µA units with RF memory retention 15 8 DELTA_XOSC_LPM R 7Ah Additional maximum current in units of 1 µA with XOSC_HF on in low power mode 7 0 BASELINE R 3Bh Worst case...

Page 798: ... 9 101 PWD_CURR_110C Register Field Descriptions Bit Field Type Reset Description 31 24 DELTA_CACHE_REF R 78h Additional maximum current in units of 1 µA with cache retention 23 16 DELTA_RFMEM_RET R 9Eh Additional maximum current in 1 µA units with RF memory retention 15 8 DELTA_XOSC_LPM R 70h Additional maximum current in units of 1 µA with XOSC_HF on in low power mode 7 0 BASELINE R 6Bh Worst ca...

Page 799: ...e 9 102 PWD_CURR_125C Register Field Descriptions Bit Field Type Reset Description 31 24 DELTA_CACHE_REF R ADh Additional maximum current in units of 1 µA with cache retention 23 16 DELTA_RFMEM_RET R E1h Additional maximum current in 1 µA units with RF memory retention 15 8 DELTA_XOSC_LPM R 80h Additional maximum current in units of 1 µA with XOSC_HF on in low power mode 7 0 BASELINE R 9Ah Worst c...

Page 800: ...with 128 bit key support local key storage and DMA capability This chapter provides the description and information for configuring the AES engine Topic Page 10 1 AES Cryptoprocessor Overview 802 10 2 Cryptography Registers 829 800 Cryptography SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 801: ...nd to write it to the AES key registers The AES engine automatically pads or masks misaligned last data blocks with zeroes for AES CBC MAC and CCM including misaligned AAD data For AES CTR mode misaligned last data blocks are internally masked to support nonblock size input data 10 1 1 Functional Description The AES engine is directly connected to the context and data registers so that it can imme...

Page 802: ...16 and 32 bit transfers However the AES module accepts only 32 bit single access As each transfer is checked for multiple error conditions depending on the address size and type of the transfer these checks are performed on registered signals to improve timing on the input signals Therefore one wait cycle must be inserted for each transfer If an ERROR response occurs h_ready_out must be taken low ...

Page 803: ... be used for debugging only The IRQSTAT register provides the status of the two interrupts along with error status messages The error status bits are asserted once they are detected and typically the value of DMA_BUS_ERR and KEY_ST_WR_ERR signals are valid after the RESULT_AVAIL bit is asserted The KEY_ST_RD_ERR bit is valid after triggering the key store module to read a key from memory and provi...

Page 804: ...51C AESKEY3__0 to Section 10 2 1 17 AESKEY3__3 register 0x4002 4540 to AESIV_0 to AESIV_3 R W 0x0000 0000 AES IV LSW Section 10 2 1 18 0x4002 454C 0x4002 4550 AESCTL R W 0x8000 0000 I O and control mode Section 10 2 1 19 0x4002 4554 AESDATALEN0 W 0x0000 0000 Crypto data length Section 10 2 1 20 LSW 0x4002 4558 AESDATALEN1 W 0x0000 0000 Crypto data length Section 10 2 1 21 MSW 0x4002 455C AESAUTHLE...

Page 805: ...2 4784 IRQEN R W 0x0000 0000 Interrupt enabling Section 10 2 1 36 register 0x4002 4788 IRQCLR W 0x0000 0000 Interrupt clear Section 10 2 1 37 register 0x4002 478C IRQSET W 0x0000 0000 Interrupt set register Section 10 2 1 38 0x4002 4790 IRQSTAT R 0x0000 0000 Interrupt status Section 10 2 1 39 register 0x4002 47F8 HWOPT R 0x0201 0093 Type and options register 0x4002 47FC HWVER R 0x9110 8778 Version...

Page 806: ...nal memory Access to the channels of the AHB master port is handled by the arbiter module Channel control registers are used for channel enabling and priority selection When a channel is disabled it becomes inactive only when all ongoing requests are finished NOTE All the channel control registers DMACHxCTL DMACHxEXTADDR and DMACHxLEN must be programmed by the host to start a new DMA operation The...

Page 807: ...key store module immediately accepts all data without delay cycles while the crypto modules operate on a data block boundary On the TCM side the key store module immediately accepts all data without delay cycles while the crypto module operates on a data block boundary the processing of which takes a number of clock cycles Special handshake signals are used between the DMAC and crypto modules A da...

Page 808: ...A encryption and decryption or AES 0 1 0 data is loaded through the DMA and result tag is read through the slave interface authentication only operations AES data is loaded through the DMA result tag is read through the DMA authentication only 0 1 1 operations 10 1 4 4 2 Master PROT Enable 10 1 4 4 2 1 Master PROT Privileged Access Enable The DMAPORTCTL register selects the AHB transfer protection...

Page 809: ...receives the proper round key from the AES key scheduler A fundamental component of the AES algorithm is the S box The S box provides a unique 8 bit output for each 8 bit input The architecture of the AES decryption core is generally the same as the architecture of the encryption core One difference is that the generation of round keys for decryption requires an initial conversion of the input key...

Page 810: ...27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AESKEY3__0 AESKEY3__3 31 0 AESKEY2__0 AESKEY2__3 159 128 AESKEY3__0 AESKEY3__3 63 32 AESKEY2__0 AESKEY2__3 191 160 AESKEY3__0 AESKEY3__3 95 64 AESKEY2__0 AESKEY2__3 223 192 AESKEY3__0 AESKEY3__3 127 96 AESKEY2__0 AESKEY2__3 255 224 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 For CCM Bit Field Name Functio...

Page 811: ...ector used for CBC MAC Bit Name Description 127 0 Zeroes For CBC MAC this register must be written with zeroes at the start of each operation After an operation these registers contain the 128 bit TAG output generated by the crypto core 10 1 4 5 3 AES I O Buffer Control Mode and Length Registers The I O buffer and mode control register AESCTL specifies the mode of operation for the AES engine NOTE...

Page 812: ...UT_RDY register bit For a host read operation this register contains the 128 bit output block from the latest AES operation Reading from a word aligned offset within this address range reads one word 4 bytes of data out of the 4 word deep 16 bytes 128 bits AES block data output buffer The words four words one full block must be read before the core moves the next block to the data output buffer To...

Page 813: ...e local key storage module is directly connected to 1 KB memory The module can store up to eight AES keys and has eight 128 bit entries The key size is programmed in the key store module The key material in the key store is not accessible through read operations through the AHB master and slave interfaces Keys can only be written to the key store through DMA Once a DMA operation for a key read is ...

Page 814: ... and initialization of the engines DMA and so forth 2 Data processing for the complete message 3 Finalization reading out the result status checking The orange sections full processing of Figure 10 2 are covered by Step 1 and Step 3 Step 1 and Step 3 are under control of the host CPU and therefore dependent on the performance of the host Step 2 is covered by the green section data processing and i...

Page 815: ...e performance in this case the configuration overhead is the most significant assuming the engine is fully reconfigured for each operation Therefore processing multiple blocks per operation results in a significantly higher performance 10 1 6 Programming Guidelines This section describes the low level programming sequences for configuring and using the AES module for the supported use cases 10 1 6...

Page 816: ...Offset 788h reset X Master control module algorithm selection register must be cleared to zero to switch off the DMA AHB Master clock see Section 10 2 1 32 ALGSEL Register Offset 700h reset X NOTE The IRQSTAT register must be checked for possible errors if bus errors can occur in the system which is typically valid in a debugging phase or in systems where bus errors can occur during a DMA operatio...

Page 817: ...sing a time out or other synchronization mechanisms that external memory reads are only performed after all memory write operations are finished 10 1 6 3 Encryption and Decryption The crypto engine AES transfers data over the following interfaces AES accepts input data from two sources AHB slave interface and DMA Within one operation it is possible to combine data from these two sources write data...

Page 818: ...hannel 0 write DMACH0EXTADDR ext_memory_address base address of the key in ext memory write DMACH0LEN length total key length in bytes e g 16 for 1 x 128 bit key wait for completion wait IRQSTAT 0 1 wait for operation completed check IRQSTAT 31 30 00 check for absence of errors in DMA and key store write IRQCLR 0x0000_0001 acknowledge the interrupt write ALGSEL 0x0000_0000 disable master control D...

Page 819: ...number of bytes 10 1 6 3 2 3 AES CTR For AES CTR operations the following configuration parameters are required Key from the key store module IV from the slave interface including initial counter value usually 0x0000 0001 Control register settings mode direction key size Length of the data may be nonblock size aligned The length field can have any value If a data stream is finished and the next da...

Page 820: ..._0 write AESIV_3 endif configure AES engine write AESCTL 0b0010_0000_0000_0000_ 0000_0000_0010_1100 program AES CBC 128 encryption and save IV write AESDATALEN0 write length of the message lo write AESDATALEN1 write length of the message hi write DMACH0CTL 0x0000_00001 enable DMA channel 0 configure DMAC write DMACH0EXTADDR address base address of the input data in ext memory write DMACH0LEN lengt...

Page 821: ...n end misaligned for CBC MAC operations If this is the case the crypto core internally pads the last input data block The length field can have any value If a data stream is finished and the next data stream uses the same key and control writing only a part of the next context is not allowed A new data stream must always write the complete context The length field must never be written with zeroes...

Page 822: ...tialization vector write AESIV_0 write AESIV_3 configure the AES engine write AESCTL 0b0010_0000_0000_0000_ 1000_0000_0100_1100 program AES CBC MAC 128 authentication write AESDATALEN0 write length of the crypto block lo write AESDATALEN1 write the length of the crypto block hi may be non block size aligned write DMACH0CTL 0x0000_00001 enable DMA channel 0 configure DMAC write DMACH0EXTADDR addres...

Page 823: ...en with a new value The user cannot write both length fields with zeroes The result TAG is typically read using the slave interface but can also be written to an external memory location using a separate DMA operation 10 1 6 3 4 1 Programming Sequence The following software example in pseudocode describes the actions that are typically executed by the host software to encrypt and authenticate a me...

Page 824: ...dress base address of the payload data in ext memory write DMACH0LEN length payload data length in bytes equal to the message length len crypto_data write DMACH1CTL 0x0000_00001 enable DMA channel 1 write DMACH1EXTADDR address base address of the output data buffer write DMACH1LEN length output data length in bytes equal to the result data length len crypto data wait for completion wait IRQSTAT 0 ...

Page 825: ...The recovery procedure is as follows Issue a soft reset to the DMAC using the DMASWRESET register to clear the DMAPORTERR register and initialize the channels to their default state Issue a soft reset to the master control module to clear its intermediate state 10 1 6 4 3 Key Store Errors Key store error generation is implemented for debugging purposes In normal or specified operation the crypto c...

Page 826: ...abyte Gbit Gigabit Gbps Gigabits per second HMAC Hashed MAC HW Hardware ICM Integer Counter Mode IETF Internet Engineering Task Force IP Internet Protocol or Intellectual Property IV Initialization Vector KB Kilobyte kbit Kilobit kbps Kilobits per second LSB Least Significant Bit LSW Least Significant Word MAC Message Authentication Code MB Megabyte Mbit Megabit Mbps Megabits per second ME Mobile ...

Page 827: ...s document contains formulas and nomenclature for different data types The presentation of syntax is given as follows 0x00 or 0h Hexadecimal value 0b Binary value 0d Decimal value 0 Digital logic 0 or LOW 1 Digital logic 1 or HIGH bit Binary digit 8 bits 1 byte 16 bits Half word 32 bits Word 64 bits Dual word 128 bits Quad word MOD Modulo REM Remainder A B A Logical AND B A OR B A Logical OR B NOR...

Page 828: ... 51Ch AESKEY3_0 to AESKEY3_3 Clear AES_KEY3 Section 10 2 1 17 540h to 54Ch AESIV_0 to AESIV_3 AES Initialization Vector Section 10 2 1 18 550h AESCTL AES Input Output Buffer Control Section 10 2 1 19 554h AESDATALEN0 Crypto Data Length LSW Section 10 2 1 20 558h AESDATALEN1 Crypto Data Length MSW Section 10 2 1 21 55Ch AESAUTHLEN AES Authentication Length Section 10 2 1 22 560h AESDATAOUT0 Data In...

Page 829: ... 2 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 1 PRIO R W 0h Channel priority A channel with high priority will be served before a channel with low priority in cases with simultaneous access requests If both channels have the same priority access of the channels to the external port is arbitrated us...

Page 830: ...8 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR R W 0h Table 10 12 DMACH0EXTADDR Register Field Descriptions Bit Field Type Reset Description 31 0 ADDR R W 0h Channel external address value Holds the last updated external address after being sent to the master interface 830 SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 T...

Page 831: ...oftware must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 15 0 LEN R W 0h DMA transfer length in bytes During configuration this register contains the DMA transfer length in bytes During operation it contains the last updated value of the DMA transfer length after being sent to the master interface Note Writing a nonzero value to...

Page 832: ...ERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 17 PORT_ERR R 0h Reflects possible transfer errors on the AHB port 16 2 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 1 CH1_ACTIVE R 0h This register field indicates...

Page 833: ...ESET W 0h W0C 0h Table 10 15 DMASWRESET Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 RESET W0C 0h Software reset enable 0 Disable 1 Enable self cleared to zero Note Completion of the software reset must be checked in DMASTAT CH0_ACTIVE...

Page 834: ...iting any other value than the reset value may result in undefined behavior 1 PRIO R W 0h Channel priority A channel with high priority will be served before a channel with low priority in cases with simultaneous access requests If both channels have the same priority access of the channels to the external port is arbitrated using a Round Robin scheme 0h Priority low 1h Priority high 0 EN R W 0h C...

Page 835: ...28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR R W 0h Table 10 17 DMACH1EXTADDR Register Field Descriptions Bit Field Type Reset Description 31 0 ADDR R W 0h Channel external address value Holds the last updated external address after being sent to the master interface 835 SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 ...

Page 836: ... Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 15 0 LEN R W 0h DMA transfer length in bytes During configuration this register contains the DMA transfer length in bytes During operation it contains the last updated value of the DMA transfer length after being sent to the master interface Note Writing a nonzero value ...

Page 837: ...T_SIZ R W 2h Maximum burst size that can be performed on the AHB bus E 2h 4_BYTE 4 bytes 3h 8_BYTE 8 bytes 4h 16_BYTE 16 bytes 5h 32_BYTE 32 bytes 6h 64_BYTE 64 bytes 11 AHB_MST1_IDLE_EN R W 0h Idle transfer insertion between consecutive burst transfers on AHB 0h Do not insert idle transfers 1h Idle transfer insertion enabled 10 AHB_MST1_INCR_EN R W 1h Burst length type of AHB transfer 0h Unspecif...

Page 838: ...not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 12 AHB_ERR R 0h A 1 indicates that the Crypto peripheral has detected an AHB bus error 11 10 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 9 LAST_CH R 0h Indicates which channel was serviced...

Page 839: ...21 DMAHWVER Register Field Descriptions Bit Field Type Reset Description 31 28 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 27 24 HW_MAJOR_VER R 1h Major version number 23 20 HW_MINOR_VER R 0h Minor version number 19 16 HW_PATCH_LVL R 1h Patch level 15 8 VER_NUM_COMPL R 2Eh Bit by bit complement of the...

Page 840: ...a or areas where the key or keys need to be written Writing to multiple RAM locations is only possible when the selected RAM areas are sequential 0h This RAM area is not selected to be written 1h This RAM area is selected to be written 5 RAM_AREA5 R W 0h Represents an area of 128 bits Select the key store RAM area or areas where the key or keys need to be written Writing to multiple RAM locations ...

Page 841: ...ct the key store RAM area or areas where the key or keys need to be written Writing to multiple RAM locations is only possible when the selected RAM areas are sequential 0h This RAM area is not selected to be written 1h This RAM area is selected to be written 0 RAM_AREA0 R W 0h Represents an area of 128 bits Select the key store RAM area or areas where the key or keys need to be written Writing to...

Page 842: ...is register will be reset on a soft reset initiated by writing to DMASWRESET RESET After a soft reset all keys must be rewritten to the key store memory 0h This RAM area is not written with valid key information 1h This RAM area is written with valid key information 6 RAM_AREA_WRITTEN6 R W1C 0h On read this bit returns the key area written status This bit can be reset by writing a 1 Note This regi...

Page 843: ...M area is not written with valid key information 1h This RAM area is written with valid key information 1 RAM_AREA_WRITTEN1 R W1C 0h On read this bit returns the key area written status This bit can be reset by writing a 1 Note This register will be reset on a soft reset initiated by writing to DMASWRESET RESET After a soft reset all keys must be rewritten to the key store memory 0h This RAM area ...

Page 844: ...scriptions Bit Field Type Reset Description 31 2 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 1 0 SIZE R W 1h Key size When writing to this register KEYWRITTENAREA will be reset Note For the Crypto peripheral this field is fixed to 128 bits For software compatibility KEYWRITTENAREA will be reset when...

Page 845: ...sy status flag read only 0 Operation is completed 1 Operation is not completed and the key store is busy 30 4 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 3 0 RAM_AREA R W 8h Selects the area of the key store RAM from where the key needs to be read that will be written to the AES engine Only RAM area...

Page 846: ... 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 KEY2 W 0h Table 10 26 AESKEY2_0 to AESKEY2_3 Register Field Descriptions Bit Field Type Reset Description 31 0 KEY2 W 0h AESKEY2 bits 31 x 0 x or AES_GHASH_H bits 31 x 0 x where x 0 32 64 96 ordered from the LSW entry of this 4 deep register array The interpretation of this field depends on the crypto operation mode 846 SWCU117C February 2015 Revised...

Page 847: ...7 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 KEY3 W 0h Table 10 27 AESKEY3_0 to AESKEY3_3 Register Field Descriptions Bit Field Type Reset Description 31 0 KEY3 W 0h AESKEY3 bits 31 x 0 x or AESKEY2 bits 159 x 128 x where x 0 32 64 96 ordered from the LSW entry of this 4 deep register arrary The interpretation of this field depends on the crypto operation mode 847 SWCU117C February 2015 Revised Sept...

Page 848: ...0 to AESIV_3 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IV R W 0h Table 10 28 AESIV_0 to AESIV_3 Register Field Descriptions Bit Field Type Reset Description 31 0 IV R W 0h The interpretation of this field depends on the crypto operation mode 848 SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Texas Inst...

Page 849: ...ONTEXT_RDY Writing 1 clears the bit to zero indicating the Crypto peripheral can start its next operation This bit is also cleared when the fourth word of the output TAG and or IV is read Note All other mode bit writes will be ignored when this mode bit is written with 1 Note This bit is controlled automatically by the Crypto peripheral for TAG read DMA operations For typical use this bit does NOT...

Page 850: ... module 00 N A reserved 01 128 bits 10 N A reserved 11 N A reserved For the Crypto peripheral this field is fixed to 128 bits 2 DIR R W 0h Direction 0 Decrypt operation is performed 1 Encrypt operation is performed This bit must be written with a 1 when CBC MAC is selected 1 INPUT_RDY R W 0h If read as 1 this status bit indicates that the 16 byte AES input buffer is empty The Host is permitted to ...

Page 851: ... 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LEN_LSW W 0h Table 10 30 AESDATALEN0 Register Field Descriptions Bit Field Type Reset Description 31 0 LEN_LSW W 0h Used to write the Length values to the Crypto peripheral This register contains bits 31 0 of the combined data length 851 SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Te...

Page 852: ...For GCM any value up to 236 32 bytes can be used This is because a 32 bit counter mode is used the maximum number of 128 bit blocks is 232 2 resulting in a maximum number of bytes of 236 32 Writing to this register triggers the engine to start using this context This is valid for all modes except GCM and CCM Note For the combined modes GCM and CCM this length does not include the authentication on...

Page 853: ... 0h Table 10 32 AESAUTHLEN Register Field Descriptions Bit Field Type Reset Description 31 0 LEN W 0h Authentication data length in bytes for combined mode CCM only Supported AAD lengths for CCM are from 0 to 216 28 bytes Once processing with this context is started this length decrements to zero Writing this register triggers the engine to start using this context for CCM 853 SWCU117C February 20...

Page 854: ...ES engine through DMA For a Host read operation these registers contain the 128 bit output block from the latest AES operation Reading from a word aligned offset within this address range will read one word 4 bytes of data out the 4 word deep 16 bytes 128 bits AES block data output buffer The words 4 words one full block must be read before the core will move the next block to the data output buff...

Page 855: ...ge will store the word 4 bytes of data into the corresponding position of 4 word deep 16 bytes 128 bit AES block data input buffer This buffer is used for the next AES operation If the last data block is not completely filled with valid data see notes below it is allowed to write only the words with valid data Next AES operation is triggered by writing to AESCTL INPUT_RDY Note AES typically operat...

Page 856: ...he AES engine through DMA For a Host read operation these registers contain the 128 bit output block from the latest AES operation Reading from a word aligned offset within this address range will read one word 4 bytes of data out the 4 word deep 16 bytes 128 bits AES block data output buffer The words 4 words one full block must be read before the core will move the next block to the data output ...

Page 857: ...ge will store the word 4 bytes of data into the corresponding position of 4 word deep 16 bytes 128 bit AES block data input buffer This buffer is used for the next AES operation If the last data block is not completely filled with valid data see notes below it is allowed to write only the words with valid data Next AES operation is triggered by writing to AESCTL INPUT_RDY Note AES typically operat...

Page 858: ...he AES engine through DMA For a Host read operation these registers contain the 128 bit output block from the latest AES operation Reading from a word aligned offset within this address range will read one word 4 bytes of data out the 4 word deep 16 bytes 128 bits AES block data output buffer The words 4 words one full block must be read before the core will move the next block to the data output ...

Page 859: ...ge will store the word 4 bytes of data into the corresponding position of 4 word deep 16 bytes 128 bit AES block data input buffer This buffer is used for the next AES operation If the last data block is not completely filled with valid data see notes below it is allowed to write only the words with valid data Next AES operation is triggered by writing to AESCTL INPUT_RDY Note AES typically operat...

Page 860: ...the AES engine through DMA For a Host read operation these registers contain the 128 bit output block from the latest AES operation Reading from a word aligned offset within this address range will read one word 4 bytes of data out the 4 word deep 16 bytes 128 bits AES block data output buffer The words 4 words one full block must be read before the core will move the next block to the data output...

Page 861: ... will store the word 4 bytes of data into the corresponding position of 4 word deep 16 bytes 128 bit AES block data input buffer This buffer is used for the next AES operation If the last data block is not completely filled with valid data see notes below it is allowed to write only the words with valid data Next AES operation is triggered by writing to AESCTL INPUT_RDY Note AES typically operates...

Page 862: ...UT_3 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TAG R 0h Table 10 41 AESTAGOUT_0 to AESTAGOUT_3 Register Field Descriptions Bit Field Type Reset Description 31 0 TAG R 0h This register contains the authentication TAG for the combined and authentication only modes 862 SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copy...

Page 863: ... 0h If this bit is cleared to 0 the DMA operation involves only data If this bit is set the DMA operation includes a TAG Authentication Result Digest 30 2 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 1 AES R W 0h If set to 1 the AES data is loaded through DMA Both Read and Write maximum transfer size...

Page 864: ...Table 10 43 DMAPROTCTL Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 EN R W 0h Select AHB transfer protection control for DMA transfers using the key store area as destination 0 Transfers use USER type access 1 Transfers use PRIVILEGE...

Page 865: ...re must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 RESET R W1C 0h If this bit is set to 1 the following modules are reset Master control internal state is reset That includes interrupt error status register and result available interrupt generation FSM Key store module state is reset That includes clearing the Written Area fl...

Page 866: ... Table 10 45 IRQTYPE Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 IEN R W 0h Interrupt enable This bit must be set to 1 to enable interrupts from the Crypto peripheral 0 All interrupts are disabled enabled 1 All interrupts are enable...

Page 867: ...SULT_AVAI E L R W 0h R W 0h R W 0h Table 10 46 IRQEN Register Field Descriptions Bit Field Type Reset Description 31 2 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 1 DMA_IN_DONE R W 0h This bit enables IRQSTAT DMA_IN_DONE as source for IRQ 0 RESULT_AVAIL R W 0h This bit enables IRQSTAT RESULT_AVAIL a...

Page 868: ...et Description 31 DMA_BUS_ERR W 0h If 1 is written to this bit IRQSTAT DMA_BUS_ERR is cleared 30 KEY_ST_WR_ERR W 0h If 1 is written to this bit IRQSTAT KEY_ST_WR_ERR is cleared 29 KEY_ST_RD_ERR W 0h If 1 is written to this bit IRQSTAT KEY_ST_RD_ERR is cleared 28 2 RESERVED W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined be...

Page 869: ...0h W 0h Table 10 48 IRQSET Register Field Descriptions Bit Field Type Reset Description 31 2 RESERVED W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 1 DMA_IN_DONE W 0h If 1 is written to this bit IRQSTAT DMA_IN_DONE is set Writing 0 has no effect 0 RESULT_AVAIL W 0h If 1 is written to this bit IRQSTAT RESULT_AVAI...

Page 870: ...g the DMA write operation to the key store memory The value of this register is held until it is cleared through IRQCLR KEY_ST_WR_ERR Note This error is asserted if a DMA operation does not cover a full key area or more areas are written than expected Note This is not an interrupt source 29 KEY_ST_RD_ERR R 0h This bit will be set when a read error is detected during the read of a key from the key ...

Page 871: ...must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 27 24 HW_MAJOR_VER R 1h Major version number 23 20 HW_MINOR_VER R 1h Minor version number 19 16 HW_PATCH_LVL R 1h Patch level starts at 0 at first delivery of this version 15 8 VER_NUM_COMPL R 87h These bits simply contain the complement of VER_NUM 0x87 used by a driver to ascerta...

Page 872: ...vice series has up to 31 I O pins configurable as GPIO or to a peripheral function Topic Page 11 1 Introduction 874 11 2 IOC Overview 874 11 3 I O Mapping and Configuration 875 11 4 Edge Detection on Pin DIO 876 11 5 AON IOC State Latching When Powering Off the MCU Domain 876 11 6 Unused I O Pins 877 11 7 GPIO 877 11 8 I O Pin Mapping 878 11 9 Peripheral PORTIDs 879 11 10 I O Pin 879 11 11 I O Con...

Page 873: ...etween DIO and pin for the different packages Eight of these DIOs also have analog capabilities 11 2 IOC Overview Figure 11 1 shows a general overview The IOC module consists of two main submodules Microcontroller unit IOC MCU IOC configures the peripheral ports to the user defined pins Always on IOC AON IOC module handles SPI S JTAG 32 kHz clock AON Peripheral and AUX signals The always on periph...

Page 874: ...le AUXIO1 is mapped to DIO29 on the 7 7 package type and set up as a digital input The pin number and DIO number differs for different package types The module must be powered and the clock to the specific module within the AUX domain must be enabled AIODIO1 for AUXIO0 to AUXIO7 1 Set the IOC IOCFG29 PORTID bit field to 0x08 AUX_I O to route AUXIO1 to DIO29 2 The I O signals in the AUX domain have...

Page 875: ...onfigured through the IOC IOCFGn EDGE_IRQ_EN and EDGE_DET bit fields The DIO must be configured as a GPIO input A GPIO edge detect event is sent to the CPU interrupt IRQ0 vector number 16 This interrupt must be enabled to call the GPIO interrupt handler In this interrupt handler the event source must be cleared by clearing the relevant GPIO EVFLAGS31 event register DIOn bit Reading this register r...

Page 876: ...he IOC module To modify a single GPIO output value use the GPIO DOUTn registers see Section 11 11 2 GPIO Registers To set up DIO1 as a GPIO output and toggle the bit use the following procedure 1 Map DIO1 as a GPIO output by setting the IOC IOCFG1 PORT_ID register to 0 GPIO PORDTID 2 Ensure DIO1 is set as output by clearing the IOC IOCFG1 IE bit More port configurations can also be set in the IOC ...

Page 877: ...mA 36 23 20 7 22 5 yes 7 2 mA 4 mA 32 22 2 mA 4 mA 31 21 2 mA 4 mA 30 20 2 mA 4 mA 29 19 2 mA 4 mA 28 18 2 mA 4 mA 27 17 16 6 16 4 2 mA 4 mA 8 mA TDI 26 16 15 5 15 3 2 mA 4 mA 8 mA TDO 25 14 14 TCKC 24 13 13 TMSC 21 15 2 mA 4 mA 20 14 2 mA 4 mA 19 13 2 mA 4 mA 18 12 2 mA 4 mA 17 11 2 mA 4 mA 16 10 2 mA 4 mA 15 9 2 mA 4 mA 14 8 2 mA 4 mA 12 7 10 4 10 2 8 2 mA 4 mA 8 mA 11 6 9 3 9 1 9 2 mA 4 mA 8 mA...

Page 878: ...RT 0 Rx pin 41 MCU_I2S_MCLK I2S MCLK pin 16 MCU_UART0_TX UART 0 Tx pin 42 45 Reserved 17 MCU_UART0_CTS UART 0 CTS pin 46 RF Core internal signal 18 MCU_UART0_RTS UART 0 RTS pin 47 RFC_GPO0 19 22 Reserved 48 RFC_GPO1 23 MCU_GPTM_GPTM0 GMTM timer pin GPTM0 49 RFC_GPO2 24 MCU_GPTM_GPTM1 GMTM timer pin GPTM2 50 RFC_GPO3 25 MCU_GPTM_GPTM2 GMTM timer pin GPTM3 51 56 RF Core internal signals 26 MCU_GPTM_...

Page 879: ...L Configures a weak pull on an I O pin The following can be set pullup pulldown or no pull See the data sheet for specific pullup and pulldown resistance Slew Control IOC IOCFGn SLEW_RED Sets high or low slew rate on an I O pin Hysteresis IOC IOCFGn HYST_EN Enables or disables input hysteresis on an I O pin Open Source or Open Drain Configuration IOC IOCFGn IOMODE Configures the pin as normal open...

Page 880: ...ified Table 11 4 AON_IOC Registers Offset Acronym Register Name Section 0h IOSTRMIN IO Drive Strength Minimum Section 11 11 1 1 4h IOSTRMED IO Drive Strength Medium Section 11 11 1 2 8h IOSTRMAX IO Drive Strength Maximum Section 11 11 1 3 Ch IOCLATCH IO Latch Control Section 11 11 1 4 10h CLK32KCTL SCLK_LF External Output Control Section 11 11 1 5 880 I O Control SWCU117C February 2015 Revised Sep...

Page 881: ...20 19 18 17 16 RESERVED R 0h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED GRAY_CODE R 0h R W 3h Table 11 5 IOSTRMIN Register Field Descriptions Bit Field Type Reset Description 31 3 RESERVED R 0h Internal Only to be used through TI provided API 2 0 GRAY_CODE R W 3h Internal Only to be used through TI provided API 881 SWCU117C February 2015 Revised September 2015 I O Control Submit Documentation ...

Page 882: ...20 19 18 17 16 RESERVED R 0h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED GRAY_CODE R 0h R W 6h Table 11 6 IOSTRMED Register Field Descriptions Bit Field Type Reset Description 31 3 RESERVED R 0h Internal Only to be used through TI provided API 2 0 GRAY_CODE R W 6h Internal Only to be used through TI provided API 882 I O Control SWCU117C February 2015 Revised September 2015 Submit Documentation ...

Page 883: ...20 19 18 17 16 RESERVED R 0h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED GRAY_CODE R 0h R W 5h Table 11 7 IOSTRMAX Register Field Descriptions Bit Field Type Reset Description 31 3 RESERVED R 0h Internal Only to be used through TI provided API 2 0 GRAY_CODE R W 5h Internal Only to be used through TI provided API 883 SWCU117C February 2015 Revised September 2015 I O Control Submit Documentation ...

Page 884: ...ely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 EN R W 1h Controls latches between MCU IOC and AON_IOC The latches are transparent by default They must be closed prior to power off the domain s controlling the IOs in order to preserve IO values on external pins 0h Latches are static meaning the current value on the IO pin is frozen by ...

Page 885: ...ESERVED OE_N R 0h R W 1h Table 11 9 CLK32KCTL Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 OE_N R W 1h 0 Output enable active SCLK_LF output on IO pin that has PORT_ID e g IOC IOCFG0 PORT_ID set to AON_CLK32K 1 Output enable not active...

Page 886: ... Data Out 16 to 19 Section 11 11 2 5 14h DOUT23_20 Data Out 20 to 23 Section 11 11 2 6 18h DOUT27_24 Data Out 24 to 27 Section 11 11 2 7 1Ch DOUT31_28 Data Out 28 to 31 Section 11 11 2 8 80h DOUT31_0 Data Output for DIO 0 to 31 Section 11 11 2 9 90h DOUTSET31_0 Data Out Set Section 11 11 2 10 A0h DOUTCLR31_0 Data Out Clear Section 11 11 2 11 B0h DOUTTGL31_0 Data Out Toggle Section 11 11 2 12 C0h D...

Page 887: ...DOE31_0 bit field is set 23 17 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 16 DIO2 W 0h Sets the state of the pin that is configured as DIO 2 if the corresponding DOE31_0 bit field is set 15 9 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value ...

Page 888: ...DOE31_0 bit field is set 23 17 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 16 DIO6 W 0h Sets the state of the pin that is configured as DIO 6 if the corresponding DOE31_0 bit field is set 15 9 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value ...

Page 889: ...ding DOE31_0 bit field is set 23 17 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 16 DIO10 W 0h Sets the state of the pin that is configured as DIO 10 if the corresponding DOE31_0 bit field is set 15 9 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset...

Page 890: ...nding DOE31_0 bit field is set 23 17 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 16 DIO14 W 0h Sets the state of the pin that is configured as DIO 14 if the corresponding DOE31_0 bit field is set 15 9 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the rese...

Page 891: ...onding DOE31_0 bit field is set 23 17 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 16 DIO18 W 0h Sets the state of the pin that is configured as DIO 18 if the corresponding DOE31_0 bit field is set 15 9 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the res...

Page 892: ...onding DOE31_0 bit field is set 23 17 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 16 DIO22 W 0h Sets the state of the pin that is configured as DIO 22 if the corresponding DOE31_0 bit field is set 15 9 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the res...

Page 893: ...onding DOE31_0 bit field is set 23 17 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 16 DIO26 W 0h Sets the state of the pin that is configured as DIO 26 if the corresponding DOE31_0 bit field is set 15 9 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the res...

Page 894: ...onding DOE31_0 bit field is set 23 17 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 16 DIO30 W 0h Sets the state of the pin that is configured as DIO 30 if the corresponding DOE31_0 bit field is set 15 9 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the res...

Page 895: ...tput for DIO 30 29 DIO29 R W 0h Data output for DIO 29 28 DIO28 R W 0h Data output for DIO 28 27 DIO27 R W 0h Data output for DIO 27 26 DIO26 R W 0h Data output for DIO 26 25 DIO25 R W 0h Data output for DIO 25 24 DIO24 R W 0h Data output for DIO 24 23 DIO23 R W 0h Data output for DIO 23 22 DIO22 R W 0h Data output for DIO 22 21 DIO21 R W 0h Data output for DIO 21 20 DIO20 R W 0h Data output for D...

Page 896: ...IO 6 5 DIO5 R W 0h Data output for DIO 5 4 DIO4 R W 0h Data output for DIO 4 3 DIO3 R W 0h Data output for DIO 3 2 DIO2 R W 0h Data output for DIO 2 1 DIO1 R W 0h Data output for DIO 1 0 DIO0 R W 0h Data output for DIO 0 896 I O Control SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 897: ...S 0h W1S 0h W1S 0h W1S 0h W1S 0h W1S 0h W1S 0h W1S 0h Table 11 20 DOUTSET31_0 Register Field Descriptions Bit Field Type Reset Description 31 DIO31 W1S 0h Set bit 31 30 DIO30 W1S 0h Set bit 30 29 DIO29 W1S 0h Set bit 29 28 DIO28 W1S 0h Set bit 28 27 DIO27 W1S 0h Set bit 27 26 DIO26 W1S 0h Set bit 26 25 DIO25 W1S 0h Set bit 25 24 DIO24 W1S 0h Set bit 24 23 DIO23 W1S 0h Set bit 23 22 DIO22 W1S 0h Se...

Page 898: ...7 DIO7 W1S 0h Set bit 7 6 DIO6 W1S 0h Set bit 6 5 DIO5 W1S 0h Set bit 5 4 DIO4 W1S 0h Set bit 4 3 DIO3 W1S 0h Set bit 3 2 DIO2 W1S 0h Set bit 2 1 DIO1 W1S 0h Set bit 1 0 DIO0 W1S 0h Set bit 0 898 I O Control SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 899: ...1C 0h W1C 0h W1C 0h Table 11 21 DOUTCLR31_0 Register Field Descriptions Bit Field Type Reset Description 31 DIO31 W1C 0h Clears bit 31 30 DIO30 W1C 0h Clears bit 30 29 DIO29 W1C 0h Clears bit 29 28 DIO28 W1C 0h Clears bit 28 27 DIO27 W1C 0h Clears bit 27 26 DIO26 W1C 0h Clears bit 26 25 DIO25 W1C 0h Clears bit 25 24 DIO24 W1C 0h Clears bit 24 23 DIO23 W1C 0h Clears bit 23 22 DIO22 W1C 0h Clears bi...

Page 900: ...h Clears bit 7 6 DIO6 W1C 0h Clears bit 6 5 DIO5 W1C 0h Clears bit 5 4 DIO4 W1C 0h Clears bit 4 3 DIO3 W1C 0h Clears bit 3 2 DIO2 W1C 0h Clears bit 2 1 DIO1 W1C 0h Clears bit 1 0 DIO0 W1C 0h Clears bit 0 900 I O Control SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 901: ...h Table 11 22 DOUTTGL31_0 Register Field Descriptions Bit Field Type Reset Description 31 DIO31 R W 0h Toggles bit 31 30 DIO30 R W 0h Toggles bit 30 29 DIO29 R W 0h Toggles bit 29 28 DIO28 R W 0h Toggles bit 28 27 DIO27 R W 0h Toggles bit 27 26 DIO26 R W 0h Toggles bit 26 25 DIO25 R W 0h Toggles bit 25 24 DIO24 R W 0h Toggles bit 24 23 DIO23 R W 0h Toggles bit 23 22 DIO22 R W 0h Toggles bit 22 21 ...

Page 902: ...ggles bit 7 6 DIO6 R W 0h Toggles bit 6 5 DIO5 R W 0h Toggles bit 5 4 DIO4 R W 0h Toggles bit 4 3 DIO3 R W 0h Toggles bit 3 2 DIO2 R W 0h Toggles bit 2 1 DIO1 R W 0h Toggles bit 1 0 DIO0 R W 0h Toggles bit 0 902 I O Control SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 903: ...30 29 DIO29 R 0h Data input from DIO 29 28 DIO28 R 0h Data input from DIO 28 27 DIO27 R 0h Data input from DIO 27 26 DIO26 R 0h Data input from DIO 26 25 DIO25 R 0h Data input from DIO 25 24 DIO24 R 0h Data input from DIO 24 23 DIO23 R 0h Data input from DIO 23 22 DIO22 R 0h Data input from DIO 22 21 DIO21 R 0h Data input from DIO 21 20 DIO20 R 0h Data input from DIO 20 19 DIO19 R 0h Data input fr...

Page 904: ...om DIO 6 5 DIO5 R 0h Data input from DIO 5 4 DIO4 R 0h Data input from DIO 4 3 DIO3 R 0h Data input from DIO 3 2 DIO2 R 0h Data input from DIO 2 1 DIO1 R 0h Data input from DIO 1 0 DIO0 R 0h Data input from DIO 0 904 I O Control SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 905: ... W 0h Data output enable for DIO 28 27 DIO27 R W 0h Data output enable for DIO 27 26 DIO26 R W 0h Data output enable for DIO 26 25 DIO25 R W 0h Data output enable for DIO 25 24 DIO24 R W 0h Data output enable for DIO 24 23 DIO23 R W 0h Data output enable for DIO 23 22 DIO22 R W 0h Data output enable for DIO 22 21 DIO21 R W 0h Data output enable for DIO 21 20 DIO20 R W 0h Data output enable for DIO...

Page 906: ... Data output enable for DIO 5 4 DIO4 R W 0h Data output enable for DIO 4 3 DIO3 R W 0h Data output enable for DIO 3 2 DIO2 R W 0h Data output enable for DIO 2 1 DIO1 R W 0h Data output enable for DIO 1 0 DIO0 R W 0h Data output enable for DIO 0 906 I O Control SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 907: ...0h 7 6 5 4 3 2 1 0 DIO7 DIO6 DIO5 DIO4 DIO3 DIO2 DIO1 DIO0 R W1C 0h R W1C 0h R W1C 0h R W1C 0h R W1C 0h R W1C 0h R W1C 0h R W1C 0h Table 11 25 EVFLAGS31_0 Register Field Descriptions Bit Field Type Reset Description 31 DIO31 R W1C 0h Event for DIO 31 30 DIO30 R W1C 0h Event for DIO 30 29 DIO29 R W1C 0h Event for DIO 29 28 DIO28 R W1C 0h Event for DIO 28 27 DIO27 R W1C 0h Event for DIO 27 26 DIO26 ...

Page 908: ...7 DIO7 R W1C 0h Event for DIO 7 6 DIO6 R W1C 0h Event for DIO 6 5 DIO5 R W1C 0h Event for DIO 5 4 DIO4 R W1C 0h Event for DIO 4 3 DIO3 R W1C 0h Event for DIO 3 2 DIO2 R W1C 0h Event for DIO 2 1 DIO1 R W1C 0h Event for DIO 1 0 DIO0 R W1C 0h Event for DIO 0 908 I O Control SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 909: ...on 11 11 3 13 34h IOCFG13 Configuration of DIO13 Section 11 11 3 14 38h IOCFG14 Configuration of DIO14 Section 11 11 3 15 3Ch IOCFG15 Configuration of DIO15 Section 11 11 3 16 40h IOCFG16 Configuration of DIO16 Section 11 11 3 17 44h IOCFG17 Configuration of DIO17 Section 11 11 3 18 48h IOCFG18 Configuration of DIO18 Section 11 11 3 19 4Ch IOCFG19 Configuration of DIO19 Section 11 11 3 20 50h IOCF...

Page 910: ... 28 27 WU_CFG R W 0h If DIO is configured GPIO or non AON peripheral signals that is PORT_ID 0x00 or 0x08 00 No wakeup 01 No wakeup 10 Wakes up from shutdown if this pad is going low 11 Wakes up from shutdown if this pad is going high If IO is configured for AON peripheral signals or AUX that is PORT_ID 0x01 0x08 this register only sets wakeup enable or not 00 01 Wakeup disabled 10 11 Wakeup enabl...

Page 911: ... any other value than the reset value may result in undefined behavior 14 13 PULL_CTL R W 3h Pull control 1h DWN Pull down 2h UP Pull up 3h DIS No pull 12 SLEW_RED R W 0h 0 Normal slew rate 1 Enables reduced slew rate in output driver 11 10 IOCURR R W 0h Selects IO current in combination with IOSTR 0h 2MA 2 mA 1h 4MA 4 mA 2h 4_8MA 4 or 8 mA 8 mA if IO is double drive strength 9 8 IOSTR R W 0h Sele...

Page 912: ...and so on 1Ah PORT_EVENT3 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Bh PORT_EVENT4 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Ch PORT...

Page 913: ...K I2S MCLK 2Eh RF Core Trace 2Fh RF Core Data Out 0 30h RF Core Data Out 1 31h RF Core Data Out 2 32h RF Core Data Out 3 33h RF Core Data In 0 34h RF Core Data In 1 35h RF Core SMI Data Link Out 36h RF Core SMI Data Link In 37h RF Core SMI Command Link Out 38h RF Core SMI Command Link In 913 SWCU117C February 2015 Revised September 2015 I O Control Submit Documentation Feedback Copyright 2015 Texa...

Page 914: ...28 27 WU_CFG R W 0h If DIO is configured GPIO or non AON peripheral signals that is PORT_ID 0x00 or 0x08 00 No wake up 01 No wake up 10 Wakes up from shutdown if this pad is going low 11 Wakes up from shutdown if this pad is going high If IO is configured for AON peripheral signals or AUX that is PORT_ID 0x01 0x08 this register only sets wakeup enable or not 00 01 Wakeup disabled 10 11 Wakeup enab...

Page 915: ...g any other value than the reset value may result in undefined behavior 14 13 PULL_CTL R W 3h Pull control 1h DWN Pull down 2h UP Pull up 3h DIS No pull 12 SLEW_RED R W 0h 0 Normal slew rate 1 Enables reduced slew rate in output driver 11 10 IOCURR R W 0h Selects IO current in combination with IOSTR 0h 2MA 2 mA 1h 4MA 4 mA 2h 4_8MA 4 or 8 mA 8 mA if IO is double drive strength 9 8 IOSTR R W 0h Sel...

Page 916: ...and so on 1Ah PORT_EVENT3 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Bh PORT_EVENT4 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Ch PORT...

Page 917: ...K I2S MCLK 2Eh RF Core Trace 2Fh RF Core Data Out 0 30h RF Core Data Out 1 31h RF Core Data Out 2 32h RF Core Data Out 3 33h RF Core Data In 0 34h RF Core Data In 1 35h RF Core SMI Data Link Out 36h RF Core SMI Data Link In 37h RF Core SMI Command Link Out 38h RF Core SMI Command Link In 917 SWCU117C February 2015 Revised September 2015 I O Control Submit Documentation Feedback Copyright 2015 Texa...

Page 918: ... 28 27 WU_CFG R W 0h If DIO is configured GPIO or non AON peripheral signals that is PORT_ID 0x00 or 0x08 00 No wakeup 01 No wakeup 10 Wakes up from shutdown if this pad is going low 11 Wakes up from shutdown if this pad is going high If IO is configured for AON peripheral signals or AUX that is PORT_ID 0x01 0x08 this register only sets wakeup enable or not 00 01 Wakeup disabled 10 11 Wakeup enabl...

Page 919: ... any other value than the reset value may result in undefined behavior 14 13 PULL_CTL R W 3h Pull control 1h DWN Pull down 2h UP Pull up 3h DIS No pull 12 SLEW_RED R W 0h 0 Normal slew rate 1 Enables reduced slew rate in output driver 11 10 IOCURR R W 0h Selects IO current in combination with IOSTR 0h 2MA 2 mA 1h 4MA 4 mA 2h 4_8MA 4 or 8 mA 8 mA if IO is double drive strength 9 8 IOSTR R W 0h Sele...

Page 920: ...and so on 1Ah PORT_EVENT3 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Bh PORT_EVENT4 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Ch PORT...

Page 921: ...K I2S MCLK 2Eh RF Core Trace 2Fh RF Core Data Out 0 30h RF Core Data Out 1 31h RF Core Data Out 2 32h RF Core Data Out 3 33h RF Core Data In 0 34h RF Core Data In 1 35h RF Core SMI Data Link Out 36h RF Core SMI Data Link In 37h RF Core SMI Command Link Out 38h RF Core SMI Command Link In 921 SWCU117C February 2015 Revised September 2015 I O Control Submit Documentation Feedback Copyright 2015 Texa...

Page 922: ... 28 27 WU_CFG R W 0h If DIO is configured GPIO or non AON peripheral signals that is PORT_ID 0x00 or 0x08 00 No wakeup 01 No wakeup 10 Wakes up from shutdown if this pad is going low 11 Wakes up from shutdown if this pad is going high If IO is configured for AON peripheral signals or AUX that is PORT_ID 0x01 0x08 this register only sets wakeup enable or not 00 01 Wakeup disabled 10 11 Wakeup enabl...

Page 923: ... any other value than the reset value may result in undefined behavior 14 13 PULL_CTL R W 3h Pull control 1h DWN Pull down 2h UP Pull up 3h DIS No pull 12 SLEW_RED R W 0h 0 Normal slew rate 1 Enables reduced slew rate in output driver 11 10 IOCURR R W 0h Selects IO current in combination with IOSTR 0h 2MA 2 mA 1h 4MA 4 mA 2h 4_8MA 4 or 8 mA 8 mA if IO is double drive strength 9 8 IOSTR R W 0h Sele...

Page 924: ...and so on 1Ah PORT_EVENT3 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Bh PORT_EVENT4 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Ch PORT...

Page 925: ...K I2S MCLK 2Eh RF Core Trace 2Fh RF Core Data Out 0 30h RF Core Data Out 1 31h RF Core Data Out 2 32h RF Core Data Out 3 33h RF Core Data In 0 34h RF Core Data In 1 35h RF Core SMI Data Link Out 36h RF Core SMI Data Link In 37h RF Core SMI Command Link Out 38h RF Core SMI Command Link In 925 SWCU117C February 2015 Revised September 2015 I O Control Submit Documentation Feedback Copyright 2015 Texa...

Page 926: ... 28 27 WU_CFG R W 0h If DIO is configured GPIO or non AON peripheral signals that is PORT_ID 0x00 or 0x08 00 No wakeup 01 No wakeup 10 Wakes up from shutdown if this pad is going low 11 Wakes up from shutdown if this pad is going high If IO is configured for AON peripheral signals or AUX that is PORT_ID 0x01 0x08 this register only sets wakeup enable or not 00 01 Wakeup disabled 10 11 Wakeup enabl...

Page 927: ... any other value than the reset value may result in undefined behavior 14 13 PULL_CTL R W 3h Pull control 1h DWN Pull down 2h UP Pull up 3h DIS No pull 12 SLEW_RED R W 0h 0 Normal slew rate 1 Enables reduced slew rate in output driver 11 10 IOCURR R W 0h Selects IO current in combination with IOSTR 0h 2MA 2 mA 1h 4MA 4 mA 2h 4_8MA 4 or 8 mA 8 mA if IO is double drive strength 9 8 IOSTR R W 0h Sele...

Page 928: ...and so on 1Ah PORT_EVENT3 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Bh PORT_EVENT4 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Ch PORT...

Page 929: ...K I2S MCLK 2Eh RF Core Trace 2Fh RF Core Data Out 0 30h RF Core Data Out 1 31h RF Core Data Out 2 32h RF Core Data Out 3 33h RF Core Data In 0 34h RF Core Data In 1 35h RF Core SMI Data Link Out 36h RF Core SMI Data Link In 37h RF Core SMI Command Link Out 38h RF Core SMI Command Link In 929 SWCU117C February 2015 Revised September 2015 I O Control Submit Documentation Feedback Copyright 2015 Texa...

Page 930: ... 28 27 WU_CFG R W 0h If DIO is configured GPIO or non AON peripheral signals that is PORT_ID 0x00 or 0x08 00 No wakeup 01 No wakeup 10 Wakes up from shutdown if this pad is going low 11 Wakes up from shutdown if this pad is going high If IO is configured for AON peripheral signals or AUX that is PORT_ID 0x01 0x08 this register only sets wakeup enable or not 00 01 Wakeup disabled 10 11 Wakeup enabl...

Page 931: ... any other value than the reset value may result in undefined behavior 14 13 PULL_CTL R W 3h Pull control 1h DWN Pull down 2h UP Pull up 3h DIS No pull 12 SLEW_RED R W 0h 0 Normal slew rate 1 Enables reduced slew rate in output driver 11 10 IOCURR R W 0h Selects IO current in combination with IOSTR 0h 2MA 2 mA 1h 4MA 4 mA 2h 4_8MA 4 or 8 mA 8 mA if IO is double drive strength 9 8 IOSTR R W 0h Sele...

Page 932: ...and so on 1Ah PORT_EVENT3 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Bh PORT_EVENT4 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Ch PORT...

Page 933: ...K I2S MCLK 2Eh RF Core Trace 2Fh RF Core Data Out 0 30h RF Core Data Out 1 31h RF Core Data Out 2 32h RF Core Data Out 3 33h RF Core Data In 0 34h RF Core Data In 1 35h RF Core SMI Data Link Out 36h RF Core SMI Data Link In 37h RF Core SMI Command Link Out 38h RF Core SMI Command Link In 933 SWCU117C February 2015 Revised September 2015 I O Control Submit Documentation Feedback Copyright 2015 Texa...

Page 934: ... 28 27 WU_CFG R W 0h If DIO is configured GPIO or non AON peripheral signals that is PORT_ID 0x00 or 0x08 00 No wakeup 01 No wakeup 10 Wakes up from shutdown if this pad is going low 11 Wakes up from shutdown if this pad is going high If IO is configured for AON peripheral signals or AUX that is PORT_ID 0x01 0x08 this register only sets wakeup enable or not 00 01 Wakeup disabled 10 11 Wakeup enabl...

Page 935: ... any other value than the reset value may result in undefined behavior 14 13 PULL_CTL R W 3h Pull control 1h DWN Pull down 2h UP Pull up 3h DIS No pull 12 SLEW_RED R W 0h 0 Normal slew rate 1 Enables reduced slew rate in output driver 11 10 IOCURR R W 0h Selects IO current in combination with IOSTR 0h 2MA 2 mA 1h 4MA 4 mA 2h 4_8MA 4 or 8 mA 8 mA if IO is double drive strength 9 8 IOSTR R W 0h Sele...

Page 936: ...and so on 1Ah PORT_EVENT3 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Bh PORT_EVENT4 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Ch PORT...

Page 937: ...K I2S MCLK 2Eh RF Core Trace 2Fh RF Core Data Out 0 30h RF Core Data Out 1 31h RF Core Data Out 2 32h RF Core Data Out 3 33h RF Core Data In 0 34h RF Core Data In 1 35h RF Core SMI Data Link Out 36h RF Core SMI Data Link In 37h RF Core SMI Command Link Out 38h RF Core SMI Command Link In 937 SWCU117C February 2015 Revised September 2015 I O Control Submit Documentation Feedback Copyright 2015 Texa...

Page 938: ... 28 27 WU_CFG R W 0h If DIO is configured GPIO or non AON peripheral signals that is PORT_ID 0x00 or 0x08 00 No wakeup 01 No wakeup 10 Wakes up from shutdown if this pad is going low 11 Wakes up from shutdown if this pad is going high If IO is configured for AON peripheral signals or AUX that is PORT_ID 0x01 0x08 this register only sets wakeup enable or not 00 01 Wakeup disabled 10 11 Wakeup enabl...

Page 939: ... any other value than the reset value may result in undefined behavior 14 13 PULL_CTL R W 3h Pull control 1h DWN Pull down 2h UP Pull up 3h DIS No pull 12 SLEW_RED R W 0h 0 Normal slew rate 1 Enables reduced slew rate in output driver 11 10 IOCURR R W 0h Selects IO current in combination with IOSTR 0h 2MA 2 mA 1h 4MA 4 mA 2h 4_8MA 4 or 8 mA 8 mA if IO is double drive strength 9 8 IOSTR R W 0h Sele...

Page 940: ...and so on 1Ah PORT_EVENT3 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Bh PORT_EVENT4 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Ch PORT...

Page 941: ...K I2S MCLK 2Eh RF Core Trace 2Fh RF Core Data Out 0 30h RF Core Data Out 1 31h RF Core Data Out 2 32h RF Core Data Out 3 33h RF Core Data In 0 34h RF Core Data In 1 35h RF Core SMI Data Link Out 36h RF Core SMI Data Link In 37h RF Core SMI Command Link Out 38h RF Core SMI Command Link In 941 SWCU117C February 2015 Revised September 2015 I O Control Submit Documentation Feedback Copyright 2015 Texa...

Page 942: ... 28 27 WU_CFG R W 0h If DIO is configured GPIO or non AON peripheral signals that is PORT_ID 0x00 or 0x08 00 No wakeup 01 No wakeup 10 Wakes up from shutdown if this pad is going low 11 Wakes up from shutdown if this pad is going high If IO is configured for AON peripheral signals or AUX that is PORT_ID 0x01 0x08 this register only sets wakeup enable or not 00 01 Wakeup disabled 10 11 Wakeup enabl...

Page 943: ... any other value than the reset value may result in undefined behavior 14 13 PULL_CTL R W 3h Pull control 1h DWN Pull down 2h UP Pull up 3h DIS No pull 12 SLEW_RED R W 0h 0 Normal slew rate 1 Enables reduced slew rate in output driver 11 10 IOCURR R W 0h Selects IO current in combination with IOSTR 0h 2MA 2 mA 1h 4MA 4 mA 2h 4_8MA 4 or 8 mA 8 mA if IO is double drive strength 9 8 IOSTR R W 0h Sele...

Page 944: ...and so on 1Ah PORT_EVENT3 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Bh PORT_EVENT4 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Ch PORT...

Page 945: ...K I2S MCLK 2Eh RF Core Trace 2Fh RF Core Data Out 0 30h RF Core Data Out 1 31h RF Core Data Out 2 32h RF Core Data Out 3 33h RF Core Data In 0 34h RF Core Data In 1 35h RF Core SMI Data Link Out 36h RF Core SMI Data Link In 37h RF Core SMI Command Link Out 38h RF Core SMI Command Link In 945 SWCU117C February 2015 Revised September 2015 I O Control Submit Documentation Feedback Copyright 2015 Texa...

Page 946: ...d 28 27 WU_CFG R W 0h If DIO is configured GPIO or non AON peripheral signals that is PORT_ID 0x00 or 0x08 00 No wakeup 01 No wakeup 10 Wakes up from shutdown if this pad is going low 11 Wakes up from shutdown if this pad is going high If IO is configured for AON peripheral signals or AUX that is PORT_ID 0x01 0x08 this register only sets wakeup enable or not 00 01 Wakeup disabled 10 11 Wakeup enab...

Page 947: ... any other value than the reset value may result in undefined behavior 14 13 PULL_CTL R W 3h Pull control 1h DWN Pull down 2h UP Pull up 3h DIS No pull 12 SLEW_RED R W 0h 0 Normal slew rate 1 Enables reduced slew rate in output driver 11 10 IOCURR R W 0h Selects IO current in combination with IOSTR 0h 2MA 2 mA 1h 4MA 4 mA 2h 4_8MA 4 or 8 mA 8 mA if IO is double drive strength 9 8 IOSTR R W 0h Sele...

Page 948: ...and so on 1Ah PORT_EVENT3 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Bh PORT_EVENT4 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Ch PORT...

Page 949: ...K I2S MCLK 2Eh RF Core Trace 2Fh RF Core Data Out 0 30h RF Core Data Out 1 31h RF Core Data Out 2 32h RF Core Data Out 3 33h RF Core Data In 0 34h RF Core Data In 1 35h RF Core SMI Data Link Out 36h RF Core SMI Data Link In 37h RF Core SMI Command Link Out 38h RF Core SMI Command Link In 949 SWCU117C February 2015 Revised September 2015 I O Control Submit Documentation Feedback Copyright 2015 Texa...

Page 950: ...red 28 27 WU_CFG R W 0h If DIO is configured GPIO or non AON peripheral signals that is PORT_ID 0x00 or 0x08 00 No wakeup 01 No wakeup 10 Wakes up from shutdown if this pad is going low 11 Wakes up from shutdown if this pad is going high If IO is configured for AON peripheral signals or AUX that is PORT_ID 0x01 0x08 this register only sets wakeup enable or not 00 01 Wakeup disabled 10 11 Wakeup en...

Page 951: ...g any other value than the reset value may result in undefined behavior 14 13 PULL_CTL R W 3h Pull control 1h DWN Pull down 2h UP Pull up 3h DIS No pull 12 SLEW_RED R W 0h 0 Normal slew rate 1 Enables reduced slew rate in output driver 11 10 IOCURR R W 0h Selects IO current in combination with IOSTR 0h 2MA 2 mA 1h 4MA 4 mA 2h 4_8MA 4 or 8 mA 8 mA if IO is double drive strength 9 8 IOSTR R W 0h Sel...

Page 952: ... and so on 1Ah PORT_EVENT3 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Bh PORT_EVENT4 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Ch POR...

Page 953: ...K I2S MCLK 2Eh RF Core Trace 2Fh RF Core Data Out 0 30h RF Core Data Out 1 31h RF Core Data Out 2 32h RF Core Data Out 3 33h RF Core Data In 0 34h RF Core Data In 1 35h RF Core SMI Data Link Out 36h RF Core SMI Data Link In 37h RF Core SMI Command Link Out 38h RF Core SMI Command Link In 953 SWCU117C February 2015 Revised September 2015 I O Control Submit Documentation Feedback Copyright 2015 Texa...

Page 954: ...red 28 27 WU_CFG R W 0h If DIO is configured GPIO or non AON peripheral signals that is PORT_ID 0x00 or 0x08 00 No wakeup 01 No wakeup 10 Wakes up from shutdown if this pad is going low 11 Wakes up from shutdown if this pad is going high If IO is configured for AON peripheral signals or AUX that is PORT_ID 0x01 0x08 this register only sets wakeup enable or not 00 01 Wakeup disabled 10 11 Wakeup en...

Page 955: ...g any other value than the reset value may result in undefined behavior 14 13 PULL_CTL R W 3h Pull control 1h DWN Pull down 2h UP Pull up 3h DIS No pull 12 SLEW_RED R W 0h 0 Normal slew rate 1 Enables reduced slew rate in output driver 11 10 IOCURR R W 0h Selects IO current in combination with IOSTR 0h 2MA 2 mA 1h 4MA 4 mA 2h 4_8MA 4 or 8 mA 8 mA if IO is double drive strength 9 8 IOSTR R W 0h Sel...

Page 956: ... and so on 1Ah PORT_EVENT3 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Bh PORT_EVENT4 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Ch POR...

Page 957: ...K I2S MCLK 2Eh RF Core Trace 2Fh RF Core Data Out 0 30h RF Core Data Out 1 31h RF Core Data Out 2 32h RF Core Data Out 3 33h RF Core Data In 0 34h RF Core Data In 1 35h RF Core SMI Data Link Out 36h RF Core SMI Data Link In 37h RF Core SMI Command Link Out 38h RF Core SMI Command Link In 957 SWCU117C February 2015 Revised September 2015 I O Control Submit Documentation Feedback Copyright 2015 Texa...

Page 958: ...red 28 27 WU_CFG R W 0h If DIO is configured GPIO or non AON peripheral signals that is PORT_ID 0x00 or 0x08 00 No wakeup 01 No wakeup 10 Wakes up from shutdown if this pad is going low 11 Wakes up from shutdown if this pad is going high If IO is configured for AON peripheral signals or AUX that is PORT_ID 0x01 0x08 this register only sets wakeup enable or not 00 01 Wakeup disabled 10 11 Wakeup en...

Page 959: ...g any other value than the reset value may result in undefined behavior 14 13 PULL_CTL R W 3h Pull control 1h DWN Pull down 2h UP Pull up 3h DIS No pull 12 SLEW_RED R W 0h 0 Normal slew rate 1 Enables reduced slew rate in output driver 11 10 IOCURR R W 0h Selects IO current in combination with IOSTR 0h 2MA 2 mA 1h 4MA 4 mA 2h 4_8MA 4 or 8 mA 8 mA if IO is double drive strength 9 8 IOSTR R W 0h Sel...

Page 960: ... and so on 1Ah PORT_EVENT3 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Bh PORT_EVENT4 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Ch POR...

Page 961: ...K I2S MCLK 2Eh RF Core Trace 2Fh RF Core Data Out 0 30h RF Core Data Out 1 31h RF Core Data Out 2 32h RF Core Data Out 3 33h RF Core Data In 0 34h RF Core Data In 1 35h RF Core SMI Data Link Out 36h RF Core SMI Data Link In 37h RF Core SMI Command Link Out 38h RF Core SMI Command Link In 961 SWCU117C February 2015 Revised September 2015 I O Control Submit Documentation Feedback Copyright 2015 Texa...

Page 962: ...red 28 27 WU_CFG R W 0h If DIO is configured GPIO or non AON peripheral signals that is PORT_ID 0x00 or 0x08 00 No wakeup 01 No wakeup 10 Wakes up from shutdown if this pad is going low 11 Wakes up from shutdown if this pad is going high If IO is configured for AON peripheral signals or AUX that is PORT_ID 0x01 0x08 this register only sets wakeup enable or not 00 01 Wakeup disabled 10 11 Wakeup en...

Page 963: ...g any other value than the reset value may result in undefined behavior 14 13 PULL_CTL R W 3h Pull control 1h DWN Pull down 2h UP Pull up 3h DIS No pull 12 SLEW_RED R W 0h 0 Normal slew rate 1 Enables reduced slew rate in output driver 11 10 IOCURR R W 0h Selects IO current in combination with IOSTR 0h 2MA 2 mA 1h 4MA 4 mA 2h 4_8MA 4 or 8 mA 8 mA if IO is double drive strength 9 8 IOSTR R W 0h Sel...

Page 964: ... and so on 1Ah PORT_EVENT3 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Bh PORT_EVENT4 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Ch POR...

Page 965: ...K I2S MCLK 2Eh RF Core Trace 2Fh RF Core Data Out 0 30h RF Core Data Out 1 31h RF Core Data Out 2 32h RF Core Data Out 3 33h RF Core Data In 0 34h RF Core Data In 1 35h RF Core SMI Data Link Out 36h RF Core SMI Data Link In 37h RF Core SMI Command Link Out 38h RF Core SMI Command Link In 965 SWCU117C February 2015 Revised September 2015 I O Control Submit Documentation Feedback Copyright 2015 Texa...

Page 966: ...red 28 27 WU_CFG R W 0h If DIO is configured GPIO or non AON peripheral signals that is PORT_ID 0x00 or 0x08 00 No wakeup 01 No wakeup 10 Wakes up from shutdown if this pad is going low 11 Wakes up from shutdown if this pad is going high If IO is configured for AON peripheral signals or AUX that is PORT_ID 0x01 0x08 this register only sets wakeup enable or not 00 01 Wakeup disabled 10 11 Wakeup en...

Page 967: ...g any other value than the reset value may result in undefined behavior 14 13 PULL_CTL R W 3h Pull control 1h DWN Pull down 2h UP Pull up 3h DIS No pull 12 SLEW_RED R W 0h 0 Normal slew rate 1 Enables reduced slew rate in output driver 11 10 IOCURR R W 0h Selects IO current in combination with IOSTR 0h 2MA 2 mA 1h 4MA 4 mA 2h 4_8MA 4 or 8 mA 8 mA if IO is double drive strength 9 8 IOSTR R W 0h Sel...

Page 968: ... and so on 1Ah PORT_EVENT3 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Bh PORT_EVENT4 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Ch POR...

Page 969: ...K I2S MCLK 2Eh RF Core Trace 2Fh RF Core Data Out 0 30h RF Core Data Out 1 31h RF Core Data Out 2 32h RF Core Data Out 3 33h RF Core Data In 0 34h RF Core Data In 1 35h RF Core SMI Data Link Out 36h RF Core SMI Data Link In 37h RF Core SMI Command Link Out 38h RF Core SMI Command Link In 969 SWCU117C February 2015 Revised September 2015 I O Control Submit Documentation Feedback Copyright 2015 Texa...

Page 970: ...red 28 27 WU_CFG R W 0h If DIO is configured GPIO or non AON peripheral signals that is PORT_ID 0x00 or 0x08 00 No wakeup 01 No wakeup 10 Wakes up from shutdown if this pad is going low 11 Wakes up from shutdown if this pad is going high If IO is configured for AON peripheral signals or AUX that is PORT_ID 0x01 0x08 this register only sets wakeup enable or not 00 01 Wakeup disabled 10 11 Wakeup en...

Page 971: ...g any other value than the reset value may result in undefined behavior 14 13 PULL_CTL R W 3h Pull control 1h DWN Pull down 2h UP Pull up 3h DIS No pull 12 SLEW_RED R W 0h 0 Normal slew rate 1 Enables reduced slew rate in output driver 11 10 IOCURR R W 0h Selects IO current in combination with IOSTR 0h 2MA 2 mA 1h 4MA 4 mA 2h 4_8MA 4 or 8 mA 8 mA if IO is double drive strength 9 8 IOSTR R W 0h Sel...

Page 972: ... and so on 1Ah PORT_EVENT3 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Bh PORT_EVENT4 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Ch POR...

Page 973: ...K I2S MCLK 2Eh RF Core Trace 2Fh RF Core Data Out 0 30h RF Core Data Out 1 31h RF Core Data Out 2 32h RF Core Data Out 3 33h RF Core Data In 0 34h RF Core Data In 1 35h RF Core SMI Data Link Out 36h RF Core SMI Data Link In 37h RF Core SMI Command Link Out 38h RF Core SMI Command Link In 973 SWCU117C February 2015 Revised September 2015 I O Control Submit Documentation Feedback Copyright 2015 Texa...

Page 974: ...ored 28 27 WU_CFG R W 0h If DIO is configured GPIO or non AON peripheral signals that is PORT_ID 0x00 or 0x08 00 No wakeup 01 No wakeup 10 Wakes up from shutdown if this pad is going low 11 Wakes up from shutdown if this pad is going high If IO is configured for AON peripheral signals or AUX that is PORT_ID 0x01 0x08 this register only sets wakeup enable or not 00 01 Wakeup disabled 10 11 Wakeup e...

Page 975: ...g any other value than the reset value may result in undefined behavior 14 13 PULL_CTL R W 3h Pull control 1h DWN Pull down 2h UP Pull up 3h DIS No pull 12 SLEW_RED R W 0h 0 Normal slew rate 1 Enables reduced slew rate in output driver 11 10 IOCURR R W 0h Selects IO current in combination with IOSTR 0h 2MA 2 mA 1h 4MA 4 mA 2h 4_8MA 4 or 8 mA 8 mA if IO is double drive strength 9 8 IOSTR R W 0h Sel...

Page 976: ... and so on 1Ah PORT_EVENT3 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Bh PORT_EVENT4 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Ch POR...

Page 977: ...K I2S MCLK 2Eh RF Core Trace 2Fh RF Core Data Out 0 30h RF Core Data Out 1 31h RF Core Data Out 2 32h RF Core Data Out 3 33h RF Core Data In 0 34h RF Core Data In 1 35h RF Core SMI Data Link Out 36h RF Core SMI Data Link In 37h RF Core SMI Command Link Out 38h RF Core SMI Command Link In 977 SWCU117C February 2015 Revised September 2015 I O Control Submit Documentation Feedback Copyright 2015 Texa...

Page 978: ...e ignored 28 27 WU_CFG R W 0h If DIO is configured GPIO or non AON peripheral signals that is PORT_ID 0x00 or 0x08 00 No wakeup 01 No wakeup 10 Wakes up from shutdown if this pad is going low 11 Wakes up from shutdown if this pad is going high If IO is configured for AON peripheral signals or AUX that is PORT_ID 0x01 0x08 this register only sets wakeup enable or not 00 01 Wakeup disabled 10 11 Wak...

Page 979: ...ing any other value than the reset value may result in undefined behavior 14 13 PULL_CTL R W 3h Pull control 1h DWN Pull down 2h UP Pull up 3h DIS No pull 12 SLEW_RED R W 0h 0 Normal slew rate 1 Enables reduced slew rate in output driver 11 10 IOCURR R W 0h Selects IO current in combination with IOSTR 0h 2MA 2 mA 1h 4MA 4 mA 2h 4_8MA 4 or 8 mA 8 mA if IO is double drive strength 9 8 IOSTR R W 0h S...

Page 980: ... and so on 1Ah PORT_EVENT3 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Bh PORT_EVENT4 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Ch POR...

Page 981: ...K I2S MCLK 2Eh RF Core Trace 2Fh RF Core Data Out 0 30h RF Core Data Out 1 31h RF Core Data Out 2 32h RF Core Data Out 3 33h RF Core Data In 0 34h RF Core Data In 1 35h RF Core SMI Data Link Out 36h RF Core SMI Data Link In 37h RF Core SMI Command Link Out 38h RF Core SMI Command Link In 981 SWCU117C February 2015 Revised September 2015 I O Control Submit Documentation Feedback Copyright 2015 Texa...

Page 982: ...red 28 27 WU_CFG R W 0h If DIO is configured GPIO or non AON peripheral signals that is PORT_ID 0x00 or 0x08 00 No wakeup 01 No wakeup 10 Wakes up from shutdown if this pad is going low 11 Wakes up from shutdown if this pad is going high If IO is configured for AON peripheral signals or AUX that is PORT_ID 0x01 0x08 this register only sets wakeup enable or not 00 01 Wakeup disabled 10 11 Wakeup en...

Page 983: ...g any other value than the reset value may result in undefined behavior 14 13 PULL_CTL R W 3h Pull control 1h DWN Pull down 2h UP Pull up 3h DIS No pull 12 SLEW_RED R W 0h 0 Normal slew rate 1 Enables reduced slew rate in output driver 11 10 IOCURR R W 0h Selects IO current in combination with IOSTR 0h 2MA 2 mA 1h 4MA 4 mA 2h 4_8MA 4 or 8 mA 8 mA if IO is double drive strength 9 8 IOSTR R W 0h Sel...

Page 984: ... and so on 1Ah PORT_EVENT3 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Bh PORT_EVENT4 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Ch POR...

Page 985: ...K I2S MCLK 2Eh RF Core Trace 2Fh RF Core Data Out 0 30h RF Core Data Out 1 31h RF Core Data Out 2 32h RF Core Data Out 3 33h RF Core Data In 0 34h RF Core Data In 1 35h RF Core SMI Data Link Out 36h RF Core SMI Data Link In 37h RF Core SMI Command Link Out 38h RF Core SMI Command Link In 985 SWCU117C February 2015 Revised September 2015 I O Control Submit Documentation Feedback Copyright 2015 Texa...

Page 986: ...red 28 27 WU_CFG R W 0h If DIO is configured GPIO or non AON peripheral signals that is PORT_ID 0x00 or 0x08 00 No wakeup 01 No wakeup 10 Wakes up from shutdown if this pad is going low 11 Wakes up from shutdown if this pad is going high If IO is configured for AON peripheral signals or AUX that is PORT_ID 0x01 0x08 this register only sets wakeup enable or not 00 01 Wakeup disabled 10 11 Wakeup en...

Page 987: ...g any other value than the reset value may result in undefined behavior 14 13 PULL_CTL R W 3h Pull control 1h DWN Pull down 2h UP Pull up 3h DIS No pull 12 SLEW_RED R W 0h 0 Normal slew rate 1 Enables reduced slew rate in output driver 11 10 IOCURR R W 0h Selects IO current in combination with IOSTR 0h 2MA 2 mA 1h 4MA 4 mA 2h 4_8MA 4 or 8 mA 8 mA if IO is double drive strength 9 8 IOSTR R W 0h Sel...

Page 988: ... and so on 1Ah PORT_EVENT3 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Bh PORT_EVENT4 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Ch POR...

Page 989: ...K I2S MCLK 2Eh RF Core Trace 2Fh RF Core Data Out 0 30h RF Core Data Out 1 31h RF Core Data Out 2 32h RF Core Data Out 3 33h RF Core Data In 0 34h RF Core Data In 1 35h RF Core SMI Data Link Out 36h RF Core SMI Data Link In 37h RF Core SMI Command Link Out 38h RF Core SMI Command Link In 989 SWCU117C February 2015 Revised September 2015 I O Control Submit Documentation Feedback Copyright 2015 Texa...

Page 990: ...red 28 27 WU_CFG R W 0h If DIO is configured GPIO or non AON peripheral signals that is PORT_ID 0x00 or 0x08 00 No wakeup 01 No wakeup 10 Wakes up from shutdown if this pad is going low 11 Wakes up from shutdown if this pad is going high If IO is configured for AON peripheral signals or AUX that is PORT_ID 0x01 0x08 this register only sets wakeup enable or not 00 01 Wakeup disabled 10 11 Wakeup en...

Page 991: ...g any other value than the reset value may result in undefined behavior 14 13 PULL_CTL R W 3h Pull control 1h DWN Pull down 2h UP Pull up 3h DIS No pull 12 SLEW_RED R W 0h 0 Normal slew rate 1 Enables reduced slew rate in output driver 11 10 IOCURR R W 0h Selects IO current in combination with IOSTR 0h 2MA 2 mA 1h 4MA 4 mA 2h 4_8MA 4 or 8 mA 8 mA if IO is double drive strength 9 8 IOSTR R W 0h Sel...

Page 992: ... and so on 1Ah PORT_EVENT3 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Bh PORT_EVENT4 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Ch POR...

Page 993: ...K I2S MCLK 2Eh RF Core Trace 2Fh RF Core Data Out 0 30h RF Core Data Out 1 31h RF Core Data Out 2 32h RF Core Data Out 3 33h RF Core Data In 0 34h RF Core Data In 1 35h RF Core SMI Data Link Out 36h RF Core SMI Data Link In 37h RF Core SMI Command Link Out 38h RF Core SMI Command Link In 993 SWCU117C February 2015 Revised September 2015 I O Control Submit Documentation Feedback Copyright 2015 Texa...

Page 994: ...red 28 27 WU_CFG R W 0h If DIO is configured GPIO or non AON peripheral signals that is PORT_ID 0x00 or 0x08 00 No wakeup 01 No wakeup 10 Wakes up from shutdown if this pad is going low 11 Wakes up from shutdown if this pad is going high If IO is configured for AON peripheral signals or AUX that is PORT_ID 0x01 0x08 this register only sets wakeup enable or not 00 01 Wakeup disabled 10 11 Wakeup en...

Page 995: ...g any other value than the reset value may result in undefined behavior 14 13 PULL_CTL R W 3h Pull control 1h DWN Pull down 2h UP Pull up 3h DIS No pull 12 SLEW_RED R W 0h 0 Normal slew rate 1 Enables reduced slew rate in output driver 11 10 IOCURR R W 0h Selects IO current in combination with IOSTR 0h 2MA 2 mA 1h 4MA 4 mA 2h 4_8MA 4 or 8 mA 8 mA if IO is double drive strength 9 8 IOSTR R W 0h Sel...

Page 996: ... and so on 1Ah PORT_EVENT3 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Bh PORT_EVENT4 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Ch POR...

Page 997: ...K I2S MCLK 2Eh RF Core Trace 2Fh RF Core Data Out 0 30h RF Core Data Out 1 31h RF Core Data Out 2 32h RF Core Data Out 3 33h RF Core Data In 0 34h RF Core Data In 1 35h RF Core SMI Data Link Out 36h RF Core SMI Data Link In 37h RF Core SMI Command Link Out 38h RF Core SMI Command Link In 997 SWCU117C February 2015 Revised September 2015 I O Control Submit Documentation Feedback Copyright 2015 Texa...

Page 998: ...red 28 27 WU_CFG R W 0h If DIO is configured GPIO or non AON peripheral signals that is PORT_ID 0x00 or 0x08 00 No wakeup 01 No wakeup 10 Wakes up from shutdown if this pad is going low 11 Wakes up from shutdown if this pad is going high If IO is configured for AON peripheral signals or AUX that is PORT_ID 0x01 0x08 this register only sets wakeup enable or not 00 01 Wakeup disabled 10 11 Wakeup en...

Page 999: ...g any other value than the reset value may result in undefined behavior 14 13 PULL_CTL R W 3h Pull control 1h DWN Pull down 2h UP Pull up 3h DIS No pull 12 SLEW_RED R W 0h 0 Normal slew rate 1 Enables reduced slew rate in output driver 11 10 IOCURR R W 0h Selects IO current in combination with IOSTR 0h 2MA 2 mA 1h 4MA 4 mA 2h 4_8MA 4 or 8 mA 8 mA if IO is double drive strength 9 8 IOSTR R W 0h Sel...

Page 1000: ...and so on 1Ah PORT_EVENT3 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Bh PORT_EVENT4 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Ch PORT...

Page 1001: ...K I2S MCLK 2Eh RF Core Trace 2Fh RF Core Data Out 0 30h RF Core Data Out 1 31h RF Core Data Out 2 32h RF Core Data Out 3 33h RF Core Data In 0 34h RF Core Data In 1 35h RF Core SMI Data Link Out 36h RF Core SMI Data Link In 37h RF Core SMI Command Link Out 38h RF Core SMI Command Link In 1001 SWCU117C February 2015 Revised September 2015 I O Control Submit Documentation Feedback Copyright 2015 Tex...

Page 1002: ...red 28 27 WU_CFG R W 0h If DIO is configured GPIO or non AON peripheral signals that is PORT_ID 0x00 or 0x08 00 No wakeup 01 No wakeup 10 Wakes up from shutdown if this pad is going low 11 Wakes up from shutdown if this pad is going high If IO is configured for AON peripheral signals or AUX that is PORT_ID 0x01 0x08 this register only sets wakeup enable or not 00 01 Wakeup disabled 10 11 Wakeup en...

Page 1003: ... any other value than the reset value may result in undefined behavior 14 13 PULL_CTL R W 3h Pull control 1h DWN Pull down 2h UP Pull up 3h DIS No pull 12 SLEW_RED R W 0h 0 Normal slew rate 1 Enables reduced slew rate in output driver 11 10 IOCURR R W 0h Selects IO current in combination with IOSTR 0h 2MA 2 mA 1h 4MA 4 mA 2h 4_8MA 4 or 8 mA 8 mA if IO is double drive strength 9 8 IOSTR R W 0h Sele...

Page 1004: ...and so on 1Ah PORT_EVENT3 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Bh PORT_EVENT4 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Ch PORT...

Page 1005: ...K I2S MCLK 2Eh RF Core Trace 2Fh RF Core Data Out 0 30h RF Core Data Out 1 31h RF Core Data Out 2 32h RF Core Data Out 3 33h RF Core Data In 0 34h RF Core Data In 1 35h RF Core SMI Data Link Out 36h RF Core SMI Data Link In 37h RF Core SMI Command Link Out 38h RF Core SMI Command Link In 1005 SWCU117C February 2015 Revised September 2015 I O Control Submit Documentation Feedback Copyright 2015 Tex...

Page 1006: ...red 28 27 WU_CFG R W 0h If DIO is configured GPIO or non AON peripheral signals that is PORT_ID 0x00 or 0x08 00 No wakeup 01 No wakeup 10 Wakes up from shutdown if this pad is going low 11 Wakes up from shutdown if this pad is going high If IO is configured for AON peripheral signals or AUX that is PORT_ID 0x01 0x08 this register only sets wakeup enable or not 00 01 Wakeup disabled 10 11 Wakeup en...

Page 1007: ... any other value than the reset value may result in undefined behavior 14 13 PULL_CTL R W 3h Pull control 1h DWN Pull down 2h UP Pull up 3h DIS No pull 12 SLEW_RED R W 0h 0 Normal slew rate 1 Enables reduced slew rate in output driver 11 10 IOCURR R W 0h Selects IO current in combination with IOSTR 0h 2MA 2 mA 1h 4MA 4 mA 2h 4_8MA 4 or 8 mA 8 mA if IO is double drive strength 9 8 IOSTR R W 0h Sele...

Page 1008: ...and so on 1Ah PORT_EVENT3 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Bh PORT_EVENT4 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Ch PORT...

Page 1009: ...K I2S MCLK 2Eh RF Core Trace 2Fh RF Core Data Out 0 30h RF Core Data Out 1 31h RF Core Data Out 2 32h RF Core Data Out 3 33h RF Core Data In 0 34h RF Core Data In 1 35h RF Core SMI Data Link Out 36h RF Core SMI Data Link In 37h RF Core SMI Command Link Out 38h RF Core SMI Command Link In 1009 SWCU117C February 2015 Revised September 2015 I O Control Submit Documentation Feedback Copyright 2015 Tex...

Page 1010: ...red 28 27 WU_CFG R W 0h If DIO is configured GPIO or non AON peripheral signals that is PORT_ID 0x00 or 0x08 00 No wakeup 01 No wakeup 10 Wakes up from shutdown if this pad is going low 11 Wakes up from shutdown if this pad is going high If IO is configured for AON peripheral signals or AUX that is PORT_ID 0x01 0x08 this register only sets wakeup enable or not 00 01 Wakeup disabled 10 11 Wakeup en...

Page 1011: ... any other value than the reset value may result in undefined behavior 14 13 PULL_CTL R W 3h Pull control 1h DWN Pull down 2h UP Pull up 3h DIS No pull 12 SLEW_RED R W 0h 0 Normal slew rate 1 Enables reduced slew rate in output driver 11 10 IOCURR R W 0h Selects IO current in combination with IOSTR 0h 2MA 2 mA 1h 4MA 4 mA 2h 4_8MA 4 or 8 mA 8 mA if IO is double drive strength 9 8 IOSTR R W 0h Sele...

Page 1012: ...and so on 1Ah PORT_EVENT3 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Bh PORT_EVENT4 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Ch PORT...

Page 1013: ...K I2S MCLK 2Eh RF Core Trace 2Fh RF Core Data Out 0 30h RF Core Data Out 1 31h RF Core Data Out 2 32h RF Core Data Out 3 33h RF Core Data In 0 34h RF Core Data In 1 35h RF Core SMI Data Link Out 36h RF Core SMI Data Link In 37h RF Core SMI Command Link Out 38h RF Core SMI Command Link In 1013 SWCU117C February 2015 Revised September 2015 I O Control Submit Documentation Feedback Copyright 2015 Tex...

Page 1014: ...red 28 27 WU_CFG R W 0h If DIO is configured GPIO or non AON peripheral signals that is PORT_ID 0x00 or 0x08 00 No wakeup 01 No wakeup 10 Wakes up from shutdown if this pad is going low 11 Wakes up from shutdown if this pad is going high If IO is configured for AON peripheral signals or AUX that is PORT_ID 0x01 0x08 this register only sets wakeup enable or not 00 01 Wakeup disabled 10 11 Wakeup en...

Page 1015: ... any other value than the reset value may result in undefined behavior 14 13 PULL_CTL R W 3h Pull control 1h DWN Pull down 2h UP Pull up 3h DIS No pull 12 SLEW_RED R W 0h 0 Normal slew rate 1 Enables reduced slew rate in output driver 11 10 IOCURR R W 0h Selects IO current in combination with IOSTR 0h 2MA 2 mA 1h 4MA 4 mA 2h 4_8MA 4 or 8 mA 8 mA if IO is double drive strength 9 8 IOSTR R W 0h Sele...

Page 1016: ...and so on 1Ah PORT_EVENT3 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Bh PORT_EVENT4 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Ch PORT...

Page 1017: ...K I2S MCLK 2Eh RF Core Trace 2Fh RF Core Data Out 0 30h RF Core Data Out 1 31h RF Core Data Out 2 32h RF Core Data Out 3 33h RF Core Data In 0 34h RF Core Data In 1 35h RF Core SMI Data Link Out 36h RF Core SMI Data Link In 37h RF Core SMI Command Link Out 38h RF Core SMI Command Link In 1017 SWCU117C February 2015 Revised September 2015 I O Control Submit Documentation Feedback Copyright 2015 Tex...

Page 1018: ...red 28 27 WU_CFG R W 0h If DIO is configured GPIO or non AON peripheral signals that is PORT_ID 0x00 or 0x08 00 No wakeup 01 No wakeup 10 Wakes up from shutdown if this pad is going low 11 Wakes up from shutdown if this pad is going high If IO is configured for AON peripheral signals or AUX that is PORT_ID 0x01 0x08 this register only sets wakeup enable or not 00 01 Wakeup disabled 10 11 Wakeup en...

Page 1019: ... any other value than the reset value may result in undefined behavior 14 13 PULL_CTL R W 3h Pull control 1h DWN Pull down 2h UP Pull up 3h DIS No pull 12 SLEW_RED R W 0h 0 Normal slew rate 1 Enables reduced slew rate in output driver 11 10 IOCURR R W 0h Selects IO current in combination with IOSTR 0h 2MA 2 mA 1h 4MA 4 mA 2h 4_8MA 4 or 8 mA 8 mA if IO is double drive strength 9 8 IOSTR R W 0h Sele...

Page 1020: ...and so on 1Ah PORT_EVENT3 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Bh PORT_EVENT4 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Ch PORT...

Page 1021: ...K I2S MCLK 2Eh RF Core Trace 2Fh RF Core Data Out 0 30h RF Core Data Out 1 31h RF Core Data Out 2 32h RF Core Data Out 3 33h RF Core Data In 0 34h RF Core Data In 1 35h RF Core SMI Data Link Out 36h RF Core SMI Data Link In 37h RF Core SMI Command Link Out 38h RF Core SMI Command Link In 1021 SWCU117C February 2015 Revised September 2015 I O Control Submit Documentation Feedback Copyright 2015 Tex...

Page 1022: ...red 28 27 WU_CFG R W 0h If DIO is configured GPIO or non AON peripheral signals that is PORT_ID 0x00 or 0x08 00 No wakeup 01 No wakeup 10 Wakes up from shutdown if this pad is going low 11 Wakes up from shutdown if this pad is going high If IO is configured for AON peripheral signals or AUX that is PORT_ID 0x01 0x08 this register only sets wakeup enable or not 00 01 Wakeup disabled 10 11 Wakeup en...

Page 1023: ... any other value than the reset value may result in undefined behavior 14 13 PULL_CTL R W 3h Pull control 1h DWN Pull down 2h UP Pull up 3h DIS No pull 12 SLEW_RED R W 0h 0 Normal slew rate 1 Enables reduced slew rate in output driver 11 10 IOCURR R W 0h Selects IO current in combination with IOSTR 0h 2MA 2 mA 1h 4MA 4 mA 2h 4_8MA 4 or 8 mA 8 mA if IO is double drive strength 9 8 IOSTR R W 0h Sele...

Page 1024: ...and so on 1Ah PORT_EVENT3 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Bh PORT_EVENT4 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Ch PORT...

Page 1025: ...K I2S MCLK 2Eh RF Core Trace 2Fh RF Core Data Out 0 30h RF Core Data Out 1 31h RF Core Data Out 2 32h RF Core Data Out 3 33h RF Core Data In 0 34h RF Core Data In 1 35h RF Core SMI Data Link Out 36h RF Core SMI Data Link In 37h RF Core SMI Command Link Out 38h RF Core SMI Command Link In 1025 SWCU117C February 2015 Revised September 2015 I O Control Submit Documentation Feedback Copyright 2015 Tex...

Page 1026: ...red 28 27 WU_CFG R W 0h If DIO is configured GPIO or non AON peripheral signals that is PORT_ID 0x00 or 0x08 00 No wakeup 01 No wakeup 10 Wakes up from shutdown if this pad is going low 11 Wakes up from shutdown if this pad is going high If IO is configured for AON peripheral signals or AUX that is PORT_ID 0x01 0x08 this register only sets wakeup enable or not 00 01 Wakeup disabled 10 11 Wakeup en...

Page 1027: ... any other value than the reset value may result in undefined behavior 14 13 PULL_CTL R W 3h Pull control 1h DWN Pull down 2h UP Pull up 3h DIS No pull 12 SLEW_RED R W 0h 0 Normal slew rate 1 Enables reduced slew rate in output driver 11 10 IOCURR R W 0h Selects IO current in combination with IOSTR 0h 2MA 2 mA 1h 4MA 4 mA 2h 4_8MA 4 or 8 mA 8 mA if IO is double drive strength 9 8 IOSTR R W 0h Sele...

Page 1028: ...and so on 1Ah PORT_EVENT3 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Bh PORT_EVENT4 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Ch PORT...

Page 1029: ...K I2S MCLK 2Eh RF Core Trace 2Fh RF Core Data Out 0 30h RF Core Data Out 1 31h RF Core Data Out 2 32h RF Core Data Out 3 33h RF Core Data In 0 34h RF Core Data In 1 35h RF Core SMI Data Link Out 36h RF Core SMI Data Link In 37h RF Core SMI Command Link Out 38h RF Core SMI Command Link In 1029 SWCU117C February 2015 Revised September 2015 I O Control Submit Documentation Feedback Copyright 2015 Tex...

Page 1030: ...red 28 27 WU_CFG R W 0h If DIO is configured GPIO or non AON peripheral signals that is PORT_ID 0x00 or 0x08 00 No wakeup 01 No wakeup 10 Wakes up from shutdown if this pad is going low 11 Wakes up from shutdown if this pad is going high If IO is configured for AON peripheral signals or AUX that is PORT_ID 0x01 0x08 this register only sets wakeup enable or not 00 01 Wakeup disabled 10 11 Wakeup en...

Page 1031: ... any other value than the reset value may result in undefined behavior 14 13 PULL_CTL R W 3h Pull control 1h DWN Pull down 2h UP Pull up 3h DIS No pull 12 SLEW_RED R W 0h 0 Normal slew rate 1 Enables reduced slew rate in output driver 11 10 IOCURR R W 0h Selects IO current in combination with IOSTR 0h 2MA 2 mA 1h 4MA 4 mA 2h 4_8MA 4 or 8 mA 8 mA if IO is double drive strength 9 8 IOSTR R W 0h Sele...

Page 1032: ...and so on 1Ah PORT_EVENT3 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Bh PORT_EVENT4 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Ch PORT...

Page 1033: ...K I2S MCLK 2Eh RF Core Trace 2Fh RF Core Data Out 0 30h RF Core Data Out 1 31h RF Core Data Out 2 32h RF Core Data Out 3 33h RF Core Data In 0 34h RF Core Data In 1 35h RF Core SMI Data Link Out 36h RF Core SMI Data Link In 37h RF Core SMI Command Link Out 38h RF Core SMI Command Link In 1033 SWCU117C February 2015 Revised September 2015 I O Control Submit Documentation Feedback Copyright 2015 Tex...

Page 1034: ...red 28 27 WU_CFG R W 0h If DIO is configured GPIO or non AON peripheral signals that is PORT_ID 0x00 or 0x08 00 No wakeup 01 No wakeup 10 Wakes up from shutdown if this pad is going low 11 Wakes up from shutdown if this pad is going high If IO is configured for AON peripheral signals or AUX that is PORT_ID 0x01 0x08 this register only sets wakeup enable or not 00 01 Wakeup disabled 10 11 Wakeup en...

Page 1035: ... any other value than the reset value may result in undefined behavior 14 13 PULL_CTL R W 3h Pull control 1h DWN Pull down 2h UP Pull up 3h DIS No pull 12 SLEW_RED R W 0h 0 Normal slew rate 1 Enables reduced slew rate in output driver 11 10 IOCURR R W 0h Selects IO current in combination with IOSTR 0h 2MA 2 mA 1h 4MA 4 mA 2h 4_8MA 4 or 8 mA 8 mA if IO is double drive strength 9 8 IOSTR R W 0h Sele...

Page 1036: ...and so on 1Ah PORT_EVENT3 PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Bh PORT_EVENT4 PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module for example EVENT GPT0ACAPTSEL EV EVENT UDMACH14BSEL EV and so on 1Ch PORT...

Page 1037: ...K I2S MCLK 2Eh RF Core Trace 2Fh RF Core Data Out 0 30h RF Core Data Out 1 31h RF Core Data Out 2 32h RF Core Data Out 3 33h RF Core Data In 0 34h RF Core Data In 1 35h RF Core SMI Data Link Out 36h RF Core SMI Data Link In 37h RF Core SMI Command Link Out 38h RF Core SMI Command Link In 1037 SWCU117C February 2015 Revised September 2015 I O Control Submit Documentation Feedback Copyright 2015 Tex...

Page 1038: ...ntroller known as μDMA Topic Page 12 1 μDMA Introduction 1040 12 2 Block Diagram 1041 12 3 Functional Description 1041 12 4 Initialization and Configuration 1054 12 5 µDMA Registers 1056 1038 Micro Direct Memory Access µDMA SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 1039: ...nsfer scenarios Ping pong for continuous data flow Scatter gather for a programmable list of arbitrary transfers initiated from a single request Highly flexible and configurable channel operation Independently configured and operated channels Dedicated channels for supported on chip modules Primary and secondary channel assignments Flexible channel assignments One channel each for receive and tran...

Page 1040: ...ticated programmed data transfers Each supported peripheral function has a dedicated channel on the μDMA controller that can be configured independently The μDMA controller implements a configuration method using channel control structures maintained in system memory by the processor While simple transfer modes are supported it is also possible to build up sophisticated task lists in memory that a...

Page 1041: ... 17 SSP1_TX 1 yes yes 0 0 16 SSP1_RX 1 yes yes 0 0 15 AON_RTC 0 0 1 14 DMA_PROG 0 0 1 13 AON_PROG2 0 0 1 12 GPT1_B 1 yes 1 0 11 GPT1_A 1 yes 1 0 10 GPT0_B 1 yes 1 0 9 GPT0_A 1 yes 1 0 8 AUX_SW 0 0 1 7 AUX_ADC 1 yes yes 0 1 1 6 SPIS_TX 1 yes yes 0 1 1 5 SPIS_RX 1 yes yes 0 1 1 4 SSP0_TX 1 yes yes 0 0 3 SSP0_RX 1 yes yes 0 0 2 UART0_TX 1 yes yes 0 0 1 UART0_RX 1 yes yes 0 0 0 1 Software 0 1 yes yes ...

Page 1042: ...ty channels must not use a large arbitration size for best response on high priority channels The arbitration size can also be thought of as burst size Arbitration size is the maximum number of items that are transferred at any one time in a burst Here the term arbitration refers to the determination of the μDMA channel priority not arbitration for the bus When the μDMA controller arbitrates for t...

Page 1043: ... a set of channel control structures in a table The control table may have one or two entries for each μDMA channel Each entry in the table structure contains source and destination pointers transfer size and transfer mode The control table can be located anywhere in system memory but it must be contiguous and aligned on a 1024 byte boundary Table 12 3 describes the memory layout of the channel co...

Page 1044: ... flag Transfer mode The control parameters for a channel can be set using the driver library function void uDMAChannelControlSet function The μDMA controller updates the transfer size and transfer mode fields as the transfer is performed At the end of a transfer the transfer size indicates 0 and the transfer mode indicates stopped Because the control word is modified by the μDMA controller it must...

Page 1045: ... 6 3 Auto Mode Auto mode is similar to basic mode except that when a transfer request is received the transfer completes even if the μDMA request is removed This mode is suitable for software triggered transfers Generally auto mode is not used with a peripheral The μDMA controller sets the mode for that channel to stop when all the items have been transferred using auto mode 12 3 6 4 Ping pong Pin...

Page 1046: ...d alternate structure x Process data in BUFFER A x Reload alternate structure µDMA controller Cortex M3 processor Time Peripheral or µDMA interrupt Peripheral or µDMA interrupt SOURCE DEST CONTROL Unused SOURCE DEST CONTROL Unused SOURCE DEST CONTROL Unused SOURCE DEST CONTROL Unused Transfers using BUFFER A Functional Description www ti com Figure 12 2 shows an example operation in ping pong mode...

Page 1047: ... the beginning of the list or to a new list It is also possible to trigger a set of other channels to perform a transfer either directly by programming a write to the software trigger for another channel or indirectly by causing a peripheral action that results in a μDMA request By programming the μDMA controller using this method a set of arbitrary transfers can be performed based on a single μDM...

Page 1048: ...tter gather Setup and Configuration 1 The application has a need to copy data items from three separate locations in memory into one combined buffer 2 The application sets up µDMA task list in memory which contains the pointers and control configuration for three µDMA copy tasks 3 The application sets up the channel primary control structure to copy each task configuration one at a time to the alt...

Page 1049: ...ure of the channel Then using the alternate control structure of the channel the µDMA controller copies data from source buffer B to the destination buffer µDMA control table in memory Buffers in memory Using the primary control structure of the channel the µDMA controller copies task C configuration to the alternate control structure of the channel Then using the alternate control structure of th...

Page 1050: ...in memory is copied to a single peripheral data register Figure 12 5 shows how the application sets up a µDMA task list in memory that is then used by the controller to perform three sets of copy operations from different locations in memory The primary control structure for the channel used for the operation is configured to copy from the task list to the alternate control structure Figure 12 6 s...

Page 1051: ...ing the alternate control structure of the channel the µDMA controller copies data from source buffer B to the peripheral data register µDMA control table in memory Buffers in memory Using the primary control structure of the channel the µDMA controller copies task C configuration to the alternate control structure of the channel Then using the alternate control structure of the channel the µDMA c...

Page 1052: ...st signal is disabled or masked when the channel request mask bit is set When the request is not masked the μDMA channel is configured correctly and enabled the peripheral asserts the request signal and the μDMA controller begins the transfer NOTE The peripheral must disable all interrupts to the event fabric when using μDMA to transfer data to and from a peripheral When a μDMA transfer is complet...

Page 1053: ...or as it tries to perform a data transfer the controller disables the μDMA channel that caused the error and generates an interrupt on the μDMA error interrupt vector The processor can read the DMA Clear Bus Error Register UDMA ERROR to determine if an error is pending The STATUS bit is set if an error occurred The error can be cleared by setting the STATUS bit to 1 NOTE The error interrupt or eve...

Page 1054: ...ntroller to recognize requests for this channel 12 4 2 2 Configure the Channel Control Structure This example transfers 256 words from one memory buffer to another Channel 0 is used for a software transfer and the control structure for channel 0 must be configured to transfer 8 bit data with source and destination increments in bytes and byte wise buffer copy A bus arbitration size of eight can be...

Page 1055: ...st Section 12 5 1 7 1Ch CLEARBURST Channel Clear UseBurst Section 12 5 1 8 20h SETREQMASK Channel Set Request Mask Section 12 5 1 9 24h CLEARREQMASK Clear Channel Request Mask Section 12 5 1 10 28h SETCHANNELEN Set Channel Enable Section 12 5 1 11 2Ch CLEARCHANNELEN Clear Channel Enable Section 12 5 1 12 30h SETCHNLPRIALT Channel Set Primary Alternate Section 12 5 1 13 34h CLEARCHNLPRIALT Channel ...

Page 1056: ...that the controller is configured to use 1 uDMA channel 0x01 Shows that the controller is configured to use 2 uDMA channels 0x1F Shows that the controller is configured to use 32 uDMA channels 32 1 31 0x1F 15 8 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 7 4 STATE R 0h Current state of the control sta...

Page 1057: ...iption 0 MASTERENABLE R 0h Shows the enable status of the controller as configured by CFG MASTERENABLE 0 Controller is disabled 1 Controller is enabled 1057 SWCU117C February 2015 Revised September 2015 Micro Direct Memory Access µDMA Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 1058: ...ite bus protocol protection state by controlling the AHB signal HProt 3 1 as follows Bit 7 Controls HProt 3 to indicate if a cacheable access is occurring Bit 6 Controls HProt 2 to indicate if a bufferable access is occurring Bit 5 Controls HProt 1 to indicate if a privileged access is occurring When bit n 1 then the corresponding HProt is high When bit n 0 then the corresponding HProt is low 4 1 ...

Page 1059: ... Type Reset Description 31 10 BASEPTR R W 0h This register point to the base address for the primary data structures of each DMA channel This is not stored in module but in system memory thus space must be allocated for this usage when DMA is in usage 9 0 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior ...

Page 1060: ... 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BASEPTR R 200h Table 12 11 ALTCTRL Register Field Descriptions Bit Field Type Reset Description 31 0 BASEPTR R 200h This register shows the base address for the alternate data structures and is calculated by module thus read only 1060 Micro Direct Memory Access µDMA SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Cop...

Page 1061: ... R FFFF1EFFh Channel wait on request status Bit Ch 0 Once uDMA receives a single or burst request on channel Ch this channel may come out of active state even if request is still present Bit Ch 1 Once uDMA receives a single or burst request on channel Ch it keeps channel Ch in active state until the requests are deasserted This handshake is necessary for channels where the requester is in an async...

Page 1062: ... Descriptions Bit Field Type Reset Description 31 0 CHNLS W 0h Set the appropriate bit to generate a software uDMA request on the corresponding uDMA channel Bit Ch 0 Does not create a uDMA request for channel Ch Bit Ch 1 Creates a uDMA request for channel Ch Writing to a bit where a uDMA channel is not implemented does not create a uDMA request for that channel 1062 Micro Direct Memory Access µDMA...

Page 1063: ...the controller data structure Read as Bit Ch 0 uDMA channel Ch responds to both burst and single requests on channel C The controller performs 2R or single bus transfers Bit Ch 1 uDMA channel Ch does not respond to single transfer requests The controller only responds to burst transfer requests and performs 2R transfers Write as Bit Ch 0 No effect Use the CLEARBURST CHNLS to set bit Ch to 0 Bit Ch...

Page 1064: ...URST Register Field Descriptions Bit Field Type Reset Description 31 0 CHNLS W 0h Set the appropriate bit to enable single transfer requests Write as Bit Ch 0 No effect Use the SETBURST CHNLS to disable single transfer requests Bit Ch 1 Enables single transfer requests on channel Ch Writing to a bit where a DMA channel is not implemented has no effect 1064 Micro Direct Memory Access µDMA SWCU117C ...

Page 1065: ...request mask status or disables the corresponding channel from generating uDMA requests Read as Bit Ch 0 External requests are enabled for channel Ch Bit Ch 1 External requests are disabled for channel Ch Write as Bit Ch 0 No effect Use the CLEARREQMASK CHNLS to enable uDMA requests Bit Ch 1 Disables uDMA burst request channel C and uDMA single request channel C input from generating uDMA requests...

Page 1066: ...QMASK Register Field Descriptions Bit Field Type Reset Description 31 0 CHNLS W 0h Set the appropriate bit to enable DMA request for the channel Write as Bit Ch 0 No effect Use the SETREQMASK CHNLS to disable channel C from generating requests Bit Ch 1 Enables channel C to generate DMA requests Writing to a bit where a DMA channel is not implemented has no effect 1066 Micro Direct Memory Access µD...

Page 1067: ...iptions Bit Field Type Reset Description 31 0 CHNLS R W 0h Returns the enable status of the channels or enables the corresponding channels Read as Bit Ch 0 Channel Ch is disabled Bit Ch 1 Channel Ch is enabled Write as Bit Ch 0 No effect Use the CLEARCHANNELEN CHNLS to disable a channel Bit Ch 1 Enables channel Ch Writing to a bit where a DMA channel is not implemented has no effect 1067 SWCU117C ...

Page 1068: ...able 12 19 CLEARCHANNELEN Register Field Descriptions Bit Field Type Reset Description 31 0 CHNLS W 0h Set the appropriate bit to disable the corresponding uDMA channel Write as Bit Ch 0 No effect Use the SETCHANNELEN CHNLS to enable uDMA channels Bit Ch 1 Disables channel Ch Writing to a bit where a uDMA channel is not implemented has no effect 1068 Micro Direct Memory Access µDMA SWCU117C Februa...

Page 1069: ...rns the channel control data structure status or selects the alternate data structure for the corresponding uDMA channel Read as Bit Ch 0 uDMA channel Ch is using the primary data structure Bit Ch 1 uDMA channel Ch is using the alternate data structure Write as Bit Ch 0 No effect Use the CLEARCHNLPRIALT CHNLS to disable a channel Bit Ch 1 Selects the alternate data structure for channel Ch Writing...

Page 1070: ...er Field Descriptions Bit Field Type Reset Description 31 0 CHNLS W 0h Clears the appropriate bit to select the primary data structure for the corresponding uDMA channel Write as Bit Ch 0 No effect Use the SETCHNLPRIALT CHNLS to select the alternate data structure Bit Ch 1 Selects the primary data structure for channel Ch Writing to a bit where a uDMA channel is not implemented has no effect 1070 ...

Page 1071: ... CHNLS R W 0h Returns the channel priority mask status or sets the channel priority to high Read as Bit Ch 0 uDMA channel Ch is using the default priority level Bit Ch 1 uDMA channel Ch is using a high priority level Write as Bit Ch 0 No effect Use the CLEARCHNLPRIORITY CHNLS to set channel Ch to the default priority level Bit Ch 1 Channel Ch uses the high priority level Writing to a bit where a u...

Page 1072: ...ster Field Descriptions Bit Field Type Reset Description 31 0 CHNLS W 0h Clear the appropriate bit to select the default priority level for the specified uDMA channel Write as Bit Ch 0 No effect Use the SETCHNLPRIORITY CHNLS to set channel Ch to the high priority level Bit Ch 1 Channel Ch uses the default priority level Writing to a bit where a uDMA channel is not implemented has no effect 1072 Mi...

Page 1073: ... Descriptions Bit Field Type Reset Description 31 1 RESERVED W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 STATUS R W 0h Returns the status of bus error flag in uDMA or clears this bit Read as 0 No bus error detected 1 Bus error detected Write as 0 No effect status of bus error flag is unchanged 1 Clears the b...

Page 1074: ...CHNLS R W 0h Reflects the uDMA done status for the given channel channel Ch It s a sticky done bit Unless cleared by writing a 1 it holds the value of 1 Read as Bit Ch 0 Request has not completed for channel Ch Bit Ch 1 Request has completed for the channel Ch Writing a 1 to individual bits would clear the corresponding bit Write as Bit Ch 0 No effect Bit Ch 1 The corresponding Ch bit is cleared a...

Page 1075: ...ne state for channel Ch is blocked from contributing to generation of combined uDMA done signal Bit Ch 1 uDMA done and active state for channel Ch is blocked from reaching to the peripherals Note that the uDMA done state for channel Ch is not blocked from contributing to generation of combined uDMA done signal Write as Bit Ch 0 Allows uDMA done and active stat to propagate to the peripherals Note ...

Page 1076: ...pic Page 13 1 General purpose Timers 1078 13 2 Block Diagram 1079 13 3 Functional Description 1079 13 4 Initialization and Configuration 1089 13 5 General purpose Timer Registers 1092 1076 Timers SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 1077: ...tions Operating modes 16 with 8 bit prescaler or 32 bit programmable one shot timer 16 with 8 bit prescaler or 32 bit programmable periodic timer Two capture compare PWM pins CCP for each 32 bit timer 24 bit input edge count or 24 bit time capture modes 24 bit PWM mode with software programmable output inversion of the PWM signal Count up or down Daisy chaining of timer modules allows a single tim...

Page 1078: ...ng up and down counters timer A and timer B two match registers two prescaler match registers two shadow registers and two load and initialization registers and their associated control functions The exact function of each GPTM is controlled by software and configured through the register interface Timer A and timer B can be used individually in which case they have a 16 bit counting range In addi...

Page 1079: ...ounters timer A and timer B are initialized to all 1s along with their corresponding load registers the GPTM Timer A Interval Load Register GPT TAILR and the GPTM Timer B Interval Load Register GPT TBILR The prescale counters are initialized to 0x00 The GPTM Timer A Prescale Register GPT TAPR and the GPTM Timer B Prescale Register GPT TBPR The GPTM Timer A Prescale Snapshot Register GPT TAPS and t...

Page 1080: ...MIS TnTOMIS bit By setting the GPT TnMR TnMIE register bit an interrupt condition can also be generated when the timer value equals the value loaded into the GPTM Timer n Match Register GPT TnMATCHR and the GPTM Timer n Prescale Match Register GPT TnPMR This interrupt has the same status masking and clearing functions as the time out interrupt but uses the match interrupt bits instead for example ...

Page 1081: ...ters Table 13 3 lists the values that are loaded into the timer registers when the timer is enabled Table 13 3 Counter Values When the Timer is Enabled in Input Edge Count Mode Register Count Down Mode Count Up Mode GPT TnR GPT TnILR 0x0 GPT TnV GPT TnILR 0x0 GPT TnPV GPT TnPR 0x0 When software writes the GPTM Control Register GPT CTL TnEN bit the timer is enabled for event capture Each input even...

Page 1082: ...er and the lower bits in the GPT TnILR register In this mode the timer is initialized to the value loaded in the GPT TnILR and the GPT TnPR registers when counting down and 0x0 when counting up The timer is capable of capturing three types of events rising edge falling edge or both The timer is placed into edge time mode by setting the GPT TnMR TnCM register bit and the type of event that the time...

Page 1083: ... edge event is detected the current count value is loaded into the GPTIMER TnR register and is held there until another rising edge is detected at which point the new count value is loaded into the GPT TnR register Figure 13 3 Input Edge time Mode Example NOTE When operating in edge time mode the counter uses a modulo 224 count if prescaler is enabled or 216 if prescaler is not enabled If there is...

Page 1084: ...If the capture mode event interrupt is enabled in the GPTM Interrupt Mask Register GPT IMR the GPTM also sets the GPTM Masked Interrupt Status Register GPT MIS CnEMIS bit NOTE The interrupt status bits are not updated unless the TnPWMIE bit is set In the PWM mode the GPT TnR and the GPT TnV registers always have the same value as do the GPT PnPS and the GPT TnPV registers The output PWM signal ass...

Page 1085: ... 13 5 shows how the CCP output operates when the TnPLO and TnMRSU bits are set and the GPT TnMATCHR register value is greater than the GPT TnILR register value Figure 13 5 CCP Output GPT TnMATCHR GPT TnILR Figure 13 6 shows how the CCP output operates when the PLO and MRSU bits are set and the GPT TnMATCHR register value is the same as the GPT TnILR register value In this situation if the PLO bit ...

Page 1086: ...s using the timer triggers Wait for trigger mode is enabled by setting the GPT TnMR TnWOT register bit When the TnWOT bit is set timer N 1 does not begin counting until the timer in the previous position in the daisy chain timer N reaches its time out event The daisy chain is configured such that GPTM1 always follows GPTM0 GPTM2 follows GPTM1 and so forth If timer A is configured as a 32 bit 16 or...

Page 1087: ...ed timers Up Count Value 0 16 bit and 32 bit one shot individual and split timers N A Down Count value ILR 16 bit and 32 bit periodic individual and split timers Up Count value 0 Down Count value ILR 16 bit and 32 bit edge count individual and split timers Up Count Value 0 Down Count value ILR 16 bit and 32 bit edge time individual and split timers Up Count Value 0 16 bit PWM Down Count value ILR ...

Page 1088: ... the supported timer modes 13 4 1 One shot and Periodic Timer Modes The GPTM is configured for one shot and periodic modes by the following sequence 1 Ensure the timer is disabled clear the GPT CTL TnEN register bit before making any changes 2 Write the GPTM Configuration Register GPT CFG with a value of 0x0000 0000 3 Configure the GPTM Timer n Mode Register GPT TnMR TnMR field a Write a value of ...

Page 1089: ...nable the timer ensure that the TnEN bit is cleared and repeat step 4 through step 9 13 4 3 Input Edge timing Mode A timer is configured to input edge timing mode by the following sequence 1 Ensure the timer is disabled the TAEN bit is cleared before making any changes 2 Write the GPTM Configuration Register GPT CFG with a value of 0x0000 0004 3 In the GPTM Timer Mode Register GPT TnMR write the T...

Page 1090: ...ing the trigger source for µDMA channels through the event fabric Each timer only produces one signal per A and B but this signal can be selected as either single or burst in the event module The DMA done interrupt is routed back to the timer module that originated the trigger The following is a procedure for configuring µDMA triggers by GPT events 1 Configure the GPT operation 2 Configure the GPT...

Page 1091: ...ster Section 13 5 1 11 30h TAMATCHR Timer A Match Register Section 13 5 1 12 34h TBMATCHR Timer B Match Register Section 13 5 1 13 38h TAPR Timer A Pre scale Section 13 5 1 14 3Ch TBPR Timer B Pre scale Section 13 5 1 15 40h TAPMR Timer A Pre scale Match Section 13 5 1 16 44h TBPMR Timer B Pre scale Match Section 13 5 1 17 48h TAR Timer A Register Section 13 5 1 18 4Ch TBR Timer B Register Section...

Page 1092: ...Type Reset Description 31 3 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 2 0 CFG R W 0h GPT Configuration 0x2 0x3 Reserved 0x5 0x7 Reserved 0h 32BIT_TIMER 32 bit timer configuration 1h 32 bit real time clock 4h 16BIT_TIMER 16 bit timer configuration Configure for two 16 bit timers Also see TAMR TAMR an...

Page 1093: ... on Time Out 6h Set CCP output pin immediately and clear on Time Out 7h Clear CCP output pin immediately and set on Time Out 12 TACINTD R W 0h One Shot Periodic Interrupt Disable 0h Time out interrupt function as normal 1h Time out interrupt are disabled 11 TAPLO R W 0h Legacy PWM operation 0h Legacy operation 1h CCP output pin is set to 1 on time out 10 TAMRSU R W 0h Timer A Match Register Update...

Page 1094: ...ot begin counting until it receives a trigger from the timer in the previous position in the daisy chain This bit must be clear for GPT Module 0 Timer A 5 TAMIE R W 0h GPT Timer A Match Interrupt Enable 0h The match interrupt is disabled for match events Additionally output triggers on match events are prevented 1h An interrupt is generated when the match value in TAMATCHR is reached in the one sh...

Page 1095: ...le on Time Out 6h Set CCP output pin immediately and clear on Time Out 7h Clear CCP output pin immediately and set on Time Out 12 TBCINTD R W 0h One Shot Periodic Interrupt Mode 0h Normal Time Out Interrupt 1h Mask Time Out Interrupt 11 TBPLO R W 0h Legacy PWM operation 0h Legacy operation 1h CCP output pin is set to 1 on time out 10 TBMRSU R W 0h Timer B Match Register Update mode This bit define...

Page 1096: ... it receives a trigger from the timer in the previous position in the daisy chain 5 TBMIE R W 0h GPT Timer B Match Interrupt Enable 0h The match interrupt is disabled for match events Additionally output triggers on match events are prevented 1h An interrupt is generated when the match value in the TBMATCHR register is reached in the one shot and periodic modes 4 TBCDIR R W 0h grep 0h DOWN The tim...

Page 1097: ...iting any other value than the reset value may result in undefined behavior 11 10 TBEVENT R W 0h GPT Timer B Event Mode 0h Positive edge 1h Negative edge 3h Both edges 9 TBSTALL R W 0h GPT Timer B Stall Enable 0h Timer B continues counting while the processor is halted by the debugger 1h Timer B freezes counting while the processor is halted by the debugger 8 TBEN R W 0h GPT Timer B Enable 0h Time...

Page 1098: ...tall Enable 0h Timer A continues counting while the processor is halted by the debugger 1h Timer A freezes counting while the processor is halted by the debugger 0 TAEN R W 0h GPT Timer A Enable 0h Timer A is disabled 1h Timer A is enabled and begins counting or the capture logic is enabled based on the CFG register 1098 Timers SWCU117C February 2015 Revised September 2015 Submit Documentation Fee...

Page 1099: ...gered 3h A timeout event for both Timer A and Timer B of GPT3 is triggered 5 4 SYNC2 W 0h Synchronize GPT Timer 2 0h No Sync GPT2 is not affected 1h A timeout event for Timer A of GPT2 is triggered 2h A timeout event for Timer B of GPT2 is triggered 3h A timeout event for both Timer A and Timer B of GPT2 is triggered 3 2 SYNC1 W 0h Synchronize GPT Timer 1 0h No Sync GPT1 is not affected 1h A timeo...

Page 1100: ...1h Enable Interrupt 15 14 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 13 DMABIM R W 0h Enabling this bit will make the RIS DMABRIS interrupt propagate to MIS DMABMIS 0h Disable Interrupt 1h Enable Interrupt 12 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than...

Page 1101: ... Disable Interrupt 1h Enable Interrupt 3 RTCIM R W 0h Enabling this bit will make the RIS RTCRIS interrupt propagate to MIS RTCMIS 0h Disable Interrupt 1h Enable Interrupt 2 CAEIM R W 0h Enabling this bit will make the RIS CAERIS interrupt propagate to MIS CAEMIS 0h Disable Interrupt 1h Enable Interrupt 1 CAMIM R W 0h Enabling this bit will make the RIS CAMRIS interrupt propagate to MIS CAMMIS 0h ...

Page 1102: ... 0 Transfer has not completed 1 Transfer has completed 12 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 11 TBMRIS R 0h GPT Timer B Match Raw Interrupt 0 The match value has not been reached 1 The match value is reached TBMR TBMIE is set and the match values in TBMATCHR and optionally TBPMR have been rea...

Page 1103: ...e RTC event has occured 2 CAERIS R 0h GPT Timer A Capture Mode Event Raw Interrupt 0 The event has not occured 1 The event has occured This interrupt asserts when the subtimer is configured in Input Edge Time mode 1 CAMRIS R 0h GPT Timer A Capture Mode Match Raw Interrupt 0 Match for Timer A has not occured 1 Match for Timer A has occurred This interrupt asserts when the values in the TAR and TAPR...

Page 1104: ...t not enabled 1 RIS DMABRIS 1 IMR DMABIM 1 12 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 11 TBMMIS R 0h 0 No interrupt or interrupt not enabled 1 RIS TBMRIS 1 IMR TBMIM 1 10 CBEMIS R 0h 0 No interrupt or interrupt not enabled 1 RIS CBERIS 1 IMR CBEIM 1 9 CBMMIS R 0h 0 No interrupt or interrupt not en...

Page 1105: ... the reset value may result in undefined behavior 13 DMABINT R W1C 0h 0 Do nothing 1 Clear RIS DMABRIS and MIS DMABMIS 12 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 11 TBMCINT R W1C 0h 0 Do nothing 1 Clear RIS TBMRIS and MIS TBMMIS 10 CBECINT R W1C 0h 0 Do nothing 1 Clear RIS CBERIS and MIS CBEMIS ...

Page 1106: ... 18 TAILR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TAILR R W FFFFFFFFh Table 13 17 TAILR Register Field Descriptions Bit Field Type Reset Description 31 0 TAILR R W FFFFFFFFh GPT Timer A Interval Load Register 1106 Timers SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 1107: ...13 19 TBILR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TBILR R W FFFFh Table 13 18 TBILR Register Field Descriptions Bit Field Type Reset Description 31 0 TBILR R W FFFFh GPT Timer B Interval Load Register 1107 SWCU117C February 2015 Revised September 2015 Timers Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 1108: ...ode this value along with TAILR determines the duty cycle of the output PWM signal When a 16 32 bit GPT is configured to one of the 32 bit modes TAMATCHR appears as a 32 bit register The upper 16 bits correspond to the contents TBMATCHR In a 16 bit mode the upper 16 bits of this register read as 0s and have no effect on the state of TBMATCHR Note This register is updated internally takes effect ba...

Page 1109: ... 31 16 are reserved in both cases Note This register is updated internally takes effect based on TBMR TBMRSU Figure 13 21 TBMATCHR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED TBMATCHR R 0h R W FFFFh Table 13 20 TBMATCHR Register Field Descriptions Bit Field Type Reset Description 31 16 RESERVED R 0h Software must not rely on the value of ...

Page 1110: ...range of the timer counter holding bits 23 16 in the 16 bit modes of the 16 32 bit GPT Figure 13 22 TAPR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED TAPSR R 0h R W 0h Table 13 21 TAPR Register Field Descriptions Bit Field Type Reset Description 31 8 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value th...

Page 1111: ...range of the timer counter holding bits 23 16 in the 16 bit modes of the 16 32 bit GPT Figure 13 23 TBPR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED TBPSR R 0h R W 0h Table 13 22 TBPR Register Field Descriptions Bit Field Type Reset Description 31 8 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value th...

Page 1112: ...9 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED TAPSMR R 0h R W 0h Table 13 23 TAPMR Register Field Descriptions Bit Field Type Reset Description 31 8 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 7 0 TAPSMR R W 0h GPT Timer A Pre scale Match In 16 bit mode this field holds bits 23 to 16 1112 ...

Page 1113: ...17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED TBPSMR R 0h R W 0h Table 13 24 TBPMR Register Field Descriptions Bit Field Type Reset Description 31 8 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 7 0 TBPSMR R W 0h GPT Timer B Pre scale Match Register In 16 bit mode this field holds bits 23 to 16 1...

Page 1114: ...ister Based on the value in the register field TAMR TAILD this register is updated with the value from TAILR register either on the next cycle or on the next timeout A read returns the current value of the Timer A Count Register in all cases except for Input Edge count and Timer modes In the Input Edge Count Mode this register contains the number of edges that have occurred In the Input Edge Time ...

Page 1115: ...Based on the value in the register field TBMR TBILD this register is updated with the value from TBILR register either on the next cycle or on the next timeout A read returns the current value of the Timer B Count Register in all cases except for Input Edge count and Timer modes In the Input Edge Count Mode this register contains the number of edges that have occurred In the Input Edge Time mode t...

Page 1116: ...ng 16 bit Timer A In the 32 bit mode Figure 13 28 TAV Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TAV R W FFFFFFFFh Table 13 27 TAV Register Field Descriptions Bit Field Type Reset Description 31 0 TAV R W FFFFFFFFh GPT Timer A Register 1116 Timers SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Texas Ins...

Page 1117: ...imer clock TIMCLK is enabled a read of a timer value will return the current count 1 Figure 13 29 TBV Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TBV R W FFFFh Table 13 28 TBV Register Field Descriptions Bit Field Type Reset Description 31 0 TBV R W FFFFh GPT Timer B Register 1117 SWCU117C February 2015 Revised September 2015 Timers Submit Documen...

Page 1118: ...count 1 Figure 13 30 RTCPD Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RTCPD R 0h R 7FFFh Table 13 29 RTCPD Register Field Descriptions Bit Field Type Reset Description 31 16 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 15 0 RTCPD R 7FFFh GPT ...

Page 1119: ...e alternate timer clock TIMCLK is enabled a read of a timer value will return the current count 1 Figure 13 31 TAPS Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED PSS R 0h R 0h Table 13 30 TAPS Register Field Descriptions Bit Field Type Reset Description 31 16 RESERVED R 0h Software must not rely on the value of a reserved Writing any other ...

Page 1120: ...e alternate timer clock TIMCLK is enabled a read of a timer value will return the current count 1 Figure 13 32 TBPS Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED PSS R 0h R 0h Table 13 31 TBPS Register Field Descriptions Bit Field Type Reset Description 31 16 RESERVED R 0h Software must not rely on the value of a reserved Writing any other ...

Page 1121: ...the current count 1 Figure 13 33 TAPV Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED PSV R 0h R 0h Table 13 32 TAPV Register Field Descriptions Bit Field Type Reset Description 31 16 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 15 0 PSV R 0h GPT ...

Page 1122: ...the current count 1 Figure 13 34 TBPV Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED PSV R 0h R 0h Table 13 33 TBPV Register Field Descriptions Bit Field Type Reset Description 31 16 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 15 0 PSV R 0h GPT ...

Page 1123: ...lue of a reserved field Writing any other value may result in undefined behavior 11 TBMDMAEN R W 0h GPT Timer B Match DMA Trigger Enable 10 CBEDMAEN R W 0h GPT Timer B Capture Event DMA Trigger Enable 9 CBMDMAEN R W 0h GPT Timer B Capture Match DMA Trigger Enable 8 TBTODMAEN R W 0h GPT Timer B Time Out DMA Trigger Enable 7 5 RESERVED R W 0h Software must not rely on the value of a reserved field W...

Page 1124: ...n regarding the GPT version Figure 13 36 VERSION Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VERSION R 400h Table 13 35 VERSION Register Field Descriptions Bit Field Type Reset Description 31 0 VERSION R 400h Timer Revision 1124 Timers SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Texas Instruments Inco...

Page 1125: ...P Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 CCP_AND_EN R W 0h Enables AND operation of the CCP outputs for timers A and B 0 PWM outputs of Timer A and Timer B are the internal generated PWM signals of the respective timers 1 PWM out...

Page 1126: ...ys on real time clock AON_RTC for the CC26xx and CC13xx platform Topic Page 14 1 Introduction 1128 14 2 Functional Specifications 1128 14 3 RTC Registers 1129 14 4 Real Time Clock Registers 1131 1126 Real Time Clock SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 1127: ...t the AON_RTC increments its counter with 1 32768 seconds each 32 kHz clock tick A subsecond increment value of 0x80 000 corresponds to 1 32768 seconds Increasing or decreasing the subsecond increments value increases or decreases the speed of the AON_RTC by the same amount Change the increment by updating the AUX_WUC RTCSUBSECINC0 and the AUX_WUC RTCSUBSECINC1 registers and then load the new sett...

Page 1128: ...hannel does not clear any pending events from that channel The only way to clear an event is by asserting the external clear signal or by writing 1 to the corresponding CHx bit in the AON_RTC EVFLAGS register 14 3 RTC Registers The RTC registers are placed in the AON domain and are clocked using 32 kHz LF clock All configuration and status registers are preserved in all power modes except for SHUT...

Page 1129: ...triggers a dummy write to the AON domain This write can ensure synchronization to the LF clock This dummy write takes 1 to 2 32 kHz LF clock cycles 1 Write to the AON_RTC SYNC register or any other register in the AON domain The write triggers an outstanding write request to be registered on the AON domain 2 Read from the AON_RTC SYNC register This read does not return until all outstanding reques...

Page 1130: ...alue Integer Part Section 14 4 1 3 Ch SUBSEC Second Counter Value Fractional Part Section 14 4 1 4 10h SUBSECINC Subseconds Increment Section 14 4 1 5 14h CHCTL Channel Configuration Section 14 4 1 6 18h CH0CMP Channel 0 Compare Value Section 14 4 1 7 1Ch CH1CMP Channel 1 Compare Value Section 14 4 1 8 20h CH2CMP Channel 2 Compare Value Section 14 4 1 9 24h CH2CMPINC Channel 2 Compare Value Auto i...

Page 1131: ...ombined event 4h Use Channel 2 delayed event in combined event 15 12 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 11 8 EV_DELAY R W 0h Number of SCLK_LF clock cycles waited before generating delayed events Common setting for all RTC channels the delayed event is delayed 0h No delay on delayed event 1h ...

Page 1132: ...al is forced to 0 1 RTC_4KHZ is enabled provided that RTC is enabled EN 1 RTC_UPD_EN R W 0h RTC_UPD is a 16 kHz signal used to sync up the radio timer The 16 kHz is SCLK_LF divided by 2 0 RTC_UPD signal is forced to 0 1 RTC_UPD signal is toggling at 16 kHz 0 EN R W 0h Enable RTC counter 0 Halted frozen 1 Running 1132 Real Time Clock SWCU117C February 2015 Revised September 2015 Submit Documentatio...

Page 1133: ...ng AUX_WUC WUEVCLR AON_RTC 15 9 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 8 CH1 R W1C 0h Channel 1 event flag set when CHCTL CH1_EN 1 and one of the following CHCTL CH1_CAPT_EN 0 and the RTC value matches or passes the CH1CMP value CHCTL CH1_CAPT_EN 1 and capture occurs An event will be scheduled to...

Page 1134: ... 14 4 SEC Register Field Descriptions Bit Field Type Reset Description 31 0 VALUE R W 0h Unsigned integer representing Real Time Clock in seconds When reading this register the content of SUBSEC VALUE is simultaneously latched A consistent reading of the combined Real Time Clock can be obtained by first reading this register then reading SUBSEC register 1134 Real Time Clock SWCU117C February 2015 ...

Page 1135: ... 4 3 2 1 0 VALUE R W 0h Table 14 5 SUBSEC Register Field Descriptions Bit Field Type Reset Description 31 0 VALUE R W 0h Unsigned integer representing Real Time Clock in fractions of a second VALUE 232 seconds at the time when SEC register was read Examples 0x0000_0000 0 0 sec 0x4000_0000 0 25 sec 0x8000_0000 0 5 sec 0xC000_0000 0 75 sec 1135 SWCU117C February 2015 Revised September 2015 Real Time...

Page 1136: ...mpensates for a SCLK_LF clock which has an offset from 32768 Hz The compensation value can be found as 238 freq where freq is SCLK_LF clock frequency in Hertz This value is added to SUBSEC VALUE on every cycle and carry of this is added to SEC VALUE To perform the addition bits 23 6 are aligned with SUBSEC VALUE bits 17 0 The remaining bits 5 0 are accumulated in a hidden 6 bit register that gener...

Page 1137: ...nel 2 17 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 16 CH2_EN R W 0h RTC Channel 2 Enable 0 Disable RTC Channel 2 1 Enable RTC Channel 2 15 10 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 9 CH1_CAPT_EN R ...

Page 1138: ...he compare value is compared against SEC VALUE 15 0 and SUBSEC VALUE 31 16 values of the Real Time Clock register A Cannel 0 event is generated when SEC VALUE 15 0 SUBSEC VALUE 31 16 is reaching or exciting the compare value Writing to this register can trigger an immediate event in case the new compare value matches a Real Time Clock value from 1 second in the past up till current Real Time Clock...

Page 1139: ...he compare value is compared against SEC VALUE 15 0 and SUBSEC VALUE 31 16 values of the Real Time Clock register A Cannel 0 event is generated when SEC VALUE 15 0 SUBSEC VALUE 31 16 is reaching or exciting the compare value Writing to this register can trigger an immediate event in case the new compare value matches a Real Time Clock value from 1 second in the past up till current Real Time Clock...

Page 1140: ... The compare value is compared against SEC VALUE 15 0 and SUBSEC VALUE 31 16 values of the Real Time Clock register A Cannel 0 event is generated when SEC VALUE 15 0 SUBSEC VALUE 31 16 is reaching or exciting the compare value Writing to this register can trigger an immediate event in case the new compare value matches a Real Time Clock value from 1 second in the past up till current Real Time Clo...

Page 1141: ...TL EVSTAT0 AON_RTC event Figure 14 11 CH2CMPINC Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VALUE R W 0h Table 14 11 CH2CMPINC Register Field Descriptions Bit Field Type Reset Description 31 0 VALUE R W 0h If CHCTL CH2_CONT_EN is set this value is added to CH2CMP VALUE on every channel 2 compare event 1141 SWCU117C February 2015 Revised September ...

Page 1142: ...L Figure 14 12 CH1CAPT Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SEC SUBSEC R 0h R 0h Table 14 12 CH1CAPT Register Field Descriptions Bit Field Type Reset Description 31 16 SEC R 0h Value of SEC VALUE bits 15 0 at capture time 15 0 SUBSEC R 0h Value of SUBSEC VALUE bits 31 16 at capture time 1142 Real Time Clock SWCU117C February 2015 Revised Se...

Page 1143: ...ion 31 1 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 WBUSY R W 0h This register will always return 0 however it will not return the value until there are no outstanding write requests between MCU and AON Note Writing to this register prior to reading will force a wait until next SCLK_LF edge This is...

Page 1144: ...pt or a reset when a time out value is reached In addition the WDT can be configured to generate an interrupt to the microcontroller MCU on its first time out and to generate a reset signal on its second time out Topic Page 15 1 WDT Introduction 1146 15 2 WDT Functional Description 1146 15 3 WDT Initialization and Configuration 1147 15 4 Watchdog Timer Registers 1148 1144 Watchdog Timer SWCU117C F...

Page 1145: ...nt the WDT configuration from being inadvertently altered by software the write access to the watchdog registers can be locked by writing the WDT LOCK register to any value To unlock the WDT write the WDT LOCK register to the value 0x1ACC E551 If the timer counts down to its zero state again before the first time out interrupt is cleared and the reset signal has been enabled by setting the WDT CTL...

Page 1146: ...nabled The WDT is running off the infrastructure clock sourced by the MCU PRCM module The WDT is then configured using the following sequence 1 Load the WDT LOAD register with the desired timer load value 2 If the watchdog is configured to trigger system resets set the WDT CTL RESEN bit 3 Set the WDT CTL INTEN register bit to enable the WDT 4 Lock the WDT module using the WDT LOCK register 1146 Wa...

Page 1147: ...er Name Section 0h LOAD Configuration Section 15 4 1 1 4h VALUE Current Count Value Section 15 4 1 2 8h CTL Control Section 15 4 1 3 Ch ICR Interrupt Clear Section 15 4 1 4 10h RIS Raw Interrupt Status Section 15 4 1 5 14h MIS Masked Interrupt Status Section 15 4 1 6 418h TEST Test Mode Section 15 4 1 7 41Ch INT_CAUS Interrupt Cause Test Mode Section 15 4 1 8 C00h LOCK Lock Section 15 4 1 9 1147 S...

Page 1148: ... Register Field Descriptions Bit Field Type Reset Description 31 0 WDTLOAD R W FFFFFFFFh This register is the 32 bit interval value used by the 32 bit counter When this register is written the value is immediately loaded and the counter is restarted to count down from the new value If this register is loaded with 0x0000 0000 an interrupt is immediately generated 1148 Watchdog Timer SWCU117C Februa...

Page 1149: ...8 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WDTVALUE R FFFFFFFFh Table 15 3 VALUE Register Field Descriptions Bit Field Type Reset Description 31 0 WDTVALUE R FFFFFFFFh This register contains the current count value of the timer 1149 SWCU117C February 2015 Revised September 2015 Watchdog Timer Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporat...

Page 1150: ...ay result in undefined behavior 2 INTTYPE R W 0h WDT Interrupt Type 0 WDT interrupt is a standard interrupt 1 WDT interrupt is a non maskable interrupt 0h Maskable interrupt 1h Non maskable interrupt 1 RESEN R W 0h WDT Reset Enable Defines the function of the WDT reset source see PRCM WARMRESET WDT_STAT if enabled 0 Disabled 1 Enable the Watchdog reset output 0h Reset output Disabled 1h Reset outp...

Page 1151: ...11 10 9 8 7 6 5 4 3 2 1 0 WDTICR W 0h Table 15 5 ICR Register Field Descriptions Bit Field Type Reset Description 31 0 WDTICR W 0h This register is the interrupt clear register A write of any value to this register clears the WDT interrupt and reloads the 32 bit counter from the LOAD register 1151 SWCU117C February 2015 Revised September 2015 Watchdog Timer Submit Documentation Feedback Copyright ...

Page 1152: ...iptions Bit Field Type Reset Description 31 1 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 WDTRIS R 0h This register is the raw interrupt status register WDT interrupt events can be monitored via this register if the controller interrupt is masked Value Description 0 The WDT has not timed out 1 A WDT...

Page 1153: ...e Reset Description 31 1 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 WDTMIS R 0h This register is the masked interrupt status register The value of this register is the logical AND of the raw interrupt bit and the WDT interrupt enable bit CTL INTEN Value Description 0 The WDT has not timed out or is...

Page 1154: ... 8 STALL R W 0h WDT Stall Enable 0 The WDT timer continues counting if the CPU is stopped with a debugger 1 If the CPU is stopped with a debugger the WDT stops counting Once the CPU is restarted the WDT resumes counting 0h Disable STALL 1h Enable STALL 7 1 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0...

Page 1155: ...0h R 0h Table 15 9 INT_CAUS Register Field Descriptions Bit Field Type Reset Description 31 2 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 1 CAUSE_RESET R 0h Indicates that the cause of an interrupt was a reset generated but blocked due to TEST TEST_EN only possible when TEST TEST_EN is set 0 CAUSE_INT...

Page 1156: ...Descriptions Bit Field Type Reset Description 31 0 WDTLOCK R W 0h WDT Lock A write of the value 0x1ACC E551 unlocks the watchdog registers for write access A write of any other value reapplies the lock preventing any register updates NOTE TEST TEST_EN bit is not lockable A read of this register returns the following values 0x0000 0000 Unlocked 0x0000 0001 Locked 1156 Watchdog Timer SWCU117C Februa...

Page 1157: ...ically secure random data Typical applications might be but are not limited to the following Generation of cryptographic key material Generation of initialization vectors Generation of cookies and nonces Statistical sampling Re try timers in communication protocols Noise generation Topic Page 16 1 Overview 1159 16 2 Block Diagram 1159 16 3 TRNG Software Reset 1160 16 4 Interrupt Requests 1160 16 5...

Page 1158: ...ciation with a nonlinear entropic hasher The random numbers are accessible to the applications in a 64 bit read only register Once the register is read the TRNG immediately generates a new value which is then shifted into the output register when ready If the ready value is not read within a maximum time out window the TRNG is set into idle mode The TRNG provides a built in self test that checks t...

Page 1159: ...e software reset must be completed before doing any TRNG operations There is also a reset possibility from the PRCM module by writing a 1 to the PRCM RESETSECDMA TRNG register which is automatically reset This reset enables the asynchronous reset input to the module and not the internal reset thus from a module perspective this is the same as doing HW reset SW must ensure that no access is done to...

Page 1160: ...lar intervals on the order of seconds If a bit is set there the TRNG ALARMSTOP register must also be checked to see if a FRO was shut down due to multiple alarm events if none were shut down the TRNG ALARMMASK register can be cleared to get rid of the spurious alarm events If one or more FROs were shut down software can modify the delay selection of those FROs in the TRNG FRODETUNE register in an ...

Page 1161: ...is bit is already set to 0 When the value is updated the corresponding FRO must be enabled again For the second option the de tune probably had no effect or the FRO is not oscillating This state must be stored so the corresponding bit in the TRNG FROEN register is kept in off state to eliminate new alarm triggers caused by the particular FRO 16 5 3 TRNG Entropy Entropy is defined as a result of Ho...

Page 1162: ...ait for SW completion by polling TRNG SWRESET RESET Select the number of clock input cycles of the FRO s between two samples TRNG CFG0 SMPL_DIV Select the number of samples taken to gather enough entropy in the FROs TRNG CTL STARTUP_CYCLES of the module and to generate the first random value Select the minimum number of samples taken regenerate entropy in the TRNG CFG0 MIN_REFILL_CYCLES FROs of th...

Page 1163: ...further locking detune the particular FRO s which had the alarm TRNG FRODETUNE FRO_MASK 0x Re enable the shut down FROs TRNG FROEN FRO_MASK 0x Clear the shutdown overflow event in the status register by writing to the acknowledge register TRNG IRQFLAGCLR SHUTDOWN_OVF 0x1 Modify the delay selection in an attempt to prevent further locking detune the particular FRO s which had the alarm TRNG FRODETU...

Page 1164: ... status register by writing to the acknowledge register TRNG IRQFLAGCLR SHUTDOWN_OVF 0x1 Exit ISR TRNG Low level Programing Guide www ti com 16 6 1 3 2 Interrupt Mode The Interrupt Mode section covers the event servicing of the module Only the unmonitored mode is covered Table 16 4 lists the TRNG interrupt mode steps while Figure 16 3 shows the interrupt service routine flow Table 16 4 TRNG Interr...

Page 1165: ...guration 0 Section 16 7 1 7 1Ch ALARMCNT Alarm Control Section 16 7 1 8 20h FROEN FRO Enable Section 16 7 1 9 24h FRODETUNE FRO De tune Bit Section 16 7 1 10 28h ALARMMASK Alarm Event Section 16 7 1 11 2Ch ALARMSTOP Alarm Shutdown Section 16 7 1 12 30h LFSR0 LFSR Readout Value Section 16 7 1 13 34h LFSR1 LFSR Readout Value Section 16 7 1 14 38h LFSR2 LFSR Readout Value Section 16 7 1 15 78h HWOPT ...

Page 1166: ...30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VALUE_31_0 R 0h Table 16 6 OUT0 Register Field Descriptions Bit Field Type Reset Description 31 0 VALUE_31_0 R 0h LSW of 64 bit random value New value ready when IRQFLAGSTAT RDY 1 1166 Random Number Generator SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Texas Instruments...

Page 1167: ...0 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VALUE_63_32 R 0h Table 16 7 OUT1 Register Field Descriptions Bit Field Type Reset Description 31 0 VALUE_63_32 R 0h MSW of 64 bit random value New value ready when IRQFLAGSTAT RDY 1 1167 SWCU117C February 2015 Revised September 2015 Random Number Generator Submit Documentation Feedback Copyright 2015 Texas Instrument...

Page 1168: ... idle and can be shut down 30 2 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 1 SHUTDOWN_OVF R 0h 1 The number of FROs shut down i e the number of 1 bits in the ALARMSTOP register has exceeded the threshold set by ALARMCNT SHUTDOWN_THR Writing 1 to IRQFLAGCLR SHUTDOWN_OVF clears this bit to 0 again 0 RD...

Page 1169: ... 0h R W 0h Table 16 9 IRQFLAGMASK Register Field Descriptions Bit Field Type Reset Description 31 2 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 1 SHUTDOWN_OVF R W 0h 1 Allow IRQFLAGSTAT SHUTDOWN_OVF to activate the interrupt from this module 0 RDY R W 0h 1 Allow IRQFLAGSTAT RDY to activate the interru...

Page 1170: ... 6 5 4 3 2 1 0 RESERVED SHUTDOWN_ RDY OVF W 0h W 0h W 0h Table 16 10 IRQFLAGCLR Register Field Descriptions Bit Field Type Reset Description 31 2 RESERVED W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 1 SHUTDOWN_OVF W 0h 1 Clear IRQFLAGSTAT SHUTDOWN_OVF 0 RDY W 0h 1 Clear IRQFLAGSTAT RDY 1170 Random Number Gener...

Page 1171: ...y result in undefined behavior 10 TRNG_EN R W 0h 0 Forces all TRNG logic back into the idle state immediately 1 Starts TRNG gathering entropy from the FROs for the number of samples determined by STARTUP_CYCLES 9 3 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 2 NO_LFSR_FB R W 0h 1 Remove XNOR feedback ...

Page 1172: ...aken from the FROs Default value 0 indicates that samples are taken every clock cycle maximum value 0xF takes one sample every 16 clock cycles This field must be set to a value such that the slowest FRO even under worst case conditions has a cycle time less than twice the sample period This field can only be modified while CTL TRNG_EN is 0 7 0 MIN_REFILL_CYCLES R W 0h This field determines the min...

Page 1173: ...23 21 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 20 16 SHUTDOWN_THR R W 0h Threshold setting for generating IRQFLAGSTAT SHUTDOWN_OVF interrupt The interrupt is triggered when SHUTDOWN_CNT value exceeds this bit field 15 8 RESERVED R 0h Software must not rely on the value of a reserved Writing any oth...

Page 1174: ...t not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 23 0 FRO_MASK R W FFFFFFh Enable bits for the individual FROs A 1 in bit n enables FRO n Default state is all 1 s to enable all FROs after power up Note that they are not actually started up before the CTL TRNG_EN bit is set to 1 Bits are automatically forced to 0 here and cannot be ...

Page 1175: ...Description 31 24 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 23 0 FRO_MASK R W 0h De tune bits for the individual FROs A 1 in bit n lets FRO n run approximately 5 faster The value of one of these bits may only be changed while the corresponding FRO is turned off by temporarily writing a 0 in the corr...

Page 1176: ... 0h Table 16 16 ALARMMASK Register Field Descriptions Bit Field Type Reset Description 31 24 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 23 0 FRO_MASK R W 0h Logging bits for the alarm events of individual FROs A 1 in bit n indicates FRO n experienced an alarm event 1176 Random Number Generator SWCU...

Page 1177: ...ld Type Reset Description 31 24 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 23 0 FRO_FLAGS R W 0h Logging bits for the alarm events of individual FROs A 1 in bit n indicates FRO n experienced more than one alarm event in quick succession and has been turned off A 1 in this field forces the correspondi...

Page 1178: ...1 10 9 8 7 6 5 4 3 2 1 0 LFSR_31_0 R W 0h Table 16 18 LFSR0 Register Field Descriptions Bit Field Type Reset Description 31 0 LFSR_31_0 R W 0h Bits 31 0 of the main entropy accumulation LFSR Register can only be accessed when CTL TEST_MODE 1 Register contents will be cleared to zero before access is enabled 1178 Random Number Generator SWCU117C February 2015 Revised September 2015 Submit Documenta...

Page 1179: ... 10 9 8 7 6 5 4 3 2 1 0 LFSR_63_32 R W 0h Table 16 19 LFSR1 Register Field Descriptions Bit Field Type Reset Description 31 0 LFSR_63_32 R W 0h Bits 63 32 of the main entropy accumulation LFSR Register can only be accessed when CTL TEST_MODE 1 Register contents will be cleared to zero before access is enabled 1179 SWCU117C February 2015 Revised September 2015 Random Number Generator Submit Documen...

Page 1180: ...r Field Descriptions Bit Field Type Reset Description 31 17 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 16 0 LFSR_80_64 R W 0h Bits 80 64 of the main entropy accumulation LFSR Register can only be accessed when CTL TEST_MODE 1 Register contents will be cleared to zero before access is enabled 1180 R...

Page 1181: ...ster Field Descriptions Bit Field Type Reset Description 31 12 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 11 6 NR_OF_FROS R 18h Number of FROs implemented in this TRNG value 24 decimal 5 0 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may...

Page 1182: ...re must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 27 24 HW_MAJOR_VER R 2h 4 bits binary encoding of the major hardware revision number 23 20 HW_MINOR_VER R 0h 4 bits binary encoding of the minor hardware revision number 19 16 HW_PATCH_LVL R 0h 4 bits binary encoding of the hardware patch level initial release will carry value ...

Page 1183: ...0h R 0h Table 16 23 IRQSTATMASK Register Field Descriptions Bit Field Type Reset Description 31 2 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 1 SHUTDOWN_OVF R 0h Shutdown Overflow result of IRQFLAGSTAT SHUTDOWN_OVF AND ed with IRQFLAGMASK SHUTDOWN_OVF 0 RDY R 0h New random value available result of IR...

Page 1184: ...0 9 8 7 6 5 4 3 2 1 0 RESERVED REV R 0h R 20h Table 16 24 HWVER1 Register Field Descriptions Bit Field Type Reset Description 31 8 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 7 0 REV R 20h The revision number of this module is Rev 2 0 1184 Random Number Generator SWCU117C February 2015 Revised Septemb...

Page 1185: ...19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RDY R W 0h Table 16 25 IRQSET Register Field Descriptions Bit Field Type Reset Description 31 0 RDY R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 1185 SWCU117C February 2015 Revised September 2015 Random Number Generator Submit Documentation Feedback Copyright ...

Page 1186: ...3 2 1 0 RESERVED RESET R 0h R W 0h Table 16 26 SWRESET Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 RESET R W 0h Write 1 to soft reset reset will be low for 4 5 clock cycles Poll to 0 for reset to be completed 1186 Random Number Genera...

Page 1187: ... 7 6 5 4 3 2 1 0 RESERVED STAT R 0h R 0h Table 16 27 IRQSTAT Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 STAT R 0h TRNG Interrupt status OR ed version of IRQFLAGSTAT SHUTDOWN_OVF and IRQFLAGSTAT RDY 1187 SWCU117C February 2015 Revised...

Page 1188: ... CC13xx platform Topic Page 17 1 Introduction 1190 17 2 Memory Mapping 1192 17 3 I O Mapping 1194 17 4 Modules 1195 17 5 Power Management 1214 17 6 Clock Management 1217 17 7 AUX Sensor Controller Registers 1219 1188 AUX Sensor Controller with Digital and Analog Peripherals SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 1189: ... oscillator calibration Frequency measurements to compensate RTC frequency Control of GPIO pins including bit banged SPI I2C and UART Capacitive sensing and filtering of measurement results to reduce load on the system CPU Comparator monitoring Software defined wake up of the MCU domain based on for example inputs from sensors NOTE To ease development of program code running on the sensor controll...

Page 1190: ... bit system CPU and the 16 bit sensor controller All peripherals other than the ADI and DDI modules only implement 16 bit registers The sensor controller always wins arbitration when the system CPU accesses the same peripheral simultaneously ensuring minimum execution time for the sensor controller The sensor controller uses two or three clock cycles per instruction dependent on operand size used ...

Page 1191: ...Description Start Address AUX_ARBITER alias of frequently used Arbitrator 1 0x 400C 0000 registers AUX_AIODIOCTRL0 IO Bank 0 0x 400C 1000 AUX_AIODIOCTRL1 IO Bank 1 0x 400C 2000 AUX_TDC Time to digital converter 0x 400C 4000 AUX_EVCTRL Event control 0x 400C 5000 AUX_WUC Wake up control 0x 400C 6000 AUX_TIMER Timers 0x 400C 7000 AUX_SEMAPH Semaphore 0x 400C 8000 AUX_ANAIF Analog control 0x 400C 9000...

Page 1192: ... SMPH3 0x400C 8000 0x0C 29 AUX_SMPH SMPH4 0x400C 8000 0x10 30 AUX_SMPH SMPH5 0x400C 8000 0x14 31 AUX_SMPH SMPH6 0x400C 8000 0x18 32 AUX_SMPH SMPH7 0x400C 8000 0x1C 33 AUX_SMPH AUTOTAKE 0x400C 8000 0x20 34 AUX_WUC MODCLKEN0 0x400C 6000 0x00 35 AUX_WUC PWROFFREQ 0x400C 6000 0x04 36 AUX_WUC PWRDWNREQ 0x400C 6000 0x08 37 AUX_EVCTL VECCFG0 0x400C 5000 0x00 38 AUX_EVCTL VECCFG1 0x400C 5000 0x04 39 AUX_A...

Page 1193: ...0C B000 0x18 76 AUX_ADI SET811 3 2 0x400C B000 0x1A 77 AUX_ADI SET1215 1 0 0x400C B000 0x1C 78 AUX_ADI SET1215 3 2 0x400C B000 0x1E 79 AUX_ADI CLR03 1 0 0x400C B000 0x20 80 AUX_ADI CLR03 3 2 0x400C B000 0x22 81 AUX_ADI CLR47 1 0 0x400C B000 0x24 82 AUX_ADI CLR47 3 2 0x400C B000 0x26 83 AUX_ADI CLR811 1 0 0x400C B000 0x28 84 AUX_ADI CLR811 3 2 0x400C B000 0x2A 85 AUX_ADI CLR1215 1 0 0x400C B000 0x2...

Page 1194: ...sters implement the traditional zero Z negative N carry C and overflow V status indications A dedicated loop count and loop address register support highly efficient looping instructions The program counter PC is used to address the instruction memory and the CPU has a built in 3 level stack to store the PC during subroutine calls Most of the sensor controller registers are memory mapped and are a...

Page 1195: ...tions describes all instructions Each table shows the instruction the mnemonic an informal and a formal description of the operation performed and how the flags zero Z negative N carry C and overflow V are updated The operation description is described as right associative 17 4 1 5 1 Memory Access The sensor controller load and store ld and st instructions allow reading and writing data from or to...

Page 1196: ...t and output instructions individual bits in the I O ports can be directly set cleared and tested using single instructions This allows very fast and code efficient implementation of common bit manipulation functions without requiring the use of internal registers Table 17 5 lists the input and output instructions available Table 17 5 Input and Output Instructions 1 Syntax Description Operation Z ...

Page 1197: ...Rd x x 0 0 1 Flags Zero Z Negative N Carry C and Overflow V For instructions using an immediate operand an 8 bit immediate is embedded in the instruction word Using the prefix instruction the immediate can be extended to a full 16 bit The arithmetic add and cmp instructions treat the 8 bit immediate as a signed quantity in other words in the range of 128 to 127 sign extending it to full register w...

Page 1198: ...tructions For all operations the zero Z flag is set if the result is 0 The negative N flag is set equal to the most significant bit of the result The carry C flag is set according to the last bit shifted out whether through the most significant or the least significant bit The overflow V flag is always cleared 17 4 1 5 6 Flow Control The sensor controller has support for several powerful flow cont...

Page 1199: ...instruction and an 8 bit signed displacement in the range 128 to 127 embedded in the instruction word itself When the condition tested is false instruction fetching continues sequentially In addition to the above mentioned conditional branches an unconditional relative branch bra rel also exists The branch event instructions bev0 and bev1 perform conditional branching depending on event inputs pro...

Page 1200: ...al register loopend The number of loop iterations as determined by either the content of the R1 register or a 3 bit immediate in the instruction word is stored in an internal register loopcount The loop control logic is armed Instruction execution continues unaffected until the address of the next instruction to be executed matches the address stored in loopend When this happens loopcount is decre...

Page 1201: ...embed a 3 bit event ID in the instruction word directly supporting eight external events More can be selected using the prefix instruction The sleep instruction also stops the clock until a dedicated wake up event is asserted When the wake up event is asserted to the configured polarity high or low the clock starts again and program execution continues at an address corresponding to the value on a...

Page 1202: ...r instructions that would normally do so as the uppermost bits are provided by the prefix register 17 4 1 5 9 Reset Following reset execution starts at an address corresponding to the value of the same vector input as used for the sleep instruction This execution enables a usage model where the sensor controller is completely disabled powered down and once activated execution starts directly at an...

Page 1203: ...le stepping first suspend the sensor controller by setting the AUX_SCE CTL SUSPEND register Single stepping is done by writing 1 to the AUX_SCE CTL SINGLE_STEP register One instruction is executed per write Normal program execution is done by clearing the AUX_SCE CTL SUSPEND register Full system real time operation can be debugged by setting the AUX_SCE CTL DBG_FREEZE_EN bit This ensures that the ...

Page 1204: ...as a wake up event vector in the AON_EVENT AUXWUSEL register When an RTC compare event occurs on channel 2 this causes AUX to be powered on in active mode However the sensor controller does not start to execute code until one of the four wake up event vectors described in Section 17 4 2 1 2 Sensor Controller Events are triggered so RTC channel 2 must also be setup as a wake up vector to the sensor...

Page 1205: ... example be set by the sensor controller to wake up the MCU domain and trigger an interrupt in the system CPU The system CPU can also write these events which allows for a communication and synchronization protocol between the sensor controller and the system CPU The software defined events are set by writing to the AUX_EVCTL SWEVSET register and are cleared by writing to AUX_EVCTL EVTOAONFLAGSCLR...

Page 1206: ...ng an RTC capture In addition these events can be routed further from the AON event fabric to the MCU event fabric as AON programmable events see Section 4 3 Event Fabric for more information Table 17 15 lists the events routed to the AON event fabric Table 17 15 Events Routed to the AON Event Fabric Name Number Description SWEV0 0 Software defined event 0 SWEV1 1 Software defined event 1 SWEV2 2 ...

Page 1207: ... a number of inputs as their tick source and can be clocked on either the AUX power domain system clock or an external event To set up a timer the tick source must first be configured in the AUX_TIMER TnCFG MODE register Setting the mode to CLK makes the timer tick at the AUX system clock Configuring it in tick mode makes the timer use the event input configured in the TICK_SRC field as its tick w...

Page 1208: ...he above configured clock sources must be enabled by writing to the AUX_WUC TDCCLKCTL REQ and the AUX_WUC REFCLKCTL REQ register The corresponding ACK bit is set when the clock source has started and is ready to use NOTE If there are any high speed clocks enabled for the TDC the system is not able to go to standby mode because the oscillator is still requesting resources from the supply system 17 ...

Page 1209: ... the next edge of the start signal This mode is recommended for measuring periodic signals such as clock inputs Once a measurement is done the counter value can be read out from the AUX_TDC RESULT register 17 4 5 Semaphores The AUX power domain has eight hardware semaphores that can be used for synchronization between the sensor controller and system CPU These are taken by reading the AUX_SMPH SMP...

Page 1210: ...eripherals 17 4 8 ADC 17 4 8 1 Introduction The ADC is a 12 bit general purpose successive approximation type SAR ADC that can sample up to 200 kS s using up to eight different input channels with a number of start triggers The input stage consists of a switched capacitor stage where the input voltage is sampled and held before the conversion is done The ADC can operate in both synchronous and asy...

Page 1211: ...he start trigger occurs to perform a conversion 17 4 8 4 Input Signal Scaling Disabling input scaling is configured through the ADI_4_AUX ADC1 SCALE_DIS register and can be used to increase the ADC step resolution if the input signal is always below VDDR Use this setting with caution as any input voltage above VDDR might damage the ADC permanently 17 4 8 5 ADC Enable Enabling the ADC analog core i...

Page 1212: ... the system CPU These are edge triggered and must be cleared by software 17 4 8 11 DMA Usage The ADC can be used together with DMA to allow data transfer from the ADC FIFO to any other memory mapped location without CPU involvement To configure the ADC to trigger a DMA transfer the corresponding DMA channel 7 must be set up in the µDMA module After configuring the µDMA configuration of a DMA trigg...

Page 1213: ... generally independent from similar requests in the MCU voltage domain By configuring the AUX_WUC both the sensor controller and the system CPU can request the following AUX_PD power modes AUX clock source and frequency AUX peripheral clocks To access a peripheral in AUX other than for AUX_WUC and AUX_EVCTL the clock must be enabled in the AUX_WUC MODCLKEN0 register or the AUX_WUC MODCLKEN1 regist...

Page 1214: ... 2 Wait for AUX_WUC PWRDWNACK 1 3 Write AUX_WUC PWRDWNREQ 0 4 Wait until AUX_WUC PWRDWNACK 0 When the PWRDWNACK register goes low the AUX starts receiving the power down clock instead of the active mode clock By default the entire AUX domain has full retention in the power down mode TI recommends using this low power mode to save execution time by not having to reconfigure AUX every time it is use...

Page 1215: ...read as 0 RTC channel 2 and software events from AON have dedicated clear bits Any wake up I O events on pins routed to the AUX are cleared by writing to the AUX_WUC WUEVCLR AON_PROG_WU register A use case that requires special handling is when both an I O and RTC channel 2 are used as AUX wake up sources and event vectors for the sensor controller If the RTC event occurs while the sensor controll...

Page 1216: ...ter this handshake AUX is ensured to always use the low frequency clock in active mode Active mode is not recommended for normal use because the system CPU experiences very long wait times to access modules in AUX_PD such as the oscillators 17 6 1 2 Power Down When AUX is in power down mode the domain receives a power down clock instead which is configured in the AON_WUC AUXCLK PWR_DWN_SRC registe...

Page 1217: ...o always run on the low frequency clock when switching between power modes See the clock section in Section 17 5 2 1 Active Mode for more details 17 6 3 Peripheral Clocks The AUX can request a number of clocks for the peripherals in the AUX domain Enabling clocks for most peripherals is done through the AUX_WUC MODCLKEN0 register After enabling the clock for a peripheral it is ready to be accessed...

Page 1218: ... 0 Section 17 7 1 1 1h MUX1 Multiplexer 1 Section 17 7 1 2 2h MUX2 Multiplexer 2 Section 17 7 1 3 3h MUX3 Multiplexer 3 Section 17 7 1 4 4h ISRC Current Source Section 17 7 1 5 5h COMP Comparator Section 17 7 1 6 7h MUX4 Multiplexer 4 Section 17 7 1 7 8h ADC0 ADC Control 0 Section 17 7 1 8 9h ADC1 ADC Control 1 Section 17 7 1 9 Ah ADCREF0 ADC Reference 0 Section 17 7 1 10 Bh ADCREF1 ADC Reference ...

Page 1219: ... COMPA_IN COMPA_REF R W 0h R W 0h Table 17 22 MUX0 Register Field Descriptions Bit Field Type Reset Description 7 4 COMPA_IN R W 0h Internal Only to be used through TI provided API 3 0 COMPA_REF R W 0h Internal Only to be used through TI provided API 1219 SWCU117C February 2015 Revised September 2015 AUX Sensor Controller with Digital and Analog Peripherals Submit Documentation Feedback Copyright ...

Page 1220: ...I Figure 17 4 MUX1 Register 7 6 5 4 3 2 1 0 COMPA_IN R W 0h Table 17 23 MUX1 Register Field Descriptions Bit Field Type Reset Description 7 0 COMPA_IN R W 0h Internal Only to be used through TI provided API 1220 AUX Sensor Controller with Digital and Analog Peripherals SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 1221: ...CCOMPB_IN COMPB_REF R W 0h R W 0h Table 17 24 MUX2 Register Field Descriptions Bit Field Type Reset Description 7 3 ADCCOMPB_IN R W 0h Internal Only to be used through TI provided API 2 0 COMPB_REF R W 0h Internal Only to be used through TI provided API 1221 SWCU117C February 2015 Revised September 2015 AUX Sensor Controller with Digital and Analog Peripherals Submit Documentation Feedback Copyrig...

Page 1222: ...igure 17 6 MUX3 Register 7 6 5 4 3 2 1 0 ADCCOMPB_IN R W 0h Table 17 25 MUX3 Register Field Descriptions Bit Field Type Reset Description 7 0 ADCCOMPB_IN R W 0h Internal Only to be used through TI provided API 1222 AUX Sensor Controller with Digital and Analog Peripherals SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 1223: ...just current from current source Output currents may be combined to get desired total current 0h No current connected 1h 0P25U 0 25 µA 2h 0P5U 0 5 µA 4h 1P0U 1 0 µA 8h 2P0U 2 0 µA 10h 4P5U 4 5 µA 20h 11P75U 11 75 µA 1 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 EN R W 0h Current source enable 1223...

Page 1224: ...ference for cap sense 6 COMPA_REF_CURR_EN R W 0h Enables 2 µA IPTAT current from ISRC to COMPA reference node Requires ISRC EN 1 Used with COMPA_REF_RES_EN to generate voltage reference for cap sense 5 3 COMPB_TRIM R W 0h COMPB voltage reference trim temperature coded 0h No reference division 1h Divide reference by 2 3h Divide reference by 3 7h Divide reference by 4 2 COMPB_EN R W 0h Comparator B ...

Page 1225: ... Figure 17 9 MUX4 Register 7 6 5 4 3 2 1 0 COMPA_REF R W 0h Table 17 28 MUX4 Register Field Descriptions Bit Field Type Reset Description 7 0 COMPA_REF R W 0h Internal Only to be used through TI provided API 1225 SWCU117C February 2015 Revised September 2015 AUX Sensor Controller with Digital and Analog Peripherals Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 1226: ...xternally driven signal 6 3 SMPL_CYCLE_EXP R W 0h Controls the sampling duration before conversion when the ADC is operated in synchronous mode SMPL_MODE 0 The setting has no effect in asynchronous mode The sampling duration is given as 2SMPL_CYCLE_EXP 1 6 µs 3h 2P7_US 16x 6 MHz clock periods 2 7 µs 4h 5P3_US 32x 6 MHz clock periods 5 3 µs 5h 10P6_US 64x 6 MHz clock periods 10 6 µs 6h 21P3_US 128x...

Page 1227: ...ster Field Descriptions Bit Field Type Reset Description 7 1 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 SCALE_DIS R W 0h Internal Only to be used through TI provided API 1227 SWCU117C February 2015 Revised September 2015 AUX Sensor Controller with Digital and Analog Peripherals Submit Documentati...

Page 1228: ... R W 0h Keep ADCREF powered up in IDLE state when ADC0 SMPL_MODE 0 Set to 1 if ADC0 SMPL_CYCLE_EXP is less than 6 21 3 µs sampling time 5 IOMUX R W 0h Internal Only to be used through TI provided API 4 EXT R W 0h Internal Only to be used through TI provided API 3 SRC R W 0h ADC reference source 0 Fixed reference 4 3 V 1 Relative reference VDDS 2 1 RESERVED R W 0h Software must not rely on the valu...

Page 1229: ... W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 5 0 VTRIM R W 0h Trim output voltage of ADC fixed reference 64 steps 2s complement Applies only for ADCREF0 SRC 0 Examples 0x00 nominal voltage 1 43 V 0x01 nominal 0 4 1 435 V 0x3F nominal 0 4 1 425 V 0x1F maximum voltage 1 6 V 0x20 minimum voltage 1 3 V 1229 SWCU11...

Page 1230: ...on 17 7 2 1 4h IOMODE Input Output Mode Section 17 7 2 2 8h GPIODIN General Purpose Input Output Data In Section 17 7 2 3 Ch GPIODOUTSET General Purpose Input Output Data Out Set Section 17 7 2 4 10h GPIODOUTCLR General Purpose Input Output Data Out Clear Section 17 7 2 5 14h GPIODOUTTGL General Purpose Input Output Data Out Toggle Section 17 7 2 6 18h GPIODIE General Purpose Input Output Input En...

Page 1231: ...5 4 3 2 1 0 RESERVED IO7_0 R 0h R W 0h Table 17 34 GPIODOUT Register Field Descriptions Bit Field Type Reset Description 31 8 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 7 0 IO7_0 R W 0h Output values for AUXIO0 through AUXIO7 for AIODIO0 or AUXIO8 through AUXIO15 for AIODIO1 1231 SWCU117C February 20...

Page 1232: ... output with GPIODIE bit 6 0 2h Open drain The pin is driven low when the corresponding GPIODOUT bit is 0 and otherwise tri stated or pulled depending on the corresponding IOC configuration 3h Open source The pin is driven high when the corresponding GPIODOUT bit is 1 and otherwise tri stated or pulled depending on the corresponding IOC configuration 11 10 IO5 R W 0h Selects mode for AUXIO5 for AI...

Page 1233: ...rwise tri stated or pulled depending on the corresponding IOC configuration 3 2 IO1 R W 0h Selects mode for AUXIO1 for AIODIO0 or AUXIO9 for AIODIO1 0h Output 1h Digital input with GPIODIE bit 1 1 Analog input output with GPIODIE bit 1 0 2h Open drain The pin is driven low when the corresponding GPIODOUT bit is 0 and otherwise tri stated or pulled depending on the corresponding IOC configuration 3...

Page 1234: ...h R 0h Table 17 36 GPIODIN Register Field Descriptions Bit Field Type Reset Description 31 8 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 7 0 IO7_0 R 0h Input values for AUXIO0 through AUXIO7 for AIODIO0 or AUXIO8 through AUXIO15 for AIODIO1 1234 AUX Sensor Controller with Digital and Analog Peripheral...

Page 1235: ... RESERVED IO7_0 R 0h R W 0h Table 17 37 GPIODOUTSET Register Field Descriptions Bit Field Type Reset Description 31 8 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 7 0 IO7_0 R W 0h Writing 1 to one or more bit positions sets the corresponding bit or bits in GPIODOUT Read value is 0x00 1235 SWCU117C Febr...

Page 1236: ...0 RESERVED IO7_0 R 0h R W 0h Table 17 38 GPIODOUTCLR Register Field Descriptions Bit Field Type Reset Description 31 8 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 7 0 IO7_0 R W 0h Writing 1 to one or more bit positions clears the corresponding bit or bits in GPIODOUT Read value is 0x00 1236 AUX Sensor...

Page 1237: ...0 RESERVED IO7_0 R 0h R W 0h Table 17 39 GPIODOUTTGL Register Field Descriptions Bit Field Type Reset Description 31 8 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 7 0 IO7_0 R W 0h Writing 1 to one or more bit positions toggles the corresponding bit or bits in GPIODOUT Read value is 0x00 1237 SWCU117C ...

Page 1238: ...e Reset Description 31 8 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 7 0 IO7_0 R W 0h Enables 1 or disables 0 digital input buffers for each AUX I O pin Input buffers must be enabled to allow reading pin values through GPIODIN Input buffers must be disabled for analog input or floating pins to avoid c...

Page 1239: ...ity Section 17 7 3 5 14h DMACTL Direct Memory Access Control Section 17 7 3 6 18h SWEVSET Software Event Set Section 17 7 3 7 1Ch EVSTAT0 Event Status 0 Section 17 7 3 8 20h EVSTAT1 Event Status 1 Section 17 7 3 9 24h EVTOMCUPOL Event To MCU Domain Polarity Section 17 7 3 10 28h EVTOMCUFLAGS Events to MCU Domain Flags Section 17 7 3 11 2Ch COMBEVTOMCUMASK Combined Event To MCU Domain Mask Section ...

Page 1240: ...an the reset value may result in undefined behavior 14 VEC1_POL R W 0h Selects vector 1 trigger event polarity To manually trigger vector 1 execution set VEC1_EV to a known static value and toggle VEC1_POL twice 0h Rising edge triggers execution 1h Falling edge triggers execution 13 VEC1_EN R W 0h Enables 1 or disables 0 triggering of vector 1 execution When enabled the edge selected by VEC1_POL o...

Page 1241: ...h AUXIO15 input data 1Dh ACLK_REF event 1Eh MCU_EV event 1Fh ADC_IRQ event 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 VEC0_POL R W 0h Selects vector 0 trigger event polarity To manually trigger vector 0 execution set VEC0_EV to a known static value and toggle VEC0_POL twice 0h Rising edge trigger...

Page 1242: ..._SW event Ch AON_PROG_WU event Dh AUXIO0 input data Eh AUXIO1 input data Fh AUXIO2 input data 10h AUXIO3 input data 11h AUXIO4 input data 12h AUXIO5 input data 13h AUXIO6 input data 14h AUXIO7 input data 15h AUXIO8 input data 16h AUXIO9 input data 17h AUXIO10 input data 18h AUXIO11 input data 19h AUXIO12 input data 1Ah AUXIO13 input data 1Bh AUXIO14 input data 1Ch AUXIO15 input data 1Dh ACLK_REF e...

Page 1243: ...he reset value may result in undefined behavior 14 VEC3_POL R W 0h Selects vector 3 trigger event polarity To manually trigger vector 3 execution set VEC3_EV to a known static value and toggle VEC3_POL twice 0h Rising edge triggers execution 1h Falling edge triggers execution 13 VEC3_EN R W 0h Enables 1 or disables 0 triggering of vector 3 execution When enabled the edge selected by VEC3_POL on th...

Page 1244: ...1Dh ACLK_REF event 1Eh MCU_EV event 1Fh ADC_IRQ event 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 VEC2_POL R W 0h Selects vector 2 trigger event polarity To manually trigger vector 2 execution set VEC2_EV to a known static value and toggle VEC2_POL twice 0h Rising edge triggers execution 1h Fallin...

Page 1245: ..._SW event Ch AON_PROG_WU event Dh AUXIO0 input data Eh AUXIO1 input data Fh AUXIO2 input data 10h AUXIO3 input data 11h AUXIO4 input data 12h AUXIO5 input data 13h AUXIO6 input data 14h AUXIO7 input data 15h AUXIO8 input data 16h AUXIO9 input data 17h AUXIO10 input data 18h AUXIO11 input data 19h AUXIO12 input data 1Ah AUXIO13 input data 1Bh AUXIO14 input data 1Ch AUXIO15 input data 1Dh ACLK_REF e...

Page 1246: ... to be mapped to AUX_SCE WUSTAT EV_SIGNALS bit 7 0h AON_RTC_CH2 event 1h AUX_COMPA event 2h AUX_COMPB event 3h TDC_DONE event 4h TIMER0_EV event 5h TIMER1_EV event 6h SMPH_AUTOTAKE_DONE event 7h ADC_DONE event 8h ADC_FIFO_ALMOST_FULL event 9h OBSMUX0 event Ah OBSMUX1 event Bh AON_SW event Ch AON_PROG_WU event Dh AUXIO0 input data Eh AUXIO1 input data Fh AUXIO2 input data 10h AUXIO3 input data 11h ...

Page 1247: ...V0 R W0C 0h R W0C 0h R W0C 0h R W0C 0h R W0C 0h R W0C 0h R W0C 0h R W0C 0h Table 17 45 EVTOAONFLAGS Register Field Descriptions Bit Field Type Reset Description 31 9 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 8 TIMER1_EV R W0C 0h TIMER1_EV event flag 7 TIMER0_EV R W0C 0h TIMER0_EV event flag 6 TDC_DO...

Page 1248: ...ned behavior 8 TIMER1_EV R W 0h Selects the event source level that sets EVTOAONFLAGS TIMER1_EV 0h High level 1h Low level 7 TIMER0_EV R W 0h Selects the event source level that sets EVTOAONFLAGS TIMER0_EV 0h High level 1h Low level 6 TDC_DONE R W 0h Selects the event source level that sets EVTOAONFLAGS TDC_DONE 0h High level 1h Low level 5 ADC_DONE R W 0h Selects the event source level that sets ...

Page 1249: ...the reset value may result in undefined behavior 2 REQ_MODE R W 0h DMA Request mode 0h Burst requests are generated on DMA channel 7 when the condition configured in SEL is met 1h Single requests are generated on DMA channel 7 when the condition configured in SEL is met 1 EN R W 0h 0 DMA interface is disabled 1 DMA interface is enabled 0 SEL R W 0h Selection of FIFO watermark level required to tri...

Page 1250: ...ERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 2 SWEV2 W 0h Writing 1 sets software event 2 For the MCU domain the event flag can be read from EVTOAONFLAGS SWEV2 and cleared using EVTOAONFLAGSCLR SWEV2 1 SWEV1 W 0h Writing 1 sets software event 1 For the MCU domain the event flag can be read from EVTOAONFLA...

Page 1251: ...O2 input data line 14 AUXIO1 R 0h Current value of AUXIO1 input data line 13 AUXIO0 R 0h Current value of AUXIO0 input data line 12 AON_PROG_WU R 0h Current value of OBSMUX3 event line 11 AON_SW R 0h Current value of OBSMUX2 event line 10 OBSMUX1 R 0h Current value of OBSMUX1 event line 9 OBSMUX0 R 0h Current value of OBSMUX0 event line 8 ADC_FIFO_ALMOST_FU R 0h Current value of ADC_FIFO_ALMOST_FU...

Page 1252: ...event line 14 MCU_EV R 0h Current value of MCU_EV event line 13 ACLK_REF R 0h Current value of ACLK_REF event line 12 AUXIO15 R 0h Current value of AUXIO15 input data line 11 AUXIO14 R 0h Current value of AUXIO14 input data line 10 AUXIO13 R 0h Current value of AUXIO13 input data line 9 AUXIO12 R 0h Current value of AUXIO12 input data line 8 AUXIO11 R 0h Current value of AUXIO11 input data line 7 ...

Page 1253: ... the reset value may result in undefined behavior 10 ADC_IRQ R W 0h Selects the event source level that sets EVTOMCUFLAGS ADC_IRQ 0h High level 1h Low level 9 OBSMUX0 R W 0h Selects the event source level that sets EVTOMCUFLAGS OBSMUX0 0h High level 1h Low level 8 ADC_FIFO_ALMOST_FU R W 0h Selects the event source level that sets LL EVTOMCUFLAGS ADC_FIFO_ALMOST_FULL 0h High level 1h Low level 7 AD...

Page 1254: ...nt source level that sets EVTOMCUFLAGS AUX_COMPB 0h High level 1h Low level 1 AUX_COMPA R W 0h Selects the event source level that sets EVTOMCUFLAGS AUX_COMPA 0h High level 1h Low level 0 AON_WU_EV R W 0h Selects the event source level that sets EVTOMCUFLAGS AON_WU_EV 0h High level 1h Low level 1254 AUX Sensor Controller with Digital and Analog Peripherals SWCU117C February 2015 Revised September ...

Page 1255: ...it Field Type Reset Description 31 11 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 10 ADC_IRQ R W0C 0h ADC_IRQ event flag 9 OBSMUX0 R W0C 0h OBSMUX0 event flag 8 ADC_FIFO_ALMOST_FU R W0C 0h ADC_FIFO_ALMOST_FULL event flag LL 7 ADC_DONE R W0C 0h ADC_DONE event flag 6 SMPH_AUTOTAKE_DON R W0C 0h SMPH_AUTO...

Page 1256: ...ibution to the AUX_COMB event 9 OBSMUX0 R W 0h Includes 1 or excludes 0 EVTOMCUFLAGS OBSMUX0 contribution to the AUX_COMB event 8 ADC_FIFO_ALMOST_FU R W 0h Includes 1 or excludes 0 LL EVTOMCUFLAGS ADC_FIFO_ALMOST_FULL contribution to the AUX_COMB event 7 ADC_DONE R W 0h Includes 1 or excludes 0 EVTOMCUFLAGS ADC_DONE contribution to the AUX_COMB event 6 SMPH_AUTOTAKE_DON R W 0h Includes 1 or exclud...

Page 1257: ...er value than the reset value may result in undefined behavior 3 VEC3 R W0C 0h The vector flag is set if the edge selected VECCFG1 VEC3_POL occurs on the event selected in VECCFG1 VEC3_EV The flag is cleared by writing a 0 to this bit or preferably a 1 to VECFLAGSCLR VEC3 2 VEC2 R W0C 0h The vector flag is set if the edge selected VECCFG1 VEC2_POL occurs on the event selected in VECCFG1 VEC2_EV Th...

Page 1258: ...avior 10 ADC_IRQ W 0h Writing 1 clears EVTOMCUFLAGS ADC_IRQ Read value is 0 9 OBSMUX0 W 0h Writing 1 clears EVTOMCUFLAGS OBSMUX0 Read value is 0 8 ADC_FIFO_ALMOST_FU W 0h Writing 1 clears EVTOMCUFLAGS ADC_FIFO_ALMOST_FULL LL Read value is 0 7 ADC_DONE W 0h Writing 1 clears EVTOMCUFLAGS ADC_DONE Read value is 0 6 SMPH_AUTOTAKE_DON W 0h Writing 1 clears EVTOMCUFLAGS SMPH_AUTOTAKE_DONE E Read value i...

Page 1259: ...ting any other value than the reset value may result in undefined behavior 8 TIMER1_EV W 0h Writing 1 clears EVTOAONFLAGS TIMER1_EV Read value is 0 7 TIMER0_EV W 0h Writing 1 clears EVTOAONFLAGS TIMER0_EV Read value is 0 6 TDC_DONE W 0h Writing 1 clears EVTOAONFLAGS TDC_DONE Read value is 0 5 ADC_DONE W 0h Writing 1 clears EVTOAONFLAGS ADC_DONE Read value is 0 4 AUX_COMPB W 0h Writing 1 clears EVT...

Page 1260: ... 57 VECFLAGSCLR Register Field Descriptions Bit Field Type Reset Description 31 4 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 3 VEC3 W 0h Writing 1 clears VECFLAGS VEC3 Read value is 0 2 VEC2 W 0h Writing 1 clears VECFLAGS VEC2 Read value is 0 1 VEC1 W 0h Writing 1 clears VECFLAGS VEC1 Read value is 0...

Page 1261: ...H0 Semaphore 0 Section 17 7 4 1 4h SMPH1 Semaphore 1 Section 17 7 4 2 8h SMPH2 Semaphore 2 Section 17 7 4 3 Ch SMPH3 Semaphore 3 Section 17 7 4 4 10h SMPH4 Semaphore 4 Section 17 7 4 5 14h SMPH5 Semaphore 5 Section 17 7 4 6 18h SMPH6 Semaphore 6 Section 17 7 4 7 1Ch SMPH7 Semaphore 7 Section 17 7 4 8 20h AUTOTAKE Sticky Request For Single Semaphore Section 17 7 4 9 1261 SWCU117C February 2015 Revi...

Page 1262: ...Bit Field Type Reset Description 31 1 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 STAT R W 1h Status when reading 0 Semaphore was already taken 1 Semaphore was available and hence taken by this read access Reading the register causes it to change value to 0 Releasing the semaphore is done by writing...

Page 1263: ...Bit Field Type Reset Description 31 1 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 STAT R W 1h Status when reading 0 Semaphore was already taken 1 Semaphore was available and hence taken by this read access Reading the register causes it to change value to 0 Releasing the semaphore is done by writing...

Page 1264: ...Bit Field Type Reset Description 31 1 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 STAT R W 1h Status when reading 0 Semaphore was already taken 1 Semaphore was available and hence taken by this read access Reading the register causes it to change value to 0 Releasing the semaphore is done by writing...

Page 1265: ...Bit Field Type Reset Description 31 1 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 STAT R W 1h Status when reading 0 Semaphore was already taken 1 Semaphore was available and hence taken by this read access Reading the register causes it to change value to 0 Releasing the semaphore is done by writing...

Page 1266: ... Bit Field Type Reset Description 31 1 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 STAT R W 1h Status when reading 0 Semaphore was already taken 1 Semaphore was available and hence taken by this read access Reading the register causes it to change value to 0 Releasing the semaphore is done by writin...

Page 1267: ... Bit Field Type Reset Description 31 1 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 STAT R W 1h Status when reading 0 Semaphore was already taken 1 Semaphore was available and hence taken by this read access Reading the register causes it to change value to 0 Releasing the semaphore is done by writin...

Page 1268: ... Bit Field Type Reset Description 31 1 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 STAT R W 1h Status when reading 0 Semaphore was already taken 1 Semaphore was available and hence taken by this read access Reading the register causes it to change value to 0 Releasing the semaphore is done by writin...

Page 1269: ... Bit Field Type Reset Description 31 1 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 STAT R W 1h Status when reading 0 Semaphore was already taken 1 Semaphore was available and hence taken by this read access Reading the register causes it to change value to 0 Releasing the semaphore is done by writin...

Page 1270: ... may result in undefined behavior 2 0 SMPH_ID R W 0h Requesting a certain semaphore is done by writing the corresponding semaphore ID 0x0 0x7 to SMPH_ID The request is sticky and once the semaphore becomes available it will be taken At the same time SMPH_AUTOTAKE_DONE event is asserted This event is deasserted when SW releases the semaphore or a new ID is written to SMPH_ID Note SW must wait until...

Page 1271: ...s Section 17 7 5 2 8h RESULT Result Section 17 7 5 3 Ch SATCFG Saturation Configuration Section 17 7 5 4 10h TRIGSRC Trigger Source Section 17 7 5 5 14h TRIGCNT Trigger Counter Section 17 7 5 6 18h TRIGCNTLOAD Trigger Counter Load Section 17 7 5 7 1Ch TRIGCNTCFG Trigger Counter Configuration Section 17 7 5 8 20h PRECTL Prescaler Control Section 17 7 5 9 24h PRECNT Prescaler Counter Section 17 7 5 ...

Page 1272: ...C FSM start counting synchronously to the first rising edge that follows a required falling edge of the start event This ensures an edge triggered start and is recommended for frequency measurements A falling edge of the start event may be missed if the command is issued close to it in time but the TDC will catch later falling edges and ensure that a measurement starts synchronously to the rising ...

Page 1273: ...ing new measurement or setting CTL CMD to CLR_RESULT 6 DONE R 0h Measurement complete flag 0 Measurement not yet complete 1 Measurement complete This field is cleared when starting new measurement or setting CTL CMD to CLR_RESULT 5 0 STATE R 6h TDC internal state machine status 0h Current state is TDC_STATE_WAIT_START 4h Current state is TDC_STATE_WAIT_STARTSTOPCNTEN 6h Current state is TDC_STATE_...

Page 1274: ...served Writing any other value than the reset value may result in undefined behavior 24 0 VALUE R 2h Result of the TDC conversion The result is in clock edges of the clock selected in DDI_0_OSC CTL0 ACLK_TDC_SRC_SEL Both rising and falling edges are counted When saturating the result is slightly higher than the saturation limit since it takes a non zero time to stop the measurement The highest sat...

Page 1275: ...LT VALUE 13 is set 5h Result bit 14 TDC saturates and stops when RESULT VALUE 14 is set 6h Result bit 15 TDC saturates and stops when RESULT VALUE 15 is set 7h Result bit 16 TDC saturates and stops when RESULT VALUE 16 is set 8h Result bit 17 TDC saturates and stops when RESULT VALUE 17 is set 9h Result bit 18 TDC saturates and stops when RESULT VALUE 18 is set Ah Result bit 19 TDC saturates and s...

Page 1276: ...START_SRC R 0h R W 0h R W 0h Table 17 73 TRIGSRC Register Field Descriptions Bit Field Type Reset Description 31 14 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 13 STOP_POL R W 0h Polarity of stop signal Note Must not be changed if STAT STATE is not IDLE 0h TDC stops when high level is detected 1h TDC ...

Page 1277: ...O3 11h Selects AUXIO4 12h Selects AUXIO5 13h Selects AUXIO6 14h Selects AUXIO7 15h Selects AUXIO8 16h Selects AUXIO9 17h Selects AUXIO10 18h Selects AUXIO11 19h Selects AUXIO12 1Ah Selects AUXIO13 1Bh Selects AUXIO14 1Ch Selects AUXIO15 1Dh Selects ACLK_REF 1Eh Selects MCU_EV 1Fh Selects TDC_PRE 7 6 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the re...

Page 1278: ..._ALMOST_FULL 9h Selects OBSMUX0 Ah Selects OBSMUX1 Bh Selects AON_SW Ch Selects AON_PROG_WU Dh Selects AUXIO0 Eh Selects AUXIO1 Fh Selects AUXIO2 10h Selects AUXIO3 11h Selects AUXIO4 12h Selects AUXIO5 13h Selects AUXIO6 14h Selects AUXIO7 15h Selects AUXIO8 16h Selects AUXIO9 17h Selects AUXIO10 18h Selects AUXIO11 19h Selects AUXIO12 1Ah Selects AUXIO13 1Bh Selects AUXIO14 1Ch Selects AUXIO15 1...

Page 1279: ...he value of a reserved Writing any other value than the reset value may result in undefined behavior 15 0 CNT R W 0h Remaining number of stop events that will be ignored Writing to this register updates the value The CNT will be loaded with the value of TRIGCNTLOAD CNT at the start of every measurement When the stop counter is enabled the first CNT 1 stop events is ignored after which the TDC will...

Page 1280: ... rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 15 0 CNT R W 0h Selects the number of stop events that will be ignored by the TDC This can be used to measure multiple periods of a clock signal The value written to this field is loaded into the stop counter at the start of each measurement Note Both values 0 and 1 will make the TDC stop...

Page 1281: ...ESERVED EN R 0h R W 0h Table 17 76 TRIGCNTCFG Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 EN R W 0h Stop counter enable 0 Stop counter is disabled 1 Stop counter is enabled 1281 SWCU117C February 2015 Revised September 2015 AUX Sensor...

Page 1282: ... must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 7 RESET_N R W 0h Prescaler reset control 0 Prescaler is held in reset 1 Prescaler is not held in reset 6 RATIO R W 0h Prescaler ratio This controls how often an event is generated on the TDC_PRE line After the prescaler is reset the event output TDC_PRE is 0 0h Prescaler divides ...

Page 1283: ...MOST_FULL 9h Selects OBSMUX0 Ah Selects OBSMUX1 Bh Selects AON_SW Ch Selects AON_PROG_WU Dh Selects AUXIO0 Eh Selects AUXIO1 Fh Selects AUXIO2 10h Selects AUXIO3 11h Selects AUXIO4 12h Selects AUXIO5 13h Selects AUXIO6 14h Selects AUXIO7 15h Selects AUXIO8 16h Selects AUXIO9 17h Selects AUXIO10 18h Selects AUXIO11 19h Selects AUXIO12 1Ah Selects AUXIO13 1Bh Selects AUXIO14 1Ch Selects AUXIO15 1Dh ...

Page 1284: ...gister Field Descriptions Bit Field Type Reset Description 31 16 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 15 0 CNT R W 0h Writing to this register will latch the contents of the 16 bit prescaler counter The value written is don t care Reading will return the latched value 1284 AUX Sensor Controller...

Page 1285: ...Registers Offset Acronym Register Name Section 0h T0CFG Timer 0 Configuration Section 17 7 6 1 4h T1CFG Timer 1 Configuration Section 17 7 6 2 8h T0CTL Timer 0 Control Section 17 7 6 3 Ch T0TARGET Timer 0 Target Section 17 7 6 4 10h T1TARGET Timer 1 Target Section 17 7 6 5 14h T1CTL Timer 1 Control Section 17 7 6 6 1285 SWCU117C February 2015 Revised September 2015 AUX Sensor Controller with Digit...

Page 1286: ...E RELOAD R W 0h R 0h R W 0h R W 0h Table 17 80 T0CFG Register Field Descriptions Bit Field Type Reset Description 31 14 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 13 TICK_SRC_POL R W 0h Source count polarity for timer 0 0h Count on rising edges of TICK_SRC 1h Count on falling edges of TICK_SRC 1286 A...

Page 1287: ... AUXIO11 19h Selects AUXIO12 1Ah Selects AUXIO13 1Bh Selects AUXIO14 1Ch Selects AUXIO15 1Dh Selects ACLK_REF 1Eh Selects MCU_EV 1Fh Selects ADC_IRQ 7 4 PRE R W 0h Prescaler division ratio is 2PRE 3 2 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 1 MODE R W 0h Timer 0 mode 0h Timer 0 increments on every...

Page 1288: ...E RELOAD R W 0h R 0h R W 0h R W 0h Table 17 81 T1CFG Register Field Descriptions Bit Field Type Reset Description 31 14 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 13 TICK_SRC_POL R W 0h Source count polarity for timer 1 0h Count on rising edges of TICK_SRC 1h Count on falling edges of TICK_SRC 1288 A...

Page 1289: ... AUXIO11 19h Selects AUXIO12 1Ah Selects AUXIO13 1Bh Selects AUXIO14 1Ch Selects AUXIO15 1Dh Selects ACLK_REF 1Eh Selects MCU_EV 1Fh Selects ADC_IRQ 7 4 PRE R W 0h Prescaler division ratio is 2PRE 3 2 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 1 MODE R W 0h Timer 1 mode 0h Timer 1 increments on every...

Page 1290: ...Descriptions Bit Field Type Reset Description 31 1 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 EN R W 0h Timer 0 run enable control The counter restarts when enabling the timer If T0CFG RELOAD 0 the timer is automatically disabled when reaching T0TARGET VALUE 0 Disable timer 0 1 Enable timer 0 1290 ...

Page 1291: ...ely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 15 0 VALUE R W 0h Timer 0 counts from 0 to VALUE Then gives an event and restarts if configured to do to so in the T0CFG RELOAD setting If VALUE is changed while timer 0 is running so that the count becomes higher than VALUE timer 0 will also restart if configured to do so If T0CFG MODE 0 n...

Page 1292: ...y on the value of a reserved Writing any other value than the reset value may result in undefined behavior 7 0 VALUE R W 0h Timer 1 counts from 0 to VALUE Then gives an event and restarts if configured to do to so in the T1CFG RELOAD setting If VALUE is changed while timer 1 is running so that the count becomes higher than VALUE timer 1 will also restart if configured to do so If T1CFG MODE 0 no p...

Page 1293: ... Descriptions Bit Field Type Reset Description 31 1 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 EN R W 0h Timer 1 run enable control The counter restarts when enabling the timer If T1CFG RELOAD 0 the timer is automatically disabled when reaching T1TARGET VALUE 0 Disable timer 1 1 Enable timer 1 1293...

Page 1294: ...tion 17 7 7 7 2Ch WUEVCLR Wake up Event Clear Section 17 7 7 8 30h ADCCLKCTL ADC Clock Control Section 17 7 7 9 34h TDCCLKCTL TDC Clock Control Section 17 7 7 10 38h REFCLKCTL Reference Clock Control Section 17 7 7 11 3Ch RTCSUBSECINC0 Real Time Counter Sub Second Increment 0 Section 17 7 7 12 40h RTCSUBSECINC1 Real Time Counter Sub Second Increment 1 Section 17 7 7 13 44h RTCSUBSECINCCTL Real Tim...

Page 1295: ...C R W 0h Enables 1 or disables 0 clock for AUX_DDI0_OSC 0h System CPU has not requested clock for AUX_DDI0_OSC 1h System CPU has requested clock for AUX_DDI0_OSC 5 TDC R W 0h Enables 1 or disables 0 clock for AUX_TDCIF Note that the TDC counter and reference clock sources must be requested separately using TDCCLKCTL and REFCLKCTL respectively 0h System CPU has not requested clock for TDC 1h System...

Page 1296: ...on 0 SMPH R W 0h Enables 1 or disables 0 clock for AUX_SMPH 0h System CPU has not requested clock for SMPH 1h System CPU has requested clock for SMPH 1296 AUX Sensor Controller with Digital and Analog Peripherals SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 1297: ...3 22 21 20 19 18 17 16 RESERVED R 0h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED REQ R 0h R W 0h Table 17 88 PWROFFREQ Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 REQ R W 0h Power off request 0 No action 1 Request to power down AUX...

Page 1298: ... 89 PWRDWNREQ Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 REQ R W 0h Power down request 0 Request for system to be in active mode 1 Request for system to be in power down mode When REQ is 1 one shall assume that the system is in power...

Page 1299: ...han the reset value may result in undefined behavior 0 ACK R 0h Power down acknowledgment Indicates whether the power down request given by PWRDWNREQ REQ is captured by the AON domain or not 0 AUX can assume that the system is in active mode 1 The request for power down is acknowledged and the AUX must act like the system is in power down mode and power supply is limited The system CPU cannot use ...

Page 1300: ...et Description 31 1 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 REQ R W 0h Low frequency request 0 Request clock frequency to be controlled by AON_WUC AUXCLK and the system state 1 Request low frequency clock SCLK_LF as the clock source for AUX This bit must not be modified unless CLKLFACK ACK match...

Page 1301: ...ptions Bit Field Type Reset Description 31 1 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 ACK R 0h Acknowledgment of CLKLFREQ REQ 0 Acknowledgment that clock frequency is controlled by AON_WUC AUXCLK and the system state 1 Acknowledgment that the low frequency clock SCLK_LF is the clock source for AU...

Page 1302: ...other value than the reset value may result in undefined behavior 2 AON_RTC_CH2 R 0h Indicates pending event from AON_RTC_CH2 compare Note that this flag will be set whenever the AON_RTC_CH2 event happens but that does not mean that this event is a wake up event To make the AON_RTC_CH2 a wake up event for the AUX domain configure it as a wake up event in AON_EVENT AUXWUSEL WU0_EV AON_EVENT AUXWUSE...

Page 1303: ...t Note that if RTC channel 2 is also set as source for AON_PROG_WU this field can also clear WUEVFLAGS AON_PROG_WU This bit must remain set until WUEVFLAGS AON_RTC_CH2 returns to 0 1 AON_SW R W 0h Set to clear the WUEVFLAGS AON_SW wake up event This bit must remain set until WUEVFLAGS AON_SW returns to 0 0 AON_PROG_WU R W 0h Set to clear the WUEVFLAGS AON_PROG_WU wake up event Note only if an IO e...

Page 1304: ... 2 1 0 RESERVED ACK REQ R 0h R 0h R W 0h Table 17 95 ADCCLKCTL Register Field Descriptions Bit Field Type Reset Description 31 2 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 1 ACK R 0h Acknowledges the last value written to REQ 0 REQ R W 0h Enables 1 or disables 0 the ADC internal clock This bit must n...

Page 1305: ...3 2 1 0 RESERVED ACK REQ R 0h R 0h R W 0h Table 17 96 TDCCLKCTL Register Field Descriptions Bit Field Type Reset Description 31 2 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 1 ACK R 0h Acknowledges the last value written to REQ 0 REQ R W 0h Enables 1 or disables 0 the TDC counter clock source This bit...

Page 1306: ... 9 8 7 6 5 4 3 2 1 0 RESERVED ACK REQ R 0h R 0h R W 0h Table 17 97 REFCLKCTL Register Field Descriptions Bit Field Type Reset Description 31 2 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 1 ACK R 0h Acknowledges the last value written to REQ 0 REQ R W 0h Enables 1 or disables 0 the TDC reference clock ...

Page 1307: ...CCTL UPD_REQ Figure 17 73 RTCSUBSECINC0 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED INC15_0 R 0h R W 0h Table 17 98 RTCSUBSECINC0 Register Field Descriptions Bit Field Type Reset Description 31 16 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 1...

Page 1308: ...CCTL UPD_REQ Figure 17 74 RTCSUBSECINC1 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED INC23_16 R 0h R W 0h Table 17 99 RTCSUBSECINC1 Register Field Descriptions Bit Field Type Reset Description 31 8 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 7...

Page 1309: ...Descriptions Bit Field Type Reset Description 31 2 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 1 UPD_ACK R 0h Acknowledgment of the UPD_REQ 0 UPD_REQ R W 0h Signal that a new real time counter sub second increment value is available 0 New sub second increment is not available 1 New sub second incremen...

Page 1310: ...ion 31 1 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 DISCONNECT_REQ R W 0h Requests the AUX domain bus to be disconnected from the MCU domain bus The request has no effect when AON_WUC AUX_CTL AUX_FORCE_ON is set The disconnection status can be monitored through MCUBUSSTAT Note however that this reg...

Page 1311: ...02 MCUBUSSTAT Register Field Descriptions Bit Field Type Reset Description 31 2 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 1 DISCONNECTED R 0h Indicates whether the AUX domain and MCU domain buses are currently disconnected 1 or connected 0 0 DISCONNECT_ACK R 0h Acknowledges reception of the bus disc...

Page 1312: ... 1 0 RESERVED AUX_FORCE_ SCE_RUN_EN ON R 0h R 0h R 0h Table 17 103 AONCTLSTAT Register Field Descriptions Bit Field Type Reset Description 31 2 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 1 AUX_FORCE_ON R 0h Status of AON_WUC AUX_CTL AUX_FORCE_ON 0 SCE_RUN_EN R 0h Status of AON_WUC AUX_CTL SCE_RUN_EN ...

Page 1313: ...0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 EN R W 0h Opens 1 or closes 0 the AUX_AIODIO0 AUX_AIODIO1 signal latching At startup set EN TRANSP before configuring AUX_AIODIO0 AUX_AIODIO1 and subsequently selecting AUX mode in the AON_IOC When powering off the AUX domain using PWROFFREQ REQ set EN STATIC in adva...

Page 1314: ...as requested clock for AUX_ADI4 6 AUX_DDI0_OSC R W 0h Enables 1 or disables 0 clock for AUX_DDI0_OSC 0h AUX_SCE has not requested clock for AUX_DDI0_OSC 1h AUX_SCE has requested clock for AUX_DDI0_OSC 5 TDC R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 4 ANAIF R W 0h Enables 1 or disables 0 clock for AUX_ANAIF...

Page 1315: ...ified Table 17 106 AUX_ANAIF Registers Offset Acronym Register Name Section 10h ADCCTL ADC Control Section 17 7 8 1 14h ADCFIFOSTAT ADC FIFO Status Section 17 7 8 2 18h ADCFIFO ADC FIFO Section 17 7 8 3 1Ch ADCTRIG ADC Trigger Section 17 7 8 4 20h ISRCCTL Current Source Control Section 17 7 8 5 1315 SWCU117C February 2015 Revised September 2015 AUX Sensor Controller with Digital and Analog Periphe...

Page 1316: ...0h Table 17 107 ADCCTL Register Field Descriptions Bit Field Type Reset Description 31 14 RESERVED R 0h Software should not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 13 START_POL R W 0h Selected active edge for start event Selected polarity for start event 0h Start on rising edge of event 1h Start on falling edge of event 1316 AUX...

Page 1317: ...Selects AUXIO3 as start signal 11h Selects AUXIO4 as start signal 12h Selects AUXIO5 as start signal 13h Selects AUXIO6 as start signal 14h Selects AUXIO7 as start signal 15h Selects AUXIO8 as start signal 16h Selects AUXIO9 as start signal 17h Selects AUXIO10 as start signal 18h Selects AUXIO11 as start signal 19h Selects AUXIO12 as start signal 1Ah Selects AUXIO13 as start signal 1Bh Selects AUX...

Page 1318: ...avior 4 OVERFLOW R 0h FIFO overflow flag 0 FIFO has not overflowed 1 FIFO has overflowed this flag is sticky until FIFO is flushed 3 UNDERFLOW R 0h FIFO underflow flag 0 FIFO has not underflowed 1 FIFO has underflowed this flag is sticky until the FIFO is flushed 2 FULL R 0h FIFO full flag 0 FIFO is not full i e there is less than 4 samples in the FIFO 1 FIFO is full i e there are 4 samples in the...

Page 1319: ...ter Field Descriptions Bit Field Type Reset Description 31 12 RESERVED R 0h Software should not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 11 0 DATA R W 0h FIFO is popped when read Data is pushed into FIFO when written Writing is intended for debugging code development purposes 1319 SWCU117C February 2015 Revised September 2015 AUX...

Page 1320: ...Descriptions Bit Field Type Reset Description 31 1 RESERVED R 0h Software should not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 START W 0h Writing to this register will trigger an ADC conversion given that ADCCTL START_SRC is set to NO_EVENT0 or NO_EVENT1 If other setting is used in ADCCTL START_SRC behavior can be unpredictable ...

Page 1321: ...D RESET_N R 0h R W 1h Table 17 111 ISRCCTL Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R 0h Software should not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 RESET_N R W 1h Current source control 0 Current source is clamped 1 Current source is active charging 1321 SWCU117C February 2015 Revised Septemb...

Page 1322: ...the CC26xx and CC13xx battery monitor and temperature sensor Topic Page 18 1 Introduction 1324 18 2 Functional Description 1324 18 3 BATMON Registers 1325 1322 Battery Monitor and Temperature Sensor SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 1323: ...erforms alternate measurements of the supply voltage and the temperature sensor A small digital core transforms these measurements to voltage and temperature in C which are read directly from the BAT and TEMP registers The module also includes two registers BATUPD and TEMPUPD that are used to monitor changes in voltage and temperature respectively The registers are connected to the AON event fabri...

Page 1324: ...Calculation Parameter 1 Section 18 3 1 4 14h TEMPP2 Temperature Calculation Parameter 2 Section 18 3 1 5 18h BATMONP0 Battery Voltage Calculation Parameter 0 Section 18 3 1 6 1Ch BATMONP1 Battery Voltage Calculation Parameter 1 Section 18 3 1 7 20h IOSTRP0 IO Drive Strength Conversion Parameter 0 Section 18 3 1 8 24h FLASHPUMPP0 Flash Pump Conversion Parameter 0 Section 18 3 1 9 28h BAT Last Measu...

Page 1325: ... R 0h 7 6 5 4 3 2 1 0 RESERVED CALC_EN MEAS_EN R 0h R W 0h R W 0h Table 18 2 CTL Register Field Descriptions Bit Field Type Reset Description 31 2 RESERVED R 0h Internal Only to be used through TI provided API 1 CALC_EN R W 0h Internal Only to be used through TI provided API 0 MEAS_EN R W 0h Internal Only to be used through TI provided API 1325 SWCU117C February 2015 Revised September 2015 Battery...

Page 1326: ...16 RESERVED R 0h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED PER R 0h R W 0h Table 18 3 MEASCFG Register Field Descriptions Bit Field Type Reset Description 31 2 RESERVED R 0h Internal Only to be used through TI provided API 1 0 PER R W 0h Internal Only to be used through TI provided API 1326 Battery Monitor and Temperature Sensor SWCU117C February 2015 Revised September 2015 Submit Documentati...

Page 1327: ...18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED CFG R 0h R W 0h Table 18 4 TEMPP0 Register Field Descriptions Bit Field Type Reset Description 31 8 RESERVED R 0h Internal Only to be used through TI provided API 7 0 CFG R W 0h Internal Only to be used through TI provided API 1327 SWCU117C February 2015 Revised September 2015 Battery Monitor and Temperature Sensor Submit Documentation Feedba...

Page 1328: ... 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED CFG R 0h R W 0h Table 18 5 TEMPP1 Register Field Descriptions Bit Field Type Reset Description 31 6 RESERVED R 0h Internal Only to be used through TI provided API 5 0 CFG R W 0h Internal Only to be used through TI provided API 1328 Battery Monitor and Temperature Sensor SWCU117C February 2015 Revised September 2015 Submit Documentation Feedb...

Page 1329: ... 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED CFG R 0h R W 0h Table 18 6 TEMPP2 Register Field Descriptions Bit Field Type Reset Description 31 5 RESERVED R 0h Internal Only to be used through TI provided API 4 0 CFG R W 0h Internal Only to be used through TI provided API 1329 SWCU117C February 2015 Revised September 2015 Battery Monitor and Temperature Sensor Submit Documentation Feedb...

Page 1330: ...19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED CFG R 0h R W 0h Table 18 7 BATMONP0 Register Field Descriptions Bit Field Type Reset Description 31 6 RESERVED R 0h Internal Only to be used through TI provided API 5 0 CFG R W 0h Internal Only to be used through TI provided API 1330 Battery Monitor and Temperature Sensor SWCU117C February 2015 Revised September 2015 Submit Documentation F...

Page 1331: ...19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED CFG R 0h R W 0h Table 18 8 BATMONP1 Register Field Descriptions Bit Field Type Reset Description 31 6 RESERVED R 0h Internal Only to be used through TI provided API 5 0 CFG R W 0h Internal Only to be used through TI provided API 1331 SWCU117C February 2015 Revised September 2015 Battery Monitor and Temperature Sensor Submit Documentation F...

Page 1332: ... 7 6 5 4 3 2 1 0 RESERVED CFG2 CFG1 R 0h R W 2h R W 8h Table 18 9 IOSTRP0 Register Field Descriptions Bit Field Type Reset Description 31 6 RESERVED R 0h Internal Only to be used through TI provided API 5 4 CFG2 R W 2h Internal Only to be used through TI provided API 3 0 CFG1 R W 8h Internal Only to be used through TI provided API 1332 Battery Monitor and Temperature Sensor SWCU117C February 2015 ...

Page 1333: ... FLASHPUMPP0 Register Field Descriptions Bit Field Type Reset Description 31 9 RESERVED R 0h Internal Only to be used through TI provided API 8 FALLB R W 0h Internal Only to be used through TI provided API 7 6 HIGHLIM R W 0h Internal Only to be used through TI provided API 5 LOWLIM R W 0h Internal Only to be used through TI provided API 4 OVR R W 0h Internal Only to be used through TI provided API...

Page 1334: ...ptions Bit Field Type Reset Description 31 11 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 10 8 INT R 0h Integer part 0x0 0V fractional part 0x3 3V fractional part 0x4 4V fractional part 7 0 FRAC R 0h Fractional part standard binary fractional encoding 0x00 0V 0x20 1 8 125V 0x40 1 4 25V 0x80 1 2 5V 0xA...

Page 1335: ...0 RESERVED STAT R 0h R W1C 0h Table 18 12 BATUPD Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 STAT R W1C 0h 0 No update since last clear 1 New battery voltage is present Write 1 to clear the status 1335 SWCU117C February 2015 Revised S...

Page 1336: ...iption 31 17 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 16 8 INT R 0h Integer part signed of temperature value Total value INTEGER FRACTIONAL 2 s complement encoding 0x100 Min value 0x1D8 40 C 0x1FF 1 C 0x00 0 C 0x1B 27 C 0x55 85 C 0xFF Max value 7 0 RESERVED R 0h Software must not rely on the value ...

Page 1337: ...3 2 1 0 RESERVED STAT R 0h R W1C 0h Table 18 14 TEMPUPD Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 STAT R W1C 0h 0 No update since last clear 1 New temperature is present Write 1 to clear the status 1337 SWCU117C February 2015 Revise...

Page 1338: ...er 1340 19 2 Block Diagram 1341 19 3 Signal Description 1341 19 4 Functional Description 1341 19 5 Interface to DMA 1345 19 6 Initialization and Configuration 1346 19 7 UARTS Registers 1348 1338 Universal Asynchronous Receivers and Transmitters UARTS SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 1339: ...istics 5 6 7 or 8 data bits Even odd stick or no parity bit generation and detection 1 or 2 stop bit generation Support for modem control functions CTS and RTS Independent masking of the TX FIFO RX FIFO RX time out modem status and error conditions Standard FIFO level and end of transmission interrupts Efficient transfers using micro direct memory access controller μDMA Separate channels for trans...

Page 1340: ...r 11 I O Control chapter Table 19 1 Signals for UART Pin Name Pin Number Pin Type 1 Description UARTRxD Assigned through I UART module 0 receive GPIO UARTTxD O UART module 0 transmit configuration 1 I Input O Output I O Bidirectional 19 4 Functional Description Each CC26xx and CC13xx UART performs the functions of parallel to serial and serial to parallel conversions The CC26xx and CC13xx UART is ...

Page 1341: ...into the UART FBRD DIVFRAC bit field can be calculated by taking the fractional part of the baud rate divisor multiplying it by 64 and adding 0 5 to account for rounding errors as shown by Equation 2 UART FBRD DIVFRAC integer BRDF 64 0 5 2 Along with the UART Line Control High Byte Register UART LCRH the UART_IBRD and the UART FBRD registers form an internal 30 bit register This internal register ...

Page 1342: ...modem flow control signals are defined as UART0CTS is Clear To Send UART0RTS is Request To Send When used as a DCE the modem flow control signals are defined as UART0CTS is Request To Send UART0RTS is Clear To Send 19 4 4 2 Flow Control Either hardware or software can accomplish flow control The following sections describe the different methods 19 4 4 2 1 Hardware Flow Control RTS and CTS Hardware...

Page 1343: ...xample if the option is selected for the receive FIFO the UART generates a receive interrupt after 4 data bytes are received Out of reset both FIFOs are configured to trigger an interrupt at the mark 19 4 6 Interrupts The UART can generate interrupts when the following conditions are observed Overrun error Break error Parity error Framing error Receive time out Transmit when the condition defined ...

Page 1344: ... error conditions framing parity break or overrun The cause of the interrupt can be determined by reading the UART RIS register or the UART MIS register The interrupt can be cleared by writing to the relevant bits of the UART ICR register In addition to the five events produced by the UART module two additional events are ORed to the interrupt line RX DMA done Indicates that the receiver DMA has c...

Page 1345: ...n the DMA Control Register UART DMACTL is cleared Figure 19 3 µDMA Example 19 6 Initialization and Configuration The UART module provides four I O signals to be routed to the pads The following signals are selected through the IOCFGn registers in the IOC module The UART module provides four I O functions to be routed to the pads Inputs RXD CTS Outputs TXD RTS CTS and RTS lines are active low NOTE ...

Page 1346: ...t No parity FIFOs disabled No interrupts The first thing to consider when programming the UART is the BRD because the UART IBRD and UART FBRD registers must be written before the UART LCRH register Using the equation described in Section 19 4 2 the BRD can be calculated BRD 24 000 000 16 115 200 13 0208 3 This means that the UART IBRD DIVINT field must be set to 13 decimal or 0xD The value to be l...

Page 1347: ...7 1 4 24h IBRD Integer Baud Rate Divisor Section 19 7 1 5 28h FBRD Fractional Baud Rate Divisor Section 19 7 1 6 2Ch LCRH Line Control Section 19 7 1 7 30h CTL Control Section 19 7 1 8 34h IFLS Interrupt FIFO Level Select Section 19 7 1 9 38h IMSC Interrupt Mask Set Clear Section 19 7 1 10 3Ch RIS Raw Interrupt Status Section 19 7 1 11 40h MIS Masked Interrupt Status Section 19 7 1 12 44h ICR Inte...

Page 1348: ...VED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 11 OE R X UART Overrun Error This bit is set to 1 if data is received and the receive FIFO is already full The FIFO contents remain valid because no more data is written when the FIFO is full only the contents of the shift register are overwritten This is cleared...

Page 1349: ...s associated with the character at the top of the FIFO i e the oldest received data character since last read 7 0 DATA R W X Data transmitted or received On writes the transmit data character is pushed into the FIFO On reads the oldest received data character since the last read is returned 1349 SWCU117C February 2015 Revised September 2015 Universal Asynchronous Receivers and Transmitters UARTS S...

Page 1350: ...3 OE R 0h UART Overrun Error This bit is set to 1 if data is received and the receive FIFO is already full The FIFO contents remain valid because no more data is written when the FIFO is full only the contents of the shift register are overwritten This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it 2 BE R 0h UART Break Error This bit is set to 1 i...

Page 1351: ...iptions Bit Field Type Reset Description 31 4 RESERVED W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 3 OE W 0h The framing FE parity PE break BE and overrun OE errors are cleared to 0 by any write to this register 2 BE W 0h The framing FE parity PE break BE and overrun OE errors are cleared to 0 by any write to ...

Page 1352: ...this bit is set when the receive FIFO is full 5 TXFF R 0h UART Transmit FIFO Full Transmit FIFO full The meaning of this bit depends on the state of LCRH FEN If the FIFO is disabled this bit is set when the transmit holding register is full If the FIFO is enabled this bit is set when the transmit FIFO is full 4 RXFE R 1h UART Receive FIFO Empty Receive FIFO empty The meaning of this bit depends on...

Page 1353: ...R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 15 0 DIVINT R W 0h The integer baud rate divisor The baud rate divisor is calculated using the formula below Baud rate divisor UART reference clock frequency 16 Baud rate Baud rate divisor must be minimum 1 and maximum 65535 That is DIVINT 0 does not give a valid b...

Page 1354: ...SERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 5 0 DIVFRAC R W 0h Fractional Baud Rate Divisor The baud rate divisor is calculated using the formula below Baud rate divisor UART reference clock frequency 16 Baud rate Baud rate divisor must be minimum 1 and maximum 65535 That is IBRD DIVINT 0 does not giv...

Page 1355: ...he number of data bits transmitted or received in a frame 0h 5 Word Length 5 bits 1h 6 Word Length 6 bits 2h 7 Word Length 7 bits 3h 8 Word Length 8 bits 4 FEN R W 0h UART Enable FIFOs 0h FIFOs are disabled character mode that is the FIFOs become 1 byte deep holding registers 1h Transmit and receive FIFO buffers are enabled FIFO mode 3 STP2 R W 0h UART Two Stop Bits Select If this bit is set to 1 ...

Page 1356: ...UARTTXD output pin after completing transmission of the current character For the proper execution of the break command the software must set this bit for at least two complete frames For normal use this bit must be cleared to 0 1356 Universal Asynchronous Receivers and Transmitters UARTS SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Texas Instruments I...

Page 1357: ...undefined behavior 11 RTS R W 0h Request to Send This bit is the complement of the active low UART RTS output That is when the bit is programmed to a 1 then RTS output on the pins is LOW 10 RESERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 9 RXE R W 1h UART Receive Enable If the UART is disabled in the mi...

Page 1358: ...ed Bit Field Type Reset Description 0 UARTEN R W 0h UART Enable 0h UART disabled 1h UART enabled 1358 Universal Asynchronous Receivers and Transmitters UARTS SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 1359: ...elect This field sets the trigger points for the receive interrupt Values 0b101 0b111 are reserved 0h 1_8 Receive FIFO becomes 1 8 full 1h 2_8 Receive FIFO becomes 1 4 full 2h 4_8 Receive FIFO becomes 1 2 full 3h 6_8 Receive FIFO becomes 3 4 full 4h 7_8 Receive FIFO becomes 7 8 full 2 0 TXSEL R W 2h Transmit interrupt FIFO level select This field sets the trigger points for the transmit interrupt ...

Page 1360: ...UART parity error interrupt On a write of 1 the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS PEMIS A write of 0 clears the mask which means MIS PEMIS will not reflect the interrupt 7 FEIM R W 0h Framing error interrupt mask A read returns the current mask for the UART framing error interrupt On a write of 1 the mask of the overrun error interr...

Page 1361: ...than the reset value may result in undefined behavior 1 CTSMIM R W 0h Clear to Send CTS modem interrupt mask A read returns the current mask for the UART clear to send interrupt On a write of 1 the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS CTSMMIS A write of 0 clears the mask which means MIS CTSMMIS will not reflect the interrupt 0 RESERVED...

Page 1362: ...smission time defined as start data parity and stop bits 8 PERIS R 0h Parity error interrupt status This field returns the raw interrupt state of the UART parity error interrupt Parity error is set if the parity of the received data character does not match the parity that the LCRH EPS and LCRH SPS select 7 FERIS R 0h Framing error interrupt status This field returns the raw interrupt state of the...

Page 1363: ...e enabled LCRH FEN 1 the receive interrupt is asserted if the receive FIFO reaches the programmed trigger level IFLS RXSEL The receive interrupt is cleared by reading data from the receive FIFO until it becomes less than the trigger level or by clearing the interrupt through ICR RXIC When FIFOs are disabled LCRH FEN 0 that is they have a depth of one location the receive interrupt is asserted if d...

Page 1364: ... 0h Framing error masked interrupt status Returns the masked interrupt state of the framing error interrupt which is the AND product of raw interrupt state RIS FERIS and the mask setting IMSC FEIM 6 RTMIS R 0h Receive timeout masked interrupt status Returns the masked interrupt state of the receive timeout interrupt The raw interrupt for receive timeout cannot be set unless the mask is set IMSC RT...

Page 1365: ...ERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 1365 SWCU117C February 2015 Revised September 2015 Universal Asynchronous Receivers and Transmitters UARTS Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 1366: ... field clears the parity error interrupt RIS PERIS Writing 0 has no effect 7 FEIC W X Framing error interrupt clear Writing 1 to this field clears the framing error interrupt RIS FERIS Writing 0 has no effect 6 RTIC W X Receive timeout interrupt clear Writing 1 to this field clears the receive timeout interrupt RIS RTRIS Writing 0 has no effect 5 TXIC W X Transmit interrupt clear Writing 1 to this...

Page 1367: ...ing any other value than the reset value may result in undefined behavior 2 DMAONERR R W 0h DMA on error If this bit is set to 1 the DMA receive request outputs for single and burst requests are disabled when the UART error interrupt is asserted more specifically if any of the error interrupts RIS PERIS RIS BERIS RIS FERIS or RIS OERIS are asserted 1 TXDMAE R W 0h Transmit DMA enable If this bit i...

Page 1368: ...chronous Serial Interface 1370 20 2 Block Diagram 1371 20 3 Signal Description 1372 20 4 Functional Description 1372 20 5 DMA Operation 1381 20 6 Initialization and Configuration 1381 20 7 SSI Registers 1383 1368 Synchronous Serial Interface SSI SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 1369: ...s Internal loopback test mode for diagnostic and debug testing Interrupts for transmit and receive FIFOs overrun and time out interrupts and DMA done interrupts Efficient transfers using micro direct memory access controller μDMA Separate channels for transmit and receive Receive single request asserted when data is in the FIFO burst request asserted when FIFO contains four or more entries Transmi...

Page 1370: ...FO 8 x 16 RX FIFO 8 x 16 PERDMACLK Interrupt DMA Request SSIn_TX SSI n_RX SSIn_CLK SSIn_FSS Block Diagram www ti com 20 2 Block Diagram Figure 20 1 shows the SSI block diagram Figure 20 1 SSI Module Block Diagram 1370 Synchronous Serial Interface SSI SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 1371: ...nerate the serial output clock The bit rates are supported to 2 MHz and higher with maximum bit rate is determined by peripheral devices The serial bit rate is derived by dividing down the input clock SysClk First the clock is divided by an even prescale value CPSDVSR from 2 to 254 which is programmed in the SSI Clock Prescale Register SSI CPSR see Section 20 7 1 5 CPSR Register Offset 10h reset X...

Page 1372: ...egister UDMA DONEMASK Clearing the appropriate bit in the UDMA DONEMASK register enables the RX or TX DMA done interrupt The status of the individual interrupt sources can be read from the SSI Raw Interrupt Status Regiater SSI RIS and the SSI Masked Interrupt Status Register SSI MIS see Section 20 7 1 7 RIS Register Offset 18h reset X and Section 20 7 1 8 MIS Register Offset 1Ch reset X respective...

Page 1373: ...control message is transmitted to the off chip slave No incoming data is received by the SSI during this transmission After the message is sent the off chip slave decodes it and responds with the requested data after waiting one serial clock after the last bit of the 8 bit control message is sent The returned data can be 4 to 16 bits long making the total frame length anywhere from 13 to 25 bits 2...

Page 1374: ... the bit places a steady state high value on the SSIn_CLK pin when data is not being transferred 20 4 4 2 2 SPH Phase Control Bit The SPH phase control bit selects the clock edge that captures data and allows it to change state The state of this bit has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge When the SPH...

Page 1375: ...the SSIn_CLK master clock pin goes high after an additional one half SSIn_CLK period The data is now captured on the rising edges and propagated on the falling edges of the SSIn_CLK signal For a single word transmission after all bits of the data word are transferred the SSIn_FSS line is returned to its IDLE high state one SSIn_CLK period after the last bit is captured For continuous back to back ...

Page 1376: ...bled and valid data is in the TX FIFO the SSIn_FSS master signal goes low at the start of transmission The master SSIn_TX output is enabled After an additional one half SSIn_CLK period both master and slave valid data are enabled onto their respective transmission lines At the same time SSIn_CLK is enabled with a rising edge transition Data is then captured on the falling edges and propagated on t...

Page 1377: ...mmediately The master SSIn_TX output pad is enabled One half SSIn_CLK period later valid master data is transferred to the SSIn_TX line When both the master and slave data have been set the SSIn_CLK master clock pin becomes low after one additional half SSIn_CLK period Data is captured on the falling edges and propagated on the rising edges of the SSIn_CLK signal For a single word transmission aft...

Page 1378: ...ord transmission after all bits are transferred the SSIn_FSS line returns to its IDLE high state one SSIn_CLK period after the last bit is captured For continuous back to back transmissions the SSIn_FSS pin remains in its active low state until the final bit of the last word is captured and then returns to its IDLE state For continuous back to back transfers the SSIn_FSS pin is held low between su...

Page 1379: ...ng the data to the RX FIFO NOTE The off chip slave device can 3 state the receive line either on the falling edge of SSIn_CLK after the LSB has been latched by the receive shifter or when the SSIn_FSS pin goes high For continuous transfers data transmission begins and ends like a single transfer but the SSIn_FSS line is held low and data transmits back to back The control byte of the next frame fo...

Page 1380: ...g bits in the UDMA REQDONE register must be 1 For more details about programming the μDMA controller see Chapter 12 µDMA 20 6 Initialization and Configuration To enable and initialize the SSI perform the following steps 1 Ensure the corresponding power domain is powered up properly For details refer to Chapter 6 PRCM 2 Enable the appropriate SSI module in PRCM by writing to the PRCM SSICLKGR regis...

Page 1381: ... is shown in Equation 6 SSIn_CLK PERDMACLK CPSDVSR 1 SCR 1 106 20 106 CPSDVSR 1 SCR 1000000 bps 48000000 Hz 2 1 23 6 In this case if CPSDVSR 0x2 SCR must be 0x18 The configuration sequence is 1 Ensure that the SSE bit in the SSI CR1 register is clear 2 Write the SSI CR1 register with a value of 0x0000 0000 3 Write the SSI CPSR register with a value of 0x0000 0002 4 Write the SSI CR0 register with ...

Page 1382: ... 0 Section 20 7 1 1 4h CR1 Control 1 Section 20 7 1 2 8h DR Data Section 20 7 1 3 Ch SR Status Section 20 7 1 4 10h CPSR Clock Prescale Section 20 7 1 5 14h IMSC Interrupt Mask Set and Clear Section 20 7 1 6 18h RIS Raw Interrupt Status Section 20 7 1 7 1Ch MIS Masked Interrupt Status Section 20 7 1 8 20h ICR Interrupt Clear Section 20 7 1 9 24h DMACR DMA Control Section 20 7 1 10 1382 Synchronous...

Page 1383: ...dge that captures data and enables it to change state It has the most impact on the first bit transmitted by either permitting or not permitting a clock transition before the first data capture edge 0h 1ST_CLK_EDGE Data is captured on the first clock edge transition 1h 2ND_CLK_EDGE Data is captured on the second clock edge transition 6 SPO R W 0h CLKOUT polarity Motorola SPI frame format only 0h S...

Page 1384: ...T 4 bit data 4h 5_BIT 5 bit data 5h 6_BIT 6 bit data 6h 7_BIT 7 bit data 7h 8_BIT 8 bit data 8h 9_BIT 9 bit data 9h 10_BIT 10 bit data Ah 11_BIT 11 bit data Bh 12_BIT 12 bit data Ch 13_BIT 13 bit data Dh 14_BIT 14 bit data Eh 15_BIT 15 bit data Fh 16_BIT 16 bit data 1384 Synchronous Serial Interface SSI SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Texa...

Page 1385: ...le ensuring that only one slave drives data onto its serial output line In such systems the RXD lines from multiple slaves could be tied together To operate in such systems this bit field can be set if the SSI slave is not supposed to drive the TXD line 0 SSI can drive the TXD output in slave mode 1 SSI cannot drive the TXD output in slave mode 2 MS R W 0h Master or slave mode select This bit can ...

Page 1386: ...t justify data written to the transmit FIFO The transmit logic ignores the unused bits Received data less than 16 bits is automatically right justified in the receive buffer Figure 20 15 DR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED DATA R 0h R W X Table 20 5 DR Register Field Descriptions Bit Field Type Reset Description 31 16 RESERVED ...

Page 1387: ...n the reset value may result in undefined behavior 4 BSY R 0h Serial interface busy 0 SSI is idle 1 SSI is currently transmitting and or receiving a frame or the transmit FIFO is not empty 3 RFF R 0h Receive FIFO full 0 Receive FIFO is not full 1 Receive FIFO is full 2 RNE R 0h Receive FIFO not empty 0 Receive FIFO is empty 1 Receive FIFO is not empty 1 TNF R 1h Transmit FIFO not full 0 Transmit F...

Page 1388: ...alue than the reset value may result in undefined behavior 7 0 CPSDVSR R W 0h Clock prescale divisor This field specifies the division factor by which the input system clock to SSI must be internally divided before further use The value programmed into this field must be an even nonzero number 2 254 The least significant bit of the programmed number is hard coded to zero If an odd number is writte...

Page 1389: ...rrupt 2 RXIM R W 0h Receive FIFO interrupt mask A read returns the current mask for receive FIFO interrupt On a write of 1 the mask for receive FIFO interrupt is set which means the interrupt state will be reflected in MIS RXMIS A write of 0 clears the mask which means MIS RXMIS will not reflect the interrupt 1 RTIM R W 0h Receive timeout interrupt mask A read returns the current mask for receive ...

Page 1390: ... to the transmit FIFO by an interrupt service routine 2 RXRIS R 0h Raw interrupt state of receive FIFO interrupt The receive interrupt is asserted when there are four or more valid entries in the receive FIFO 1 RTRIS R 0h Raw interrupt state of receive timeout interrupt The receive timeout interrupt is asserted when the receive FIFO is not empty and SSI has remained idle for a fixed 32 bit period ...

Page 1391: ...h is the AND product of raw interrupt state RIS TXRIS and the mask setting IMSC TXIM 2 RXMIS R 0h Masked interrupt state of receive FIFO interrupt This field returns the masked interrupt state of receive FIFO interrupt which is the AND product of raw interrupt state RIS RXRIS and the mask setting IMSC RXIM 1 RTMIS R 0h Masked interrupt state of receive timeout interrupt This field returns the mask...

Page 1392: ... Field Descriptions Bit Field Type Reset Description 31 2 RESERVED W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 1 RTIC W 0h Clear the receive timeout interrupt Writing 1 to this field clears the timeout interrupt RIS RTRIS Writing 0 has no effect 0 RORIC W 0h Clear the receive overrun interrupt Writing 1 to thi...

Page 1393: ...Register Field Descriptions Bit Field Type Reset Description 31 2 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 1 TXDMAE R W 0h Transmit DMA enable If this bit is set to 1 DMA for the transmit FIFO is enabled 0 RXDMAE R W 0h Receive DMA enable If this bit is set to 1 DMA for the receive FIFO is enabled ...

Page 1394: ...erface Topic Page 21 1 Inter Integrated Circuit Interface 1396 21 2 Block Diagram 1396 21 3 Functional Description 1397 21 4 Initialization and Configuration 1408 21 5 I2 C Registers 1409 1394 SWCU117C February 2015 Revised September 2015 Inter Integrated Circuit I2 C Interface Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 1395: ...the bus The CC26xx and CC13xx devices include one I2 C module with the following features Devices on the I2 C bus can be designated as either a master or a slave Supports both transmitting and receiving data as either a master or a slave Supports simultaneous master and slave operation Four I2 C modes Master transmit Master receive Slave transmit Slave receive Two transmission speeds standard 100 ...

Page 1396: ... releases the clock SCL 21 3 1 1 Start and Stop Conditions The protocol of the I2 C bus defines two states to begin and end a transaction Start and Stop A high to low transition on the SDA line while the SCL is high is defined as a Start condition and a low to high transition on the SDA line while the SCL line is high is defined as a Stop condition The bus is considered busy after a Start conditio...

Page 1397: ... the message A 0 in the R S position of the first byte means that the master transmits sends data to the selected slave and a 1 in this position means that the master receives data from the slave Figure 21 5 R S Bit in First Byte 21 3 1 3 Data Validity The SDA line must contain stable data during the high period of the clock and the data line can change only when SCL is low see Figure 21 6 Figure ...

Page 1398: ...selected using a value in the I2 C Master Timer Period I2C MTPR register that results in an SCL frequency of 100 kbps for standard mode or 400 kbps for fast mode The I2 C clock rate is determined by the parameters CLK_PRD TIMER_PRD SCL_LP and SCL_HP where CLK_PRD is the system clock period TIMER_PRD is the programmed value in the I2C MTPR register SCL_LP is the low phase of SCL fixed at 6 SCL_HP i...

Page 1399: ...s Register I2C MRIS 21 3 3 2 I2 C Slave Interrupts The slave module can generate an interrupt when data is received or requested This interrupt is enabled by setting the in the I2 C Slave Interrupt Mask Register I2C SIMR Software determines whether the module must write transmit or read receive data from the I2 C Slave Data Register I2C SDR DATAIM bit by checking the RREQ and TREQ bits of the I2 C...

Page 1400: ...be omitted in a single master system Functional Description www ti com 21 3 5 1 I2 C Master Command Sequences Figure 21 7 through Figure 21 12 show the command sequences available for the I2 C master Figure 21 7 Master Single TRANSMIT 1400 SWCU117C February 2015 Revised September 2015 Inter Integrated Circuit I2 C Interface Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporate...

Page 1401: ... service Yes No Yes No Yes No Sequence may be omitted in a single master system Read data from I2C_MDR www ti com Functional Description Figure 21 8 Master Single RECEIVE 1401 SWCU117C February 2015 Revised September 2015 Inter Integrated Circuit I2 C Interface Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 1402: ... Write data to I2C_MDR BUSY bit 0 Write 0 t 001 to I2C_MCTRL Write 0 t 101 to I2C_MCTRL Read I2C_MSTAT Write data to I2C_MDR Error serivce Write 0 t 100 to I2C_MCTRL No No Yes Yes Yes No Yes No Functional Description www ti com Figure 21 9 Master TRANSMIT With Repeated Start Condition 1402 SWCU117C February 2015 Revised September 2015 Inter Integrated Circuit I2 C Interface Submit Documentation Fe...

Page 1403: ...USY bit 0 Write 0 1001 to I2C_MCTRL Write 0 101 to I2C_MCTRL Read I2C_MSTAT Read data from I2C_MDR Error serivce Write 0 100 to I2C_MCTRL No No Yes Yes Yes No Read data from I2C_MDR No Yes Yes www ti com Functional Description Figure 21 10 Master RECEIVE With Repeated Start Condition 1403 SWCU117C February 2015 Revised September 2015 Inter Integrated Circuit I2 C Interface Submit Documentation Fee...

Page 1404: ...ive mode Repeated Start condition is generated with changing data direction Functional Description www ti com Figure 21 11 Master RECEIVE With Repeated Start After TRANSMIT With Repeated Start Condition 1404 SWCU117C February 2015 Revised September 2015 Inter Integrated Circuit I2 C Interface Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 1405: ...mit mode Repeated Start condition is generated with changing data direction www ti com Functional Description Figure 21 12 Master TRANSMIT With Repeated Start After RECEIVE With Repeated Start Condition 1405 SWCU117C February 2015 Revised September 2015 Inter Integrated Circuit I2 C Interface Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 1406: ...data to I2C_SDR Functional Description www ti com 21 3 5 2 I2 C Slave Command Sequences Figure 21 13 shows the command sequence available for the I2 C slave Figure 21 13 Slave Command Sequence 1406 SWCU117C February 2015 Revised September 2015 Inter Integrated Circuit I2 C Interface Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 1407: ...ster with the correct value The value written to the I2C MTPR register represents the number of system clock periods in one SCL clock period The TPR value is determined by Equation 8 through Equation 10 TPR PERDMACLK 2 SCL_LP SCL_HP SCL_CLK 1 8 TPR 24 MHz 2 6 4 100000 1 9 TPR 11 10 Write the I2C MTPR register with the value of 0x0000 000B 5 Specify the slave address of the master and that the next...

Page 1408: ...ion 21 5 1 6 14h SMIS Slave Masked Interrupt Status Section 21 5 1 7 18h SICR Slave Interrupt Clear Section 21 5 1 8 800h MSA Master Salve Address Section 21 5 1 9 804h MSTAT Master Status Section 21 5 1 10 804h MCTRL Master Control Section 21 5 1 11 808h MDR Master Data Section 21 5 1 12 80Ch MTPR I2C Master Timer Period Section 21 5 1 13 810h MIMR Master Interrupt Mask Section 21 5 1 14 814h MRI...

Page 1409: ...8 7 6 5 4 3 2 1 0 RESERVED OAR R 0h R W 0h Table 21 3 SOAR Register Field Descriptions Bit Field Type Reset Description 31 7 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 6 0 OAR R W 0h I2C slave own address This field specifies bits a6 through a0 of the slave address 1409 SWCU117C February 2015 Revised...

Page 1410: ... R 0h First byte received 0 The first byte has not been received 1 The first byte following the slave s own address has been received This bit is only valid when the RREQ bit is set and is automatically cleared when data has been read from the SDR register Note This bit is not used for slave transmit operations 1 TREQ R 0h Transmit request 0 No outstanding transmit request 1 The I2C controller has...

Page 1411: ...19 18 17 16 RESERVED W 0h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED DA W 0h W 0h Table 21 5 SCTL Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED W 0h Software must not rely on the value of a reserved field Writing any other value may result in undefined behavior 0 DA W 0h Device active 0 Disables the I2C slave operation 1 Enables the I2C slave operation 1411 SWCU117...

Page 1412: ...eset Description 31 8 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 7 0 DATA R W 0h Data for transfer This field contains the data for transfer during a slave receive or transmit operation When written the register data is used as transmit data When read this register returns the last data received Data...

Page 1413: ...or 2 STOPIM R W 0h Stop condition interrupt mask 0 The SRIS STOPRIS interrupt is suppressed and not sent to the interrupt controller 1 The SRIS STOPRIS interrupt is enabled and sent to the interrupt controller 0h Disable Interrupt 1h Enable Interrupt 1 STARTIM R W 0h Start condition interrupt mask 0 The SRIS STARTRIS interrupt is suppressed and not sent to the interrupt controller 1 The SRIS START...

Page 1414: ...ue of a reserved Writing any other value than the reset value may result in undefined behavior 2 STOPRIS R 0h Stop condition raw interrupt status 0 No interrupt 1 A Stop condition interrupt is pending This bit is cleared by writing a 1 to SICR STOPIC 1 STARTRIS R 0h Start condition raw interrupt status 0 No interrupt 1 A Start condition interrupt is pending This bit is cleared by writing a 1 to SI...

Page 1415: ...result in undefined behavior 2 STOPMIS R 0h Stop condition masked interrupt status 0 An interrupt has not occurred or is masked disabled 1 An unmasked Stop condition interrupt is pending This bit is cleared by writing a 1 to the SICR STOPIC 1 STARTMIS R 0h Start condition masked interrupt status 0 An interrupt has not occurred or is masked disabled 1 An unmasked Start condition interrupt is pendin...

Page 1416: ... Bit Field Type Reset Description 31 3 RESERVED W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 2 STOPIC W 0h Stop condition interrupt clear Writing 1 to this bit clears SRIS STOPRIS and SMIS STOPMIS 1 STARTIC W 0h Start condition interrupt clear Writing 1 to this bit clears SRIS STARTRIS SMIS STARTMIS 0 DATAIC W ...

Page 1417: ...SA Register Field Descriptions Bit Field Type Reset Description 31 8 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 7 1 SA R W 0h I2C master slave address Defines which slave is addressed for the transaction in master mode 0 RS R W 0h Receive or Send This bit field specifies if the next operation is a re...

Page 1418: ... arbitration 1 The I2C controller lost arbitration 3 DATACK_N R 0h Data Was Not Acknowledge 0 The transmitted data was acknowledged 1 The transmitted data was not acknowledged 2 ADRACK_N R 0h Address Was Not Acknowledge 0 The transmitted address was acknowledged 1 The transmitted address was not acknowledged 1 ERR R 0h Error 0 No error was detected on the last operation 1 An error occurred on the ...

Page 1419: ...ister Field Descriptions Bit Field Type Reset Description 31 4 RESERVED W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 3 ACK W 0h Data acknowledge enable 0 The received data byte is not acknowledged automatically by the master 1 The received data byte is acknowledged automatically by the master This bit field mus...

Page 1420: ...tion 0 RUN W 0h I2C master enable 0 The master is disabled 1 The master is enabled to transmit or receive data 0h Disable Master 1h Enable Master 1420 SWCU117C February 2015 Revised September 2015 Inter Integrated Circuit I2 C Interface Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 1421: ...14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED DATA R 0h R W 0h Table 21 14 MDR Register Field Descriptions Bit Field Type Reset Description 31 8 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 7 0 DATA R W 0h When Read Last RX Data is returned When Written Data is transferred during TX transaction 1421 SWCU...

Page 1422: ...y on the value of a reserved Writing any other value than the reset value may result in undefined behavior 7 TPR_7 R W 0h Must be set to 0 to set TPR If set to 1 a write to TPR will be ignored 6 0 TPR R W 1h SCL clock period This field specifies the period of the SCL clock SCL_PRD 2 1 TPR SCL_LP SCL_HP CLK_PRD where SCL_PRD is the SCL line period I2C clock TPR is the timer period register value ra...

Page 1423: ...Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 IM R W 0h Interrupt mask 0 The MRIS RIS interrupt is suppressed and not sent to the interrupt controller 1 The master interrupt is sent to the interrupt controller when the MRIS RIS is set 0...

Page 1424: ...VED RIS R 0h R 0h Table 21 17 MRIS Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 RIS R 0h Raw interrupt status 0 No interrupt 1 A master interrupt is pending This bit is cleared by writing 1 to the MICR IC bit 1424 SWCU117C February 201...

Page 1425: ...RVED MIS R 0h R 0h Table 21 18 MMIS Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 MIS R 0h Masked interrupt status 0 An interrupt has not occurred or is masked 1 A master interrupt is pending This bit is cleared by writing 1 to the MICR...

Page 1426: ...RVED IC W 0h W 0h Table 21 19 MICR Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 IC W 0h Interrupt clear Writing 1 to this bit clears MRIS RIS and MMIS MIS Reading this register returns no meaningful data 1426 SWCU117C February 2015 Rev...

Page 1427: ...SERVED R W 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 5 SFE R W 0h I2C slave function enable 0h Slave mode is disabled 1h Slave mode is enabled 4 MFE R W 0h I2C master function enable 0h Master mode is disabled 1h Master mode is enabled 3 1 RESERVED R 0h Software must not rely on the value of a reserved Writing...

Page 1428: ...Audio Interface 1430 22 3 Frame Configuration 1431 22 4 Pin Configuration 1431 22 5 Clock Configuration 1431 22 6 Serial Interface Formats 1432 22 7 Memory Interface 1435 22 8 Samplestamp Generator 1436 22 9 Usage 1439 22 10 I2S Registers 1441 1428 Integrated Interchip Sound I2S Module SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Texas Instruments Inco...

Page 1429: ...y The period from one positive WCLK edge to the next positive WCLK edge is called a frame Depending on the interface format a frame may consist of one or two phases Data is sampled on one edge of BCLK and updated on the opposite edge The frequency of BCLK may be any multiple of the frequency of WCLK but the number of BCLK periods within a frame must at least be equal to the number of bits produced...

Page 1430: ...s interval is determined by the I2S AIFFMTCFG WORD_LEN register 8 to 24 BCLK cycles In dual phase mode the I2S IRQFLAGS WCLK_ERR register is asserted if two WCLK edges are less than four BCLK cycles apart Similarly in the single phase mode the I2S IRQFLAGS WCLK_ERR register is asserted if a new WCLK edge occurs before the last channel is started 3 IDLE is the inactive period between the last word ...

Page 1431: ...WCLK is high WDIV 7 0 unsigned 1 to 255 BCLK periods and low WDIV 15 8 unsigned 1 to 255 BCLK periods WCLK MCUCLK BDIV WDIV 7 0 WDIV 15 8 13 22 6 Serial Interface Formats The interface supports the dual phase formats I2S LJF and RJF which support one or two audio channels per ADx pin The I2S module also supports the single phase format DSP which supports up to eight audio channels per ADx pin 22 6...

Page 1432: ... this number When there is an IDLE period at the end of the clock phase MSB of the next sample is output during this interval Figure 22 5 LJF Interface Format 22 6 3 Right Justified RJF Figure 22 6 shows the RJF interface format RJF is a dual phase format I2S AIFFMTCFG DUAL_PHASE 1 with a 50 WCLK duty cycle and LSB of each sample word aligned with the edge of WCLK For any given sample the left cha...

Page 1433: ...d by setting I2S AIFFMTCFG SMPL_EDGE 0 There is an optional IDLE period at the end of the clock phase between the last data channel and the next WCLK period logical 0 is output during this period The number of BCLK cycles in the phase must be equal to or higher than the word length as specified in the I2S AIFFMTCFG WORD_LEN register times the number of specified channels determined by the most sig...

Page 1434: ...ansferred in a double locked transfer consisting of one 8 bit word and one 16 bit word in the appropriate order The addresses written to the I2S AIFINPTRNEXT and the I2S AIFOUTPTRNEXT registers do not have to be word aligned Samples on the serial interface and in memory are always aligned by MSB If the source is longer than the destination the words are truncated If the source is shorter than the ...

Page 1435: ...e I2S AIFOUTPTR registers increase for each memory access When a block is finished the following occurs Input memory interface block I2S AIFINPTR I2S AIFINPTRNEXT I2S AIFINPTRNEXT NULL I2S IRQFLAGS AIF_DMA_IN is set Output memory interface block I2S AIFOUTPTR I2S AIFOUTPTRNEXT I2S AIFOUTPTRNEXT NULL I2S IRQFLAGS AIF_DMA_OUT is set The interrupt or alternatively the I2S AIFINPTRNEXT and the I2S AIF...

Page 1436: ...MPWCNT register The lower part of Figure 22 8 shows the part of the samplestamp generator that is used by the I2S module to control the I O pins on the serial audio interface The upper part of Figure 22 8 inside the dotted line includes optional functionality in the form of capturing registers which can be used for example in real time streaming applications to achieve fixed latency and I2S synchr...

Page 1437: ...lestamp Capturing A pulse on samplestamp_req captures the XOSC and WCLK counter values for later retrieval I2S STMPXCNTCAPTn the XOSC counter at time of capture I2S STMPXPER the number of XOSC cycles in the previous WCLK period I2S STMPWCNTCAPTn the WCLK counter at time of capture The samplestamp value used is a fixed point number INT FRAC where INT I2S STMPWCNTCAPTn FRAC I2S STMPXCNTCAPTn and I2S...

Page 1438: ... is started 6 Enable the samplestamp generator Set I2S STMPCTRL STMP_EN 1 Optional steps Poll the I2S STMPWCNT register and wait until the counter value is 2 or higher When the value is 2 or higher there are no more false increments as described in Section 22 8 1 Counters and Registers When the value is 4 or higher the WCLK period is read out from the I2S STMPXPER register This is used to determin...

Page 1439: ...t interrupt 2 Await next memory interface in out interrupt The I2S module closes down the input output pins after this interrupt because NULL is loaded as pointer The I2S IRQFLAGS PTR_ERR register is set because NULL is loaded as pointer and the I2S module error interrupt is generated 3 Set I2S AIFDMACFG 0 4 Set I2S STMPCTL STMP_EN 0 5 Clear the I2S IRQFLAGS PTR_ERR register 6 Disable the BCLK sou...

Page 1440: ...tor Control Register Section 22 10 1 13 38h STMPXCNTCAPT0 Captured XOSC Counter Value Capture Channel 0 Section 22 10 1 14 3Ch STMPXPER XOSC Period Value Section 22 10 1 15 40h STMPWCNTCAPT0 Captured WCLK Counter Value Capture Channel 0 Section 22 10 1 16 44h STMPWPER WCLK Counter Period Value Section 22 10 1 17 48h STMPINTRIG WCLK Counter Trigger Value for Input Pins Section 22 10 1 18 4Ch STMPOU...

Page 1441: ...h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 2 WCLK_INV R W 0h Inverts WCLK source pad or internal when set 0 Not inverted 1 Inverted 1 0 WCLK_SRC R W 0h Selects WCLK source for AIF must be the same as the BCLK source The BCLK source is defined in the PRCM I2SBCLKSEL SRC 0h None 0 1h External WCLK generator from p...

Page 1442: ...it Field Type Reset Description 31 8 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 7 0 END_FRAME_IDX R W 0h Defines the length of the Writing a nonzero value to this register field enables and initializes AIF Note that before doing so all other configuration must have been done and AIFINPTR AIFOUTPTR mu...

Page 1443: ... R W 0h Configures the AD2 audio data pin usage 0x3 Reserved 0h Not in use disabled 1h Input mode 2h Output mode 7 6 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 5 4 AD1 R W 0h Configures the AD1 audio data pin usage 0x3 Reserved 0h Not in use disabled 1h Input mode 2h Output mode 3 2 RESERVED R 0h Sof...

Page 1444: ... logical 0 will be output until the data delay has expired 7 MEM_LEN_24 R W 0h The size of each word stored to or loaded from memory 0h 16BIT 16 bit one 16 bit access per sample 1h 24BIT 24 bit one 8 bit and one 16 bit locked access per sample 6 SMPL_EDGE R W 1h On the serial audio interface data and wclk is sampled and clocked out on opposite edges of BCLK 0h Data is sampled on the negative edge ...

Page 1445: ... word in the frame A frame can contain up to 8 channels Channels that are not included in the mask will not be sampled and stored in memory and clocked out as 0 In dual phase mode only the two LSBs are considered For a stereo configuration set both bits For a mono configuration set bit 0 only In mono mode only channel 0 will be sampled and stored to memory and channel 0 will be repeated when clock...

Page 1446: ...ord in the frame A frame can contain up to 8 channels Channels that are not included in the mask will not be sampled and stored in memory and clocked out as 0 In dual phase mode only the two LSBs are considered For a stereo configuration set both bits For a mono configuration set bit 0 only In mono mode only channel 0 will be sampled and stored to memory and channel 0 will be repeated when clocked...

Page 1447: ...ord in the frame A frame can contain up to 8 channels Channels that are not included in the mask will not be sampled and stored in memory and clocked out as 0 In dual phase mode only the two LSBs are considered For a stereo configuration set both bits For a mono configuration set bit 0 only In mono mode only channel 0 will be sampled and stored to memory and channel 0 will be repeated when clocked...

Page 1448: ...tware must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 15 0 PULSE_WIDTH R W 0h The value written to this register determines the width of the active high PWM pulse pwm_debug which starts together with MSB of the first output word in a DMA buffer 0x0000 Constant low 0x0001 Width of the pulse number of BCLK cycles here 1 0xFFFE Wi...

Page 1449: ...d to the DMA controller to start on the next buffer This event is signalized by aif_dma_in_irq At startup the value must be written once before and once after configuring the DMA buffer size in AIFDMACFG The next pointer must be written to this register while the DMA function uses the previously written pointer If not written in time IRQFLAGS PTR_ERR will be raised and all input pins will be disab...

Page 1450: ...17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PTR R W 0h Table 22 11 AIFINPTR Register Field Descriptions Bit Field Type Reset Description 31 0 PTR R W 0h Value of the DMA input buffer pointer currently used by the DMA controller Incremented by 1 byte or 2 word for each AHB access 1450 Integrated Interchip Sound I2S Module SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback C...

Page 1451: ...art on the next buffer This event is signalized by aif_dma_out_irq At startup the value must be written once before and once after configuring the DMA buffer size in AIFDMACFG At this time the first two samples will be fetched from memory The next pointer must be written to this register while the DMA function uses the previously written pointer If not written in time IRQFLAGS PTR_ERR will be rais...

Page 1452: ... 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PTR R W 0h Table 22 13 AIFOUTPTR Register Field Descriptions Bit Field Type Reset Description 31 0 PTR R W 0h Value of the DMA output buffer pointer currently used by the DMA controller Incremented by 1 byte or 2 word for each AHB access 1452 Integrated Interchip Sound I2S Module SWCU117C February 2015 Revised September 2015 Submit Documentation Feedbac...

Page 1453: ...e reset value may result in undefined behavior 2 OUT_RDY R 0h Low until the output pins are ready to be started by the samplestamp generator When started that is STMPOUTTRIG equals the WCLK counter the bit goes back low 1 IN_RDY R 0h Low until the input pins are ready to be started by the samplestamp generator When started that is STMPINTRIG equals the WCLK counter the bit goes back low 0 STMP_EN ...

Page 1454: ...value may result in undefined behavior 15 0 CAPT_VALUE R 0h The value of the samplestamp XOSC counter STMPXCNT CURR_VALUE last time an event was pulsed event source selected in EVENT I2SSTMPSEL0 EV for channel 0 This number corresponds to the number of 24 MHz clock cycles since the last positive edge of the selected WCLK The value is cleared when STMPCTL STMP_EN 0 Note Due to buffering and synchro...

Page 1455: ...d Type Reset Description 31 16 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 15 0 VALUE R 0h The number of 24 MHz clock cycles in the previous WCLK period that is the next value of the XOSC counter at the positive WCLK edge had it not been reset to 0 The value is cleared when STMPCTL STMP_EN 0 1455 SWCU...

Page 1456: ...t not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 15 0 CAPT_VALUE R 0h The value of the samplestamp WCLK counter STMPWCNT CURR_VALUE last time an event was pulsed event source selected in EVENT I2SSTMPSEL0 EV for channel 0 This number corresponds to the number of positive WCLK edges since the samplestamp generator was enabled not ta...

Page 1457: ...ED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 15 0 VALUE R W 0h Used to define when STMPWCNT is to be reset so number of WCLK edges are found for the size of the sample buffer This is thus a modulo value for the WCLK counter This number must correspond to the size of the sample buffer used by the system that ...

Page 1458: ...15 0 IN_START_WCNT R W 0h Compare value used to start the incoming audio streams This bit field shall equal the WCLK counter value during the WCLK period in which the first input word s are sampled and stored to memory that is the sample at the start of the very first DMA input buffer The value of this register takes effect when the following conditions are met One or more pins are configured as i...

Page 1459: ...ust equal the WCLK counter value during the WCLK period in which the first output word s read from memory are clocked out that is the sample at the start of the very first DMA output buffer The value of this register takes effect when the following conditions are met One or more pins are configured as outputs in AIFDIRCFG AIFDMACFG has been configured for the correct buffer size and 32 BCLK cycle ...

Page 1460: ...R W 0h Table 22 21 STMPWSET Register Field Descriptions Bit Field Type Reset Description 31 16 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 15 0 VALUE R W 0h WCLK counter modification Sets the running WCLK counter equal to the written value 1460 Integrated Interchip Sound I2S Module SWCU117C February 2...

Page 1461: ...eset Description 31 16 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 15 0 VALUE_INC R W 0h WCLK counter modification Adds the written value to the running WCLK counter If a positive edge of WCLK occurs at the same time as the operation this will be taken into account To add a negative value write STMPWP...

Page 1462: ...ust not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 15 0 VALUE R W FFFFh Each time STMPXPER is updated the value is also loaded into this register provided that the value is smaller than the current value in this register When written the register is reset to 0xFFFF 65535 regardless of the value written The minimum value can be used...

Page 1463: ...ESERVED CURR_VALUE R 0h R 0h Table 22 24 STMPWCNT Register Field Descriptions Bit Field Type Reset Description 31 16 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 15 0 CURR_VALUE R 0h Current value of the WCLK counter 1463 SWCU117C February 2015 Revised September 2015 Integrated Interchip Sound I2S Modu...

Page 1464: ...LUE R 0h R 0h Table 22 25 STMPXCNT Register Field Descriptions Bit Field Type Reset Description 31 16 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 15 0 CURR_VALUE R 0h Current value of the XOSC counter latched when reading STMPWCNT 1464 Integrated Interchip Sound I2S Module SWCU117C February 2015 Revis...

Page 1465: ...ALUE R 0h R 0h Table 22 26 STMPXCNTCAPT1 Register Field Descriptions Bit Field Type Reset Description 31 16 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 15 0 CAPT_VALUE R 0h Channel 1 is idle and can not be sampled from an external pulse as with Channel 0 STMPXCNTCAPT0 1465 SWCU117C February 2015 Revis...

Page 1466: ...ALUE R 0h R 0h Table 22 27 STMPWCNTCAPT1 Register Field Descriptions Bit Field Type Reset Description 31 16 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 15 0 CAPT_VALUE R 0h Channel 1 is idle and can not be sampled from an external event as with Channel 0 STMPWCNTCAPT0 1466 Integrated Interchip Sound I...

Page 1467: ...han the reset value may result in undefined behavior 5 AIF_DMA_IN R W 0h Defines the masks state for the interrupt of IRQFLAGS AIF_DMA_IN 0 Disable 1 Enable 4 AIF_DMA_OUT R W 0h Defines the masks state for the interrupt of IRQFLAGS AIF_DMA_OUT 0 Disable 1 Enable 3 WCLK_TIMEOUT R W 0h Defines the masks state for the interrupt of IRQFLAGS WCLK_TIMEOUT 0 Disable 1 Enable 2 BUS_ERR R W 0h Defines the ...

Page 1468: ...nly be cleared by software by writing 1 to IRQCLR WCLK_TIMEOUT 2 BUS_ERR R 0h Set when a DMA operation is not completed in time that is audio output buffer underflow or audio input buffer overflow This error requires a complete restart since word synchronization has been lost The bit is sticky and may only be cleared by software by writing 1 to IRQCLR BUS_ERR Note that DMA initiated transactions t...

Page 1469: ...g any other value than the reset value may result in undefined behavior 5 AIF_DMA_IN W 0h 1 Sets the interrupt of IRQFLAGS AIF_DMA_IN unless a auto clear criteria was given at the same time in which the set will be ignored 4 AIF_DMA_OUT W 0h 1 Sets the interrupt of IRQFLAGS AIF_DMA_OUT unless a auto clear criteria was given at the same time in which the set will be ignored 3 WCLK_TIMEOUT W 0h 1 Se...

Page 1470: ...at the same time in which the clear will be ignored 4 AIF_DMA_OUT W 0h 1 Clears the interrupt of IRQFLAGS AIF_DMA_OUT unless a set criteria was given at the same time in which the clear will be ignored 3 WCLK_TIMEOUT W 0h 1 Clears the interrupt of IRQFLAGS WCLK_TIMEOUT unless a set criteria was given at the same time in which the clear will be ignored 2 BUS_ERR W 0h 1 Clears the interrupt of IRQFL...

Page 1471: ...automation The application software interfaces and interoperates with the radio firmware using shared memory interface system RAM or radio RAM and specific handshake hardware radio doorbell Topic Page 23 1 RF Core 1473 23 2 Radio Doorbell 1474 23 3 RF Core HAL 1478 23 4 Data Queue Usage 1518 23 5 IEEE 802 15 4 1522 23 6 Bluetooth Low Energy 1545 23 7 Proprietary Radio 1578 23 8 Radio Registers 160...

Page 1472: ...fulfill them These requests are basically oriented to the transmission and reception of information through the radio channel but can also include additional maintenance tasks such as calibration test or debug features As a general framework the transactions between the system CPU and the RF core operate as follows The RF core can access data and configuration parameters from the system RAM This r...

Page 1473: ...to modulated signals and vice versa 23 2 Radio Doorbell The radio doorbell module RFC_DBELL is the primary means of communication between the system CPU and the radio CPU also known as command and packet engine CPE The radio doorbell contains a set of dedicated registers parameters in any of the RAMs of the device and a set of interrupts to both the radio CPU and to the system CPU In addition para...

Page 1474: ...h should be cleared when the interrupt has been processed See Section 23 3 2 for the format of the command and status registers 23 2 2 RF Core Interrupts The RF core has four interrupt lines to the ARM Cortex M3 see Figure 23 2 The following interrupts are controlled by the radio doorbell module RF_CPE0 interrupt number 9 RF_CPE1 interrupt number 2 RF_HW interrupt number 10 RF_CMD_ACK interrupt nu...

Page 1475: ... be served this way Clearing bits in RFHWIFG is done by writing 0 to those bits while any bits written to 1 remain unchanged NOTE When clearing bits in RFHWIFG interrupts may be lost if a read modify write operation is done Therefore the same rule applies for the RFHWIFG register as for RFCPEIFG see Section 23 2 2 1 23 2 2 3 RF Core Command Acknowledge Interrupt The system level interrupt RF_CMD_A...

Page 1476: ...Section 23 3 4 14 through Section 23 3 4 15 While disarmed the channel keeps its configuration To disable a channel that is not going to be re armed with the same configuration the CMD_DISABLE_RAT_CH command may be used see Section 23 3 4 12 23 2 3 2 Radio Timer Outputs The RAT module has four controllable outputs RAT_GPO0 through RAT_GPO3 These signals may be controlled by one of the RAT channels...

Page 1477: ...ecides a course of action Three classes of commands are issued Radio operation command Immediate command Direct command For the first two classes of commands CMDR contains a pointer to a command structure This pointer must be a valid pointer with 32 bit word alignment so the 2 least significant bits LSBs must be 0 0 as shown in Figure 23 3 A direct command is signaled by setting the 2 LSBs to 01 a...

Page 1478: ...transmitting or receiving a packet setting up radio hardware registers or doing more complex protocol dependent operations A radio operation command can normally be issued only while the radio is idle An immediate command is a command to change or request status of the radio or to manipulate TX or RX data queues An intermediate command can monitor status such as received signal strength An immedia...

Page 1479: ...ers that are parsed on submission For radio operation commands errors in parameters 0x87 ParError parsed after start of the command are signaled by the command ending and an error is indicated in the status field of that command structure An operation on a data entry queue was attempted but the operation 0x88 QueueError was not supported by the queue in its current state 0x89 QueueBusy An operatio...

Page 1480: ...r TX attempted without the synthesizer being 0x0808 ERROR_NO_FS programmed or powered on 0x0809 ERROR_SYNTH_PROG Synthesizer programming failed 0x080A ERROR_TXUNF Modem TX underflow observed 0x080B ERROR_RXOVF Modem RX overflow observed 0x080C ERROR_NO_RX Data requested from last RX when no such data exists When the system CPU prepares a command structure the CPU must initialize the status field t...

Page 1481: ... be running during this delay and no other radio operation command can be scheduled unless the pending command is aborted or stopped first The system CPU can schedule back to back radio operation commands by using the next operation pointer in any radio operation command This pointer can point to the next command to perform in the chain and by this method complex operations can be made Under some ...

Page 1482: ...command was submitted 4 TRIG_REL_START At a time relative to start of this command not allowed for start triggers 5 TRIG_REL_PREVSTART At a time relative to the start of the previous command 6 TRIG_REL_FIRSTSTART At a time relative to the start of the first command of the chain 7 TRIG_REL_PREVEND At a time relative to the end of the previous command 8 TRIG_REL_EVT1 At a time relative to event 1 of...

Page 1483: ...rig bit is 1 for start triggers timing relative to the start of the command is relative to the programmed start time not the actual start time For an external trigger the radio CPU sets the RAT to use the selected input event as a one capture trigger the CPU then uses this capture interrupt to trigger the action If the event occurs before the setup occurs the event is not captured and the pastTrig...

Page 1484: ...G_NEVER in combination with no command trigger the radio CPU sets the status field to ERROR_START_TRIG If the condition field has an illegal value the radio CPU sets the status field to ERROR_CONDITION If the start trigger occurs in the past and startTrigger pastTrig is 0 the radio CPU sets the status field to ERROR_PAST_START 23 3 2 6 Command Data Structures The data structures are listed in tabl...

Page 1485: ...n 23 3 2 7 Data Entry Structures A data entry must belong to a queue The queues are set up as part of the command structure of a radio operation command Operations on queues available as commands are described in Section 23 3 5 23 3 2 7 1 Data Entry Queue Any command that uses a queue contains a pointer to a data entry queue structure as given in Table 23 9 The system CPU allocates and initializes...

Page 1486: ...atus field may take the following values 0 Pending The entry is not yet in use by the radio CPU This is the status to write by the system CPU before submitting the entry 1 Active The entry is the entry in the queue currently open for writing RX or reading TX by the radio CPU 2 Busy An ongoing radio operation is writing or reading an unfinished packet Certain operations are not allowed while an ent...

Page 1487: ...eration being run 12 7 n RXData R Each entry element may start with a length byte or word An RX entry that is in the ACTIVE or BUSY state may be read by the system CPU but cannot be freed or written to except for data already committed by the radio CPU in other words finished The system CPU may read and modify the data in the RXData buffer up to nextIndex 1 while these bytes are not modified by th...

Page 1488: ...lement committed by the radio CPU Data received Exact format depends on operation being run 12 7 n RXData R Each entry element may start with a length byte or word The entry is updated as follows The nextIndex field is updated as new bytes are written to the buffer While a packet is being received pktStatus bEntryOpen is set to 1 by the radio CPU When an entry element is finished either because th...

Page 1489: ... earlier and the timing is more accurate compared to the first transmitted symbol out of the modem However CPEGPO1 is recommended for control of external PA to avoid turning it on too early The signal RATGPO1 may be configured to go high when sync is found in the receiver and low when the packet is received or reception aborted this does not work for the IEEE 802 15 4 receiver command The RATGPO1 ...

Page 1490: ... Received CMD_ABORT DONE_ABORT ABORT The start trigger occurred in the past with startTrigger pastTrig 0 ERROR_PAST_START ABORT Illegal start trigger parameter ERROR_START_TRIG ABORT Illegal condition for next operation ERROR_CONDITION ABORT Observed illegal parameter ERROR_PAR ABORT Invalid pointer to next operation ERROR_POINTER ABORT Next operation has a command ID that is undefined or not a ra...

Page 1491: ...bias 3 biasMode W 1 External bias 0 Program ADI 0 with default values 4 bNoAdi0Setup W 1 Do not program ADI 0 0 Apply trim values to ADI 0 5 bNoAdi0Trim W 1 Use default values for ADI 0 16 17 config 0 Apply ADI 0 overrides 6 bNoAdi0Ovr W 1 Ignore ADI 0 overrides 0 Program ADI 1 with default values 7 bNoAdi1Setup W 1 Do not program ADI 1 0 Apply trim values to ADI 1 8 bNoAdi1Trim W 1 Use default va...

Page 1492: ...otherwise ignore For ADI 0 registers ignore if config bNoAdi0Ovr 1 otherwise If config bNoAdi0Setup 0 update the prepared values If config bNoAdi0Setup 1 write directly to ADI 0 For ADI 1 registers ignore if config bNoAdi1Ovr 1 otherwise If config bNoAdi1Setup 0 update the prepared values If config bNoAdi1Setup 1 write directly to ADI 1 If mode 0xFF and config bNoAdi0Trim 0 modify the RSSI offset ...

Page 1493: ...egisters with 32 bit values 10 ADI registers 11 Firmware defined parameters Table 23 18 Format of an ADI Register Override Entry Bit Index Bit Field Name Description 0 1 entryType 10 ADI register 2 9 adiValue2 Optional second value to write 10 15 adiAddr2 Optional second ADI bus address 16 23 adiValue Value to write to register 24 29 adiAddr ADI bus address 0 Use full size writes 30 bHalfSize 1 Us...

Page 1494: ...RfFreq to recalculate RX IF 11 bApplyTx If 1 use invRfFreq to recalculate TX shape Value where fRFMHz is center frequency in MHz 12 31 invRfFreq 12 24 220 fRFMHz loDivider Table 23 22 Format of an End of List Entry Bit Index Bit Field Name Description 0 1 entryType 11 Firmware defined parameter 2 3 entrySubType 11 End of list segment 0x0 End of list 0x1 SRAM Base 0x2000 0000 0x2 RF core RAM Base 0...

Page 1495: ...ble 23 18 The ADI to write is selected through adiNo If bHalfSize is 1 the write size bit on the ADI interface is set causing the value to be masked half size otherwise it is a full size write and the LSB of the address is ignored If adiAddr2 is nonzero the value given by adiValue2 is written to the ADI bus address given by adiAddr2 otherwise these two fields are ignored if ADI address 0 is to be ...

Page 1496: ...synthesizer fails the command ends with ERROR_SYNTH_PROG as the status When otherwise finished the command ends with DONE_OK as the status Table 23 23 CMD_FS_POWERUP Command Format Bit Field Byte Index Field Name Bit Index Type Description Name 14 15 Reserved Pointer to a list of hardware and 16 19 pRegOverride W configuration registers to override If NULL no override is used 23 3 3 1 4 CMD_FS_POW...

Page 1497: ...mand ends with ERROR_PAR as the status If the command is called without the radio being configured it ends with ERROR_NO_SETUP as the status If the command is called without the synthesizer being powered up it ends with ERROR_NO_FS as status Table 23 24 CMD_FS Command Format please check the accuracy of this table Byte Index Field Name Bit Index Bit Field Name Type Description The frequency in MHz...

Page 1498: ...sponding to CMD_FS_OFF see Section 23 3 3 1 6 after the operation is done otherwise the synthesizer is left on A trigger to end the operation is set up by endTrigger and endTime see Section 23 3 2 5 1 If the trigger that is defined by this parameter occurs the radio operation ends The operation ends by one of the causes listed in Table 23 14 The command structure for CMD_RX_TEST contains the field...

Page 1499: ... x22 x2 x 1 is used This gives a pseudo noise sequence with length 4294967295 For whitening modes 2 and 3 initialization is done by the radio CPU writing 0xAAAA 0000 to the PRBS value register before transmission starts For whitening mode 1 the default initialization is used The transmitter runs until the trigger set up by endTrigger and endTime see Section 23 3 2 5 1 occurs or until an abort comm...

Page 1500: ...28 CMD_SYNC_START_RAT Command Format Byte Index Field Name Bits Bit Field Name Type Description 14 15 Unused The desired RAT value corresponding to the value the RAT would have had when 16 19 rat0 W the RTC was zero This parameter is returned by CMD_SYNC_STOP_RAT When starting the radio CPU starts the RAT and sets up capture of an RTC tick and waits for this tick then calculates the necessary time...

Page 1501: ...CH_IMM is a radio operation command In addition to the parameters listed in Table 23 8 the command structure contains the fields listed in Table 23 31 Table 23 31 CMD_SCH_IMM Command Format Byte Index Field Name Bits Bit Field Name Type Description 14 15 Reserved 16 19 cmdrVal W Value as would be written to CMDR 20 23 cmdstaVal R Value as would be returned in CMDSTA When starting the radio CPU tak...

Page 1502: ...ecrements the counter field by 1 unless it was already 0 and writes the result back to this field If the result of the decrement is zero the operation ends with the status DONE_COUNTDOWN and the result FALSE Otherwise the operation ends with the status DONE_OK and the result TRUE In this case the next radio operation command to run is given by pNextOpIfOk instead of pNextOp see Table 23 8 which ca...

Page 1503: ... the last committed RX entry element and adding the signed number found in pValue as a byte offset In either case this pointer does not need to be 4 byte aligned if not the value is read byte by byte The value is then subject to the following operations in this order 1 If patternOpt bByteRev 1 interchange byte 3 with byte 0 and byte 1 with byte 2 as if the bytes had been read most significant byte...

Page 1504: ...running no action is taken The result signaled in the CMDSTA register is Done in all cases If a radio operation command was running CMDSTA may be updated before the radio operation has ended 23 3 4 2 CMD_STOP Stop Command Command ID number 0x0402 CMD_STOP is a direct command On reception the radio CPU informs the radio operation command currently running that it has been requested to stop The STOP...

Page 1505: ...dio configuration controlled by the radio CPU and protocol related variables The format is as for CMD_RADIO_SETUP see Section 23 3 3 1 If done while the radio is running the update must primarily be done on the radio and protocol configuration as modifications to hardware registers may cause undesired behavior 23 3 4 5 CMD_TRIGGER Generate Command Trigger Command ID number 0x0404 CMD_TRIGGER is an...

Page 1506: ... as offset from the start of the radio RAM NOTE Some of this free RAM is used for patches provided by TI The availRatCh field is a bitmap where bit position n indicates whether radio timer channel n may be used by the system CPU A bit value of 1 indicates that the corresponding channel may be used by the system CPU while a bit value of 0 means that the channel is reserved for the radio CPU or none...

Page 1507: ...t RAT Channel to Compare Mode Command ID number 0x000A CMD_SET_RAT_CMP is an immediate command that takes the parameters listed in Table 23 41 Table 23 41 CMD_SET_RAT_CMP Command Format Byte Field Name Bits Bit Field Name Type Description Index 0 1 commandNo W The command ID number 2 ratCh W The radio timer channel number 3 Reserved 4 7 compareTime W The time at which the compare occurs On recepti...

Page 1508: ... may be sent as a direct command If so bits 2 15 of the config word are given by bits 2 15 of CMDR bits 0 1 of config are not used The channel number must indicate a channel that is not reserved for use by the radio CPU Otherwise the radio CPU returns ParError in CMDSTA If the channel is successfully set up the radio CPU returns Done in CMDSTA 23 3 4 12 CMD_DISABLE_RAT_CH Disable RAT Channel Comma...

Page 1509: ... 0 1 of config are not used The channel number config ratCh must indicate a channel that is not reserved for use by the radio CPU and the output number config outputSel must not be an output used by the radio CPU Otherwise the radio CPU returns ParError in CMDSTA If the output event is successfully set up the radio CPU returns Done in CMDSTA 23 3 4 14 CMD_ARM_RAT_CH Arm RAT Channel Command ID numb...

Page 1510: ...r channel number On reception the radio CPU disarms the RAT channel given by ratCh CMD_DISABLE_RAT_CH may be sent as a direct command If so ratCh is given by the parameter in bits 8 15 of CMDR The channel number must indicate a channel not reserved for use by the radio CPU Otherwise the radio CPU returns ParError in CMDSTA If the channel number is valid the CPU returns Done in CMDSTA after the cha...

Page 1511: ...tting use value from 2 3 txPower W SmartRF Studio On reception the radio CPU sets the transmit power for use the next time transmission is started If a packet is being transmitted the transmit power is not updated until transmission starts for the next packet Each time transmission of a packet begins temperature compensation of the transmit power is done The radio CPU returns Done in CMDSTA when f...

Page 1512: ...ithout restarting calibration This must be a small change compared to the frequency used under calibration otherwise the synthesizer is most likely unable to relock Extra distortion may occur if the command is done during RX or TX The frequency to use is given by frequency and fractFreq and the frequency must be as close as possible to frequency fractFreq 65536 MHz If the synthesizer is not runnin...

Page 1513: ...ystem bus stays awake even if the system goes to deep sleep which must be done for the RF core to run and access to the system side for one of the following reasons Any command structure data structure and so on pointed to by a pointer sent to the RF core is placed in system RAM or flash The RF core must read the temperature because the TX power has a nonzero temperature coefficient The RF core mu...

Page 1514: ...3 2 7 1 the command fails and the radio CPU sets the result byte of CMDSTA to QueueError 23 3 5 2 CMD_REMOVE_DATA_ENTRY Remove First Data Entry From Queue Command ID number 0x0006 CMD_REMOVE_DATA_ENTRY is an immediate command that takes the parameters listed in Table 23 51 Table 23 51 CMD_REMOVE_DATA_ENTRY Command Format Byte Index Field Name Bits Bit Field Name Type Description 0 1 commandNo W Th...

Page 1515: ...as a success The returned pFirstEntry is NULL in this case 23 3 5 4 CMD_CLEAR_RX Clear All RX Queue Entries Command ID number 0x0008 CMD_CLEAR_RX is an immediate command that takes the parameters listed in Table 23 53 Table 23 53 CMD_CLEAR_RX Command Format Byte Index Field Name Bits Bit Field Name Type Description 0 1 commandNo W The command ID number 2 3 Reserved 4 7 pQueue W Pointer to the queu...

Page 1516: ...e indicated and returns a pointer to the first entry that was removed The radio CPU performs the following operations If pQueue pCurrEntry status Pending then Set pFirstEntry pQueue pCurrEntry Set pQueue pCurrEntry NULL Set pQueue pLastEntry NULL else Set pFirstEntry pQueue pCurrEntry pNextEntry Set pQueue pCurrEntry pNextEntry NULL Set pQueue pLastEntry pQueue pCurrEntry If the pointer pQueue is ...

Page 1517: ...ue is already busy Otherwise the following is done Set pQueue pCurrEntry status Busy Set pEntry pQueue pCurrEntry 23 4 1 2 PROC_FREE_DATA_ENTRY Free Allocated Data Entry The procedure takes the following input parameters Pointer to queue pQueue The procedure returns with error if the specified queue is empty Otherwise the following is done Set pQueue pCurrEntry status Active 23 4 1 3 PROC_FINISH_D...

Page 1518: ...escribes the operations Set pFinishedEntry NULL If pQueue pCurrEntry NULL then Return with no space error end if If pQueue pCurrEntry type 1 then if pQueue pCurrEntry length size then Return with no space error else Set pQueue pCurrEntry status Busy Set pEntry pQueue pCurrEntry end if else Set pTemp pQueue pCurrEntry If pTemp nextIndex 2 size pTemp length then Set pQueue pCurrEntry pTemp pNextEntr...

Page 1519: ...pe 1 then Set pTemp pQueue pCurrEntry Set pQueue pCurrEntry pTemp pNextEntry Set pTemp status Finished else Increase pQueue pCurrEntry nextIndex by size Increment pQueue pCurrEntry numElements by 1 If pQueue pCurrEntry nextIndex 2 pQueue pCurrEntry length then Set pTemp pQueue pCurrEntry Set pQueue pCurrEntry pTemp pNextEntry Set pTemp status Finished Set pFinishedEntry pTemp else Set pQueue pCurr...

Page 1520: ...queue it calls PROC_ALLOCATE_TX to get a pointer to the data to transmit When the packet has been transmitted the radio CPU calls PROC_FINISH_DATA_ENTRY or PROC_FREE_DATA_ENTRY If PROC_FINISH_DATA_ENTRY is called the system CPU gets informed that the entry is finished and may be reused This must be used if re transmission of the packet is not an option If PROC_FREE_DATA_ENTRY is called the transmi...

Page 1521: ...ants of other commands and differ only in that they run in the foreground rather than the background These are defined in Table 23 57 Table 23 57 Common Radio Operation Commands on Foreground Level ID Command Name Description 0x0C10 CMD_FG_SCH_IMM Behaves as CMD_SCH_IMM 0x0C12 CMD_FG_COUNT_BRANCH Behaves as CMD_COUNT_BRANCH 0x0C13 CMD_FG_PATTERN_CHECK Behaves as CMD_PATTERN_CHECK In addition there...

Page 1522: ...of extended address entries 31 numShortEntries W Number of short address entries 32 35 pExtEntryList W Pointer to list of extended address entries 36 39 pShortEntryList W Pointer to list of short address entries 40 47 localExtAddr W The extended address of the local device 48 49 localShortAddr W The short address of the local device 50 51 localPanID W The PAN ID of the local device 52 54 Reserved ...

Page 1523: ...EEE 802 15 4 20 BE R W CSMA CA algorithm The number of remaining periods from a 21 remainingPeriods R W paused backoff countdown 22 lastRssi R RSSI measured at the last CCA operation Trigger that causes the device to end the 23 endTrigger W CSMA CA operation 24 27 lastTimeStamp R Time of the last CCA operation 28 31 endTime W Time parameter for endTrigger Table 23 62 IEEE 802 15 4 TX Command Struc...

Page 1524: ...n Table 23 65 IEEE 802 15 4 Modify Frame Filtering Immediate Command Structure Byte Index Field Name Type Description 0 1 commandNo W The command number New value of frameFiltOpt for the running 2 3 newFrameFiltOpt W background level operation New value of frameTypes for the running 4 newFrameTypes W background level operation Table 23 66 IEEE 802 15 4 Enable or Disable Source Matching Entry Immed...

Page 1525: ... Output Structures Table 23 68 RX Command Byte Index Field Name Type Description 0 nTxAck R W Total number of transmitted ACK frames 1 nRxBeacon R W Number of received beacon frames 2 nRxData R W Number of received data frames 3 nRxAck R W Number of received acknowledgment frames 4 nRxMacCmd R W Number of received MAC command frames 5 nRxReserved R W Number of received frames with reserved frame t...

Page 1526: ...m the source matching algorithm 7 bAppendTimestamp If 1 append a timestamp to the packet in the RX queue Table 23 70 CCA Configuration Bit Field Bits Bit Field Name Description 0 ccaEnEnergy Enable energy scan as CCA source 1 ccaEnCorr Enable correlator based carrier sense as CCA source 2 ccaEnSync Enable sync found based carrier sense as CCA source Operator to use between energy based and correla...

Page 1527: ...e field before frame type filtering 0 No modification 13 14 modifyFtFilter 1 Invert MSB 2 Set MSB to 0 3 Set MSB to 1 0 Accept acknowledgment frames of any length 5 15 bStrictLenFilter 1 Accept only acknowledgment frames of length 5 Table 23 72 Frame Type Filtering Bit Field Bits Bit Field Name Description Treatment of frames with frame type 000 beacon 0 bAcceptFt0Beacon 0 Reject 1 Accept Treatmen...

Page 1528: ...ts for each shortAddrEntry LSB of first word corresponds to entry 0 The array size K ceil N 32 0 4K 1 srcMatchEn R W where N is the number of entries given by numShortEntries see Table 23 59 and ceil denotes rounding upwards Words with pending data bits for each shortAddrEntry LSB of 4K 8K 1 srcPendEn R W first word corresponds to entry 0 Short address number 0 the entry is an address PAN ID pair ...

Page 1529: ...h byte or word is stored if configured in the RX entry by config lenSz and calculated from the length received over the air and the configuration of appended status information The format of the entry elements in the receive queue pointed to by pRxQ is given by the configuration rxConfig defined in Section 23 6 1 4 Following the length field the received PHY header byte is stored if rxConfig bIncl...

Page 1530: ... running at the same time The background level operations are the receive and energy detect scan operations Only one of these can run at a time The foreground level operations are the CSMA CA operation the receive ACK operation the transmit operation the abort background level operation and the modify radio setup operation These can be entered as one command or a command chain even if a background...

Page 1531: ...ration Ending 0x2400 IEEE_DONE_OK Operation ended normally 0x2401 IEEE_DONE_BUSY CSMA CA operation ended with failure 0x2402 IEEE_DONE_STOPPED Operation stopped after stop command 0x2403 IEEE_DONE_ACK ACK packet received with pending data bit cleared 0x2404 IEEE_DONE_ACKPEND ACK packet received with pending data bit set 0x2405 IEEE_DONE_TIMEOUT Operation ended due to timeout 0x2406 IEEE_DONE_BGEND...

Page 1532: ...t packet types Rejection of packets with a nonmatching destination address Rejection of packets with unknown version or illegal fields Automatic identification of source address Automatic acknowledgment transmission Automatic insertion of pending data bit based on source address 23 5 4 1 1 1 Frame Filtering When frame filtering is enabled the MAC header of the packet is investigated by the radio C...

Page 1533: ...e value of the bit in srcPendEn corresponding to the index of the match If no match was found or if frameFiltOpt autoPendEn is 0 the pending data bit is set equal to frameFiltOpt defaultPend If frameFiltOpt bPendDataReqOnly is 1 the radio CPU investigates the frame to determine if it is a MAC command frame with the command frame identifier set to a Data Request If not the pending data bit of an au...

Page 1534: ...n 1 The frame is accepted by frame filtering bIgnore 0 The frame is a data frame or a MAC command frame The destination address is not the broadcast address The ACK request bit of the FCF is set The CRC check is passed bCrcErr 0 The frame fits in the receive queue The transmit time of the ACK packet is timed by the radio CPU depending on frameFiltOpt slottedAckEn If this bit is 0 the ACK packet is...

Page 1535: ...g While the receiver is running the radio CPU monitors some signals for use in clear channel assessment This monitoring is controlled by ccaOpt There are three sources for CCA RSSI above level ccaEnergy carrier sense based on the correlation value ccaCorr and carrier sense based on sync found ccaSync Each of these may have the state BUSY IDLE or INVALID The RSSI above level is maintained by monito...

Page 1536: ... is implemented by setting ccaEnEnergy 1 and ccaEnCorr 1 With CCA mode 3 ccaCorrOp is allowed to be either 0 or 1 this distinguishes between the logical operator AND 1 and OR 0 as described in the IEEE 802 15 4 standard The CCA states and the current RSSI can be read by the system CPU by issuing the immediate command CMD_IEEE_CCA_REQ If a CMD_IEEE_CSMA operation is running in the foreground the ra...

Page 1537: ...proceeding Otherwise the radio CPU draws a pseudo random number in the range 0 to 2 BE 1 where BE is given by Table 23 61 The radio CPU then waits that number of backoff periods from the start trigger before proceeding After this wait time the radio CPU checks the CCA state from the background level operation as in Section 23 5 4 1 5 If the CCA state was INVALID the radio CPU waits before trying a...

Page 1538: ...If randomState is 0 the radio CPU self seeds by initializing the LFSR to the 16 LSBs of the radio timer There is some randomness to this value but this is limited especially for slotted CSMA CA and seeding with a true random number or a pseudo random number based on a true random seed by the system CPU is therefore recommended If the 16 LSBs of the radio timer are all 0 another fixed value is subs...

Page 1539: ...ackoffs Failure CW CWí1 CW 0 Success Check CCA state Wait 1 backoff period Y Y Y Y N N CCA state Invalid N Y N CW initCW N Slotted Y N Wait for RSSI update Slotted Wait for next backoff period boundary Y N www ti com IEEE 802 15 4 Figure 23 7 CSMA CA Operation 1539 SWCU117C February 2015 Revised September 2015 Radio Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 1540: ...on ended IEEE_DONE_BGEND ABORT Observed illegal parameter IEEE_ERROR_PAR ABORT When the operation ends the time of the last CCA check that is the time written into lastTimeStamp is defined as event 1 and may be used for timing subsequent chained operations 23 5 4 4 Transmit Operation The transmit operation is a foreground level operation that transmits one packet The operation is started with the ...

Page 1541: ...ceive ACK operation is a foreground level operation that runs on top of a receive operation The operation starts with the CMD_IEEE_RX_ACK command and uses the command structure listed in Table 23 63 At the start of a receive ACK operation the radio CPU waits for the start trigger If the receiver was suspended due to a TX operation before the receive ACK operation the background level RX operation ...

Page 1542: ...due to one of the causes listed in Table 23 85 The status field of the command structure after the command has ended indicates the reason why the operation ended In all cases an FG_COMMAND_DONE interrupt is raised In each case it is indicated if the result is TRUE FALSE or ABORT This indicates whether to start the next command if any in pNextOp or to return to an IDLE state Table 23 85 End of ABOR...

Page 1543: ...e illegal the radio CPU returns the result ParError in CMDSTA Otherwise the radio CPU returns Done 23 5 5 2 Modify Frame Filtering Parameter Command The CMD_IEEE_MOD_FILT command takes a command structure as defined in Table 23 65 CMD_IEEE_MOD_FILT must only be sent while an RX operation is running On reception the radio CPU modifies the values of frameFiltOpt and frameTypes for the running proces...

Page 1544: ...d is running no action is taken The result signaled in CMDSTA is Done in all cases If a foreground level radio operation command was running CMDSTA may be updated before the radio operation has ended 23 5 5 6 Request CCA and RSSI Information Command The CMD_IEEE_CCA_REQ command takes a command structure as defined in Table 23 67 CMD_IEEE_CCA_REQ must only be sent while an RX or energy detect scan ...

Page 1545: ...les The Byte Index is the offset from the pointer to that structure Multibyte fields are little endian and halfword or word alignment is required For bit numbering 0 is the LSB The R W column is used as follows R The system CPU can read a result back the radio CPU does not read the field W The system CPU writes a value the radio CPU reads it and does not modify the value R W The system CPU writes ...

Page 1546: ...on the connection 19 timeoutTrigger W Trigger that defines timeout of the first receive operation 20 23 timeoutTime W Time parameter for timeoutTrigger 24 26 Reserved Trigger that causes the device to end the connection event 27 endTrigger W as soon as allowed 28 31 endTime W Time parameter for endTrigger Table 23 92 Master Commands Byte Index Field Name Type Description 0 3 pRxQ W Pointer to rece...

Page 1547: ...Q W Pointer to receive queue Configuration bits for the receive queue 4 rxConfig W entries see Table 23 104 for details 0 scanFilterPolicy W The scanner filter policy 0 Passive scan 1 bActiveScan W 1 Active scan The type of the device address public 0 2 deviceAddrType W or random 1 5 scanConfig 3 Reserved 4 bStrictLenFilter W 1 Discard messages with illegal length 5 bAutoWlIgnore W 1 Automatically...

Page 1548: ...dom 1 The type of the peer device address 3 peerAddrType W public 0 or random 1 4 bStrictLenFilter W 1 Discard messages with illegal length 6 Reserved 7 connectReqLen W Size of connect request data Pointer to buffer containing LLData to go in 8 11 pConnectReqData W the CONNECT_REQ Pointer to device address used for this 12 15 pDeviceAddress W device 16 19 pWhiteList W Pointer to white list or peer...

Page 1549: ...e Index Field Name Bits Bit Field Name Type Description Number of packets to transmit 0 1 numPackets W 0 Transmit unlimited number of packets The number of payload bytes in each 2 payloadLength W packet 3 packetType W The packet type to be used Number of radio timer cycles between 4 7 period W the start of each packet 0 Use default packet encoding 0 bOverride W 1 Override packet contents If bOverr...

Page 1550: ...ets received with CRC OK and ignored due to 11 nRxIgnored R W repeated sequence number 12 nRxEmpty R W Number of packets received with CRC OK and no payload Number of packets received and discarded due to lack of buffer 13 nRxBufFull R W space 14 lastRssi R RSSI of last received packet 15 pktStatus R W Status of received packets see Table 23 108 16 19 timeStamp R Slave operation Timestamp of first...

Page 1551: ... not ignored Table 23 101 Initiator Command Byte Index Field Name Type Description 0 nTxConnectReq R W Number of transmitted CONNECT_REQ packets Number of ADV _IND packets received with CRC OK and not 1 nRxAdvOk R W ignored 2 3 nRxAdvIgnored R W Number of ADV _IND packets received with CRC OK but ignored 4 5 nRxAdvNok R W Number of ADV _IND packets received with CRC error Number of ADV _IND packet...

Page 1552: ...1 if the last transmitted packet was an LL control packet LLID 11 6 bLlCtrlAckRx 1 if the last received packet was the ACK of an LL control packet 1 if the last successfully received packet was an LL control packet which 7 bLlCtrlAckPending has not yet been ACK ed Table 23 106 White List Structure 1 Byte Index Field Name Bits Bit Field Name Type Description 0 7 Size W Number of while list entries ...

Page 1553: ...d packet with CRC OK was empty 0 otherwise 5 bLastMd 1 if the last received packet with CRC OK had MD 1 0 otherwise 1 if the last received packet with CRC OK was an ACK of a transmitted 6 bLastAck packet 0 otherwise 7 Reserved 23 6 2 Interrupts The radio CPU signals events back to the system CPU using firmware defined interrupts The interrupts used by the BLE commands are listed in Table 23 109 Ea...

Page 1554: ...f appended information Following the optional length field the received header and payload is stored as received over the air If rxConfig bIncludeLenByte is 1 the full 16 bit header including the received length field is stored despite the length field being redundant information if a length byte or word is present If rxConfig bIncludeLenByte is 0 only the first byte of the header is stored so tha...

Page 1555: ...ng BLE radio operation commands have a BLE compliant CRC appended On all packets received using BLE radio operation commands a BLE compliant CRC check is performed The initialization of the CRC register is defined for each command The radio CPU times transmissions immediately following receptions to fulfill the requirements for T_IFS For reception immediately following transmissions the radio CPU ...

Page 1556: ...ch operation Some of the error causes listed in Table 23 110 are not repeated in these lists In some cases general error causes may occur In all of these cases the result of the operation is ABORT 23 6 4 1 Link Layer Connection At the start of a slave or master operation the radio CPU waits for the start trigger then program the frequency based on the channel parameter of the command structure The...

Page 1557: ...e condition fulfilled after a packet is transmitted or received In the list of conditions the term acknowledgment is used which is defined as a successfully received packet with an NESN value in the header different from the SN value of the last transmitted packet Table 23 112 Conditions for Incrementing Counters and Raising Interrupts for Master and Slave Commands Condition Counter Incremented In...

Page 1558: ...ket the received SN bit is compared to pParams seqStat lastRXSn If a packet is received with correct CRC and the packet fits in an Rx buffer the received SN is stored in pParams seqStat lastRXSn If the packet was an LL control packet LLID 11b and the packet was not to be ignored pParams seqStat bLlCtrlAckPending is set to 1 and an RX_CTRL interrupt is raised If a packet is received with correct CR...

Page 1559: ...ncremented In the header of a transmitted packet the MD bit is set according to the following rules If the transmit queue is empty or the packet being transmitted is the last packet of the transmit queue MD is 0 If the trigger described in pParams endTrigger has occurred MD is 0 If the counter nPkt is 1 MD is 0 Otherwise MD is 1 The pOutput structure contains counters that are updated by the radio...

Page 1560: ... the TX queue or transmits an automatically empty packet if the TX queue is empty The transmission may be a retransmission Unless the operation ends due to the criteria listed in Table 23 113 the receiver starts after the transmission is done A slave operation ends due to one of the causes listed in Table 23 113 The status field of the command structure after the operation is ended indicates the r...

Page 1561: ...vertiser At the start of an advertiser operation of any kind the radio CPU waits for the start trigger then programs the frequency based on the channel parameter of the command structure The channel parameter is not allowed to be in the range 0 36 as these are data channels The radio CPU sets up the advertising channel access address and uses the CRC initialization value 0x55 5555 The whitener is ...

Page 1562: ...compared against the peer address as described in Section 23 6 4 4 2 Depending on this the actions taken are as given in Table 23 116 where the definition of each action including the value used on bCrcErr and bIgnore is given in Table 23 117 If pParams advConfig bStrictLenFilter is 1 only length fields that are compliant with the BLE specification are considered valid For a SCAN_REQ that means a ...

Page 1563: ...sult is FALSE This can for instance be used to stop execution instead of proceeding with the next chained operation by use of the condition in the command structure If the immediate command CMD_STOP is received by the radio CPU it has the same meaning as the end trigger occurring except that the status code after ending is CMD_DONE_STOPPED The output structure pOutput contains fields which give in...

Page 1564: ... the type defined in Table 23 93 and a pOutput parameter of the type defined in Table 23 99 The operation starts with transmission and operates as described in Section 23 6 4 4 with some modifications as described in the following For the directed advertiser pParams pWhiteList points to a buffer containing only the device address of the device to connect to The address type of the peer is given in...

Page 1565: ...3 and a pOutput parameter of the type defined in Table 23 99 The operation starts with transmission and operates as described in Section 23 6 4 4 After transmission of an ADV_NONCONN_IND the operation ends without any receive operation An advertiser operation that is not connectable ends with one of the statuses listed in Table 23 120 The status field of the command structure after the operation i...

Page 1566: ...or the start trigger then programs the frequency based on the channel parameter of the command structure The channel parameter is not allowed to be in the range 0 36 as these are data channels The radio CPU sets up the advertising channel access address and uses the CRC initialization value 0x55 5555 The whitener is set up as defined in the whitening parameter The radio CPU then configures the rec...

Page 1567: ...No X N A X 2 ADV_NONCONN_IND OK X Yes X N A X 1 ADV_NONCONN_IND NOK X X X N A X 4 ADV_DIRECT_IND OK 1 No No X X 1 ADV_DIRECT_IND OK 1 No Yes No X 1 ADV_DIRECT_IND OK 1 No Yes Yes X 2 ADV_DIRECT_IND OK 0 No X No X 1 ADV_DIRECT_IND OK 0 No X Yes X 2 ADV_DIRECT_IND OK X Yes X X X 1 ADV_DIRECT_IND NOK X X X X X 4 ADV _IND with invalid length X X X X X X 5 Other X X N A N A N A X 5 Table 23 123 Descrip...

Page 1568: ...eader is checked once it is received and if it is not a SCAN_RSP message the demodulator is stopped immediately If it is a SCAN_RSP message then it is received into the RX queue Depending on the received SCAN_RSP the values of bCrcErr and bIgnore are as given in Table 23 124 If pParams scanConfig bStrictLenFilter is 1 only length fields that are compliant with the BLE specification are considered ...

Page 1569: ...o CPU it has the same meaning as the end trigger occurring except that the status code after ending is CMD_DONE_STOPPED The differences between the two triggers are the status and result at the end of the operation Typically timeoutTrigger can be used at the end of a scan window while endTrigger can be used when scanning is to end entirely The output structure pOutput contains fields which give in...

Page 1570: ...23 94 and a pOutput parameter of the type defined in Table 23 100 At the start of an initiator operation the radio CPU waits for the start trigger then programs the frequency based on the channel parameter of the command structure The channel parameter is not allowed to be in the range 0 36 as these are data channels The radio CPU sets up the advertising channel access address and uses the CRC ini...

Page 1571: ...The payload starts with the 6 byte device address read from pParams pDeviceAddress followed by the 6 byte peer address read from the AdvA field of the received message The rest of the payload is read from the pParams pConnectData buffer If pParams initConfig bDynamicWinOffset is 1 the radio CPU replaces the bytes in the WinSize and WinOffset position with a calculated value as explained below Afte...

Page 1572: ...imeStamp is set to a timestamp of the start of the packet If an ADV _IND packet is received with CRC OK and the bIgnore flag set nRXAdvIgnored is incremented and an RX_IGNORED interrupt is raised If an ADV _IND packet is received with CRC error nRXAdvNok is incremented and an RX_NOK interrupt is raised If an ADV _IND packet is received and did not fit in the RX queue nRXAdvBufFull is incremented a...

Page 1573: ...s as soon as possible If the trigger occurs while waiting for sync the operation ends immediately If the trigger occurs at another time the operation continues until the current packet has been fully received and then ends If the immediate command CMD_STOP is received by the radio CPU it has the same meaning as the end trigger occurring except that the status code after ending is CMD_DONE_STOPPED ...

Page 1574: ...ialization value 0x55 5555 The whitener is set up as defined in the whitening parameter To produce PHY test packets conforming to the BLE Test Specification the whitener must be disabled The radio CPU transmits pParams numPackets packets then ends the operation If pParams numPackets is 0 transmission continues until the operation ends for another reason timeout stop or abort command The time numbe...

Page 1575: ...e radio CPU it has the same meaning as the end trigger occurring except that the status code after ending is CMD_DONE_STOPPED The output structure pOutput contains only the field nTX and is incremented each time a packet has been transmitted The radio CPU does not initialize the field so this must be done by the system CPU when a reset of the counters is desired A TX_DONE interrupt is raised each ...

Page 1576: ... to configure the radio CPU to automatically set the bWlIgn bit see Section 23 6 4 5 23 6 5 Immediate Commands In addition to the immediate commands from Section 23 3 5 Immediate Commands for Data Queue Manipulation the following immediate command is supported 23 6 5 1 Update Advertising Payload Command The CMD_BLE_ADV_PAYLOAD command can change the payload buffer for an advertising command The co...

Page 1577: ...CMD_PROP_RX_ADV and CMD_PROP_TX_ADV The format in Figure 23 9 is an example of this Figure 23 10 Advanced Packet Format 23 7 2 Commands The proprietary radio operation commands are defined in Table 23 133 Table 23 133 Proprietary Radio Operation Commands ID Command Name Supported Devices Description 0x3801 CMD_PROP_TX CC26xx CC13xx Transmit packet 0x3802 CMD_PROP_RX CC26xx CC13xx Receive packet or...

Page 1578: ...W 1 Append CRC 0 Fixed length 4 bVarLen W 1 Transmit length as first byte 5 7 Reserved 15 pktLen W Packet length 16 19 syncWord W Sync word to transmit 20 23 pPkt W Pointer to packet Table 23 136 CMD_PROP_TX_ADV Command Structure Byte Field Name Bits Bit Field name Type Description Index 0 Keep frequency synthesizer on after command 0 bFsOff W 1 Turn frequency synthesizer off after command 1 2 Res...

Page 1579: ...ceiving a packet with CRC error 0 Do not check CRC 3 bUseCrc W 1 Check CRC 14 pktConf 0 Fixed length 4 bVarLen W 1 Receive length as first byte 0 No address check 5 bChkAddress W 1 Check address 0 Packet is received to the end if end trigger happens after sync is obtained 6 endType W 1 Packet reception is stopped if end trigger happens 0 Stop receiver and restart sync search on address mismatch 7 ...

Page 1580: ... it as ignored on address mismatch RX configuration refer to Table 23 144 for 15 rxConf W details 16 19 syncWord0 W Sync word to listen for 20 23 syncWord1 W Alternative sync word if nonzero Maximum length of received packets 24 25 maxPktLen W 0 Unlimited or unknown length 0 5 numHdrBits W Number of bits in header 0 32 26 27 hdrConf 6 10 lenPos W Position of length field in header 0 31 11 15 numLe...

Page 1581: ...ndwidth 45 4240 kHz CC13xx Number of preamble bytes 0 5 nPreamBytes W 31 Send 4 bits 00 Send 0 as the first preamble bit 21 preamConf 01 Send 1 as the first preamble bit 6 7 preamMode W 10 Send same first bit in preamble and sync word 11 Send different first bit in preamble and sync word 0 5 nSwBits W Number of sync word bits up to 32 0 Use positive deviation for 1 6 bBitReversal W 1 Use positive ...

Page 1582: ... is used CMD_PROP_RADIO_DIV_SETUP only Center 32 33 centerFreq W frequency of the band To be used in the initial parameter computations CC13xx only CMD_PROP_RADIO_DIV_SETUP only Intermediate frequency to use for TX in MHz 4 12 signed format 34 35 intFreq W If the TX and RX devices share a common LO frequency then this value should match those in the receiver RX side as given in table CC13xx only C...

Page 1583: ...C OK and ignored 4 nRXIgnored R W due to address mismatch Number of packets not received due to illegal length or address mismatch 5 nRXStopped R W with pktConf filterOp 1 Number of packets that have been received and discarded due to lack of 6 nRXBufFull R W buffer space 7 lastRssi R RSSI of last received packet RSSI is captured when sync word is found 8 11 timeStamp R Timestamp of last received ...

Page 1584: ...Busy 5 timeoutRes W 1 Timeout with channel state Invalid treated as Idle 1 rssiThr W RSSI threshold Number of consecutive RSSI measurements 2 numRssiIdle W below the threshold needed before the channel is declared Idle Number of consecutive RSSI measurements 3 numRssiBusy W above the threshold needed before the channel is declared Busy Number of RAT ticks for a correlation 4 5 corrPeriod W observa...

Page 1585: ...re listed in Table 23 146 Each interrupt may be enabled individually in the system CPU Details for when the interrupts are generated are given in Section 23 7 4 and Section 23 7 5 Table 23 146 Interrupt Definitions Interrupt Number Interrupt Name Description 0 COMMAND_DONE A radio operation command has finished The last radio operation command in a chain of commands has 1 LAST_COMMAND_DONE finishe...

Page 1586: ...mr_t data type Though the timestamp is multibyte no word address alignment is made so the timestamp must be written and read byte wise If the reception of a packet is aborted the packet is immediately removed from the receive queue except if a partial read RX entry is used In that case the RSSI Timestamp and Status fields are appended if configured except if no more buffer space is available and t...

Page 1587: ...CPU writes a status indicating that the operation is finished The status codes used by a proprietary radio operation are listed in Table 23 147 Table 23 147 Proprietary Radio Operation Status Codes Number Name Description Operation not finished 0x0000 IDLE Operation not started 0x0001 PENDING Waiting for start trigger 0x0002 ACTIVE Running operation Operation finished normally 0x3400 PROP_DONE_OK ...

Page 1588: ...e for some typical deviations The symbol rate is programmed with symbolRate The parameters are passed directly to the modem and may be calculated using an external tool The symbol rate is given by Equation 14 fbaud R fclk p 220 14 where f baud is the obtained baud rate f clk is the system clock frequency of 24 MHz R is the rate word given by symbolRate rateWord p is the prescaler value given by sy...

Page 1589: ...SK type modulation is given by bBitReversal which must be 1 for compatibility with CC1101 The bit ordering is given by bMsbFirst where 1 gives compatibility with the CC1101 device and so forth The whitenMode setting can select a whitener scheme Other whiteners are obtained using override settings Details of the IEEE 802 15 4g settings are given in Section 23 7 5 2 1 The fecMode setting can be used...

Page 1590: ...ansmit_len payload CRC length The Radio will flip the bits around so tx_buf 0 must have the length LSBs PHR 15 8 and tx_buf 1 will have PHR 7 0 Length in 15 4g PHY HDR includes the CRC but not the HDR itself uint16_t total_length total_length transmit_len CRC_LEN CRC_LEN is 2 for CRC 16 and 4 for CRC 32 tx_buf 0 total_length 0xFF tx_buf 1 total_length 8 0x08 0x0 Whitening and CRC 32 bits tx_buf 2 ...

Page 1591: ...s the first payload byte If pktConf bUseCrc is 1 a CRC is calculated and transmitted at the end The number of CRC bits polynomial and initialization are as configured in the radio The CRC is calculated over the length byte if present and over the entire contents of the buffer pointed to by pPkt If whitening is enabled the optional length byte the entire contents of the buffer pointed to by pPkt an...

Page 1592: ...ts CMD_PROP_RX and CMD_PROP_RX_ADV The latter gives more flexibility in how the packet can be formed Details of this are described in Section 23 7 5 4 1 and Section 23 7 5 4 2 respectively For both commands the radio must be set up in a compatible mode such as proprietary mode and the synthesizer must be programmed using CMD_FS before the command is sent to the radio core Both commands have an end...

Page 1593: ... action depends on pktConf bRepeat If this is 0 the command ends Otherwise it goes back into RX unless another criterion exists that leads to the command to end When the command ends the frequency synthesizer is turned off if pktConf bFsOff is 1 If pktConf bFsOff is 0 the synthesizer keeps running so that the command must either be followed by an RX or TX command which operate on the same frequenc...

Page 1594: ...ng is done before the CRC is evaluated If a status byte is appended RXConf bAppendStatus is 1 to the packet it is formatted as follows see Table 23 107 If pktConf addressMode is nonzero the addressInd field is 0 if the address matched address0 1 if it matched address1 2 if it matched 0x00 and this address was enabled and 3 if it matched 0xFF and this address was enabled Otherwise addressInd is 0 T...

Page 1595: ...adio If the header has more than 8 bits and rxConf bIncludeHdr is 1 the header is always written in little endian byte order to the receive buffer If the radio is configured to receive the MSB first the last header byte stored in the receive buffer is received first The payload is stored byte by byte so after the header no swapping of bytes occurs regardless of bit ordering over the air If pktConf...

Page 1596: ...umCorrInv correlation tops with at most corrPeriod RAT ticks between them are observed the state becomes Invalid If the state is INVALID and at least corrConfig numCorrBusy correlation tops with at most corrPeriod RAT ticks between them are observed the state becomes BUSY If corrConfig numCorrBusy is 0 the state goes directly to BUSY from IDLE The value of corrConfig numCorrIdle must be greater th...

Page 1597: ...f it ends with another status the synthesizer is turned off if either of these bits is 1 The end statuses for use with CMD_PROP_CS are summarized in Table 23 153 This status decides the next operation as in Section 23 7 5 1 Table 23 153 End of CMD_PROP_CS Command Condition Status Code Result Observed channel state BUSY with nonzero csConf busyOp PROP_DONE_BUSY FALSE Observed channel state IDLE wit...

Page 1598: ...16 of CMDR and the 8 MSBs of this parameter is 0 If the command is issued without a CMD_PROP_RX or CMD_PROP_RX_ADV command running or if such a command is not configured with unlimited length the radio CPU returns the result ContextError in CMDSTA Otherwise the radio CPU returns Done 23 7 6 2 Restart Packet RX Command CMD_PROP_RESTART_RX The CMD_PROP_RESTART_RX command is a direct command that tak...

Page 1599: ...er Section 23 8 1 2 84h RATCH1VAL Timer Channel 1 Capture Compare Register Section 23 8 1 3 88h RATCH2VAL Timer Channel 2 Capture Compare Register Section 23 8 1 4 8Ch RATCH3VAL Timer Channel 3 Capture Compare Register Section 23 8 1 5 90h RATCH4VAL Timer Channel 4 Capture Compare Register Section 23 8 1 6 94h RATCH5VAL Timer Channel 5 Capture Compare Register Section 23 8 1 7 98h RATCH6VAL Timer ...

Page 1600: ...0 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CNT R W 0h Table 23 155 RATCNT Register Field Descriptions Bit Field Type Reset Description 31 0 CNT R W 0h Counter value This is not writable while radio timer counter is enabled 1600 Radio SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 1601: ... 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VAL R W 0h Table 23 156 RATCH0VAL Register Field Descriptions Bit Field Type Reset Description 31 0 VAL R W 0h Capture compare value The system CPU can safely read this register but it is recommended to use the CPE API commands to configure it for compare mode 1601 SWCU117C February 2015 Revised September 2015 Radio Submit Documentation Feedbac...

Page 1602: ... 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VAL R W 0h Table 23 157 RATCH1VAL Register Field Descriptions Bit Field Type Reset Description 31 0 VAL R W 0h Capture compare value The system CPU can safely read this register but it is recommended to use the CPE API commands to configure it for compare mode 1602 Radio SWCU117C February 2015 Revised September 2015 Submit Documentation Feedbac...

Page 1603: ... 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VAL R W 0h Table 23 158 RATCH2VAL Register Field Descriptions Bit Field Type Reset Description 31 0 VAL R W 0h Capture compare value The system CPU can safely read this register but it is recommended to use the CPE API commands to configure it for compare mode 1603 SWCU117C February 2015 Revised September 2015 Radio Submit Documentation Feedbac...

Page 1604: ... 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VAL R W 0h Table 23 159 RATCH3VAL Register Field Descriptions Bit Field Type Reset Description 31 0 VAL R W 0h Capture compare value The system CPU can safely read this register but it is recommended to use the CPE API commands to configure it for compare mode 1604 Radio SWCU117C February 2015 Revised September 2015 Submit Documentation Feedbac...

Page 1605: ... 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VAL R W 0h Table 23 160 RATCH4VAL Register Field Descriptions Bit Field Type Reset Description 31 0 VAL R W 0h Capture compare value The system CPU can safely read this register but it is recommended to use the CPE API commands to configure it for compare mode 1605 SWCU117C February 2015 Revised September 2015 Radio Submit Documentation Feedbac...

Page 1606: ... 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VAL R W 0h Table 23 161 RATCH5VAL Register Field Descriptions Bit Field Type Reset Description 31 0 VAL R W 0h Capture compare value The system CPU can safely read this register but it is recommended to use the CPE API commands to configure it for compare mode 1606 Radio SWCU117C February 2015 Revised September 2015 Submit Documentation Feedbac...

Page 1607: ... 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VAL R W 0h Table 23 162 RATCH6VAL Register Field Descriptions Bit Field Type Reset Description 31 0 VAL R W 0h Capture compare value The system CPU can safely read this register but it is recommended to use the CPE API commands to configure it for compare mode 1607 SWCU117C February 2015 Revised September 2015 Radio Submit Documentation Feedbac...

Page 1608: ... 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VAL R W 0h Table 23 163 RATCH7VAL Register Field Descriptions Bit Field Type Reset Description 31 0 VAL R W 0h Capture compare value The system CPU can safely read this register but it is recommended to use the CPE API commands to configure it for compare mode 1608 Radio SWCU117C February 2015 Revised September 2015 Submit Documentation Feedbac...

Page 1609: ...rdware Modules Section 23 8 2 3 Ch RFHWIEN Interrupt Enable For RF Hardware Modules Section 23 8 2 4 10h RFCPEIFG Interrupt Flags For Command and Packet Engine Section 23 8 2 5 Generated Interrupts 14h RFCPEIEN Interrupt Enable For Command and Packet Engine Section 23 8 2 6 Generated Interrupts 18h RFCPEISL Interrupt Vector Selection For Command and Packet Section 23 8 2 7 Engine Generated Interru...

Page 1610: ...7 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CMD R W 0h Table 23 165 CMDR Register Field Descriptions Bit Field Type Reset Description 31 0 CMD R W 0h Command register Raises an interrupt to the Command and packet engine CPE upon write 1610 Radio SWCU117C February 2015 Revised September 2015 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 1611: ... 22 CMDSTA Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 STAT R 0h Table 23 166 CMDSTA Register Field Descriptions Bit Field Type Reset Description 31 0 STAT R 0h Status of the last command used 1611 SWCU117C February 2015 Revised September 2015 Radio Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 1612: ...ATCH4 R W 0h Radio timer channel 4 interrupt flag Write zero to clear flag Write to one has no effect 15 RATCH3 R W 0h Radio timer channel 3 interrupt flag Write zero to clear flag Write to one has no effect 14 RATCH2 R W 0h Radio timer channel 2 interrupt flag Write zero to clear flag Write to one has no effect 13 RATCH1 R W 0h Radio timer channel 1 interrupt flag Write zero to clear flag Write t...

Page 1613: ... zero to clear flag Write to one has no effect 3 MDMIN R W 0h Modem FIFO input interrupt flag Write zero to clear flag Write to one has no effect 2 MDMDONE R W 0h Modem command done interrupt flag Write zero to clear flag Write to one has no effect 1 FSCA R W 0h Frequency synthesizer calibration accelerator interrupt flag Write zero to clear flag Write to one has no effect 0 RESERVED R W 0h Softwa...

Page 1614: ... W 0h Interrupt enable for RFHWIFG RATCH4 15 RATCH3 R W 0h Interrupt enable for RFHWIFG RATCH3 14 RATCH2 R W 0h Interrupt enable for RFHWIFG RATCH2 13 RATCH1 R W 0h Interrupt enable for RFHWIFG RATCH1 12 RATCH0 R W 0h Interrupt enable for RFHWIFG RATCH0 11 RFESOFT2 R W 0h Interrupt enable for RFHWIFG RFESOFT2 10 RFESOFT1 R W 0h Interrupt enable for RFHWIFG RFESOFT1 9 RFESOFT0 R W 0h Interrupt enab...

Page 1615: ...no effect 29 MODULES_UNLOCKED R W 0h Interrupt flag 29 As part of command and packet engine CPE boot process it has opened access to RF Core modules and memories Write zero to clear flag Write to one has no effect 28 SYNTH_NO_LOCK R W 0h Interrupt flag 28 The phase locked loop in frequency synthesizer has reported loss of lock Write zero to clear flag Write to one has no effect 27 IRQ27 R W 0h Int...

Page 1616: ...S R W 0h Interrupt flag 9 BLE mode only Packet retransmitted Write zero to clear flag Write to one has no effect 8 TX_CTRL_ACK_ACK R W 0h Interrupt flag 8 BLE mode only Acknowledgement received on a transmitted LL control packet and acknowledgement transmitted for that packet Write zero to clear flag Write to one has no effect 7 TX_CTRL_ACK R W 0h Interrupt flag 7 BLE mode Acknowledgement received...

Page 1617: ...DULES_UNLOCKED R W 1h Interrupt enable for RFCPEIFG MODULES_UNLOCKED 28 SYNTH_NO_LOCK R W 1h Interrupt enable for RFCPEIFG SYNTH_NO_LOCK 27 IRQ27 R W 1h Interrupt enable for RFCPEIFG IRQ27 26 RX_ABORTED R W 1h Interrupt enable for RFCPEIFG RX_ABORTED 25 RX_N_DATA_WRITTEN R W 1h Interrupt enable for RFCPEIFG RX_N_DATA_WRITTEN 24 RX_DATA_WRITTEN R W 1h Interrupt enable for RFCPEIFG RX_DATA_WRITTEN 2...

Page 1618: ...r RFCPEIFG TX_CTRL 5 TX_ACK R W 1h Interrupt enable for RFCPEIFG TX_ACK 4 TX_DONE R W 1h Interrupt enable for RFCPEIFG TX_DONE 3 LAST_FG_COMMAND_D R W 1h Interrupt enable for RFCPEIFG LAST_FG_COMMAND_DONE ONE 2 FG_COMMAND_DONE R W 1h Interrupt enable for RFCPEIFG FG_COMMAND_DONE 1 LAST_COMMAND_DONE R W 1h Interrupt enable for RFCPEIFG LAST_COMMAND_DONE 0 COMMAND_DONE R W 1h Interrupt enable for RF...

Page 1619: ...PU interrupt vector the RFCPEIFG BOOT_DONE interrupt must use 0h Associate this interrupt line with INT_RF_CPE0 interrupt vector 1h Associate this interrupt line with INT_RF_CPE1 interrupt vector 29 MODULES_UNLOCKED R W 1h Select which CPU interrupt vector the RFCPEIFG MODULES_UNLOCKED interrupt must use 0h Associate this interrupt line with INT_RF_CPE0 interrupt vector 1h Associate this interrupt...

Page 1620: ...rrupt vector 18 RX_IGNORED R W 1h Select which CPU interrupt vector the RFCPEIFG RX_IGNORED interrupt must use 0h Associate this interrupt line with INT_RF_CPE0 interrupt vector 1h Associate this interrupt line with INT_RF_CPE1 interrupt vector 17 RX_NOK R W 1h Select which CPU interrupt vector the RFCPEIFG RX_NOK interrupt must use 0h Associate this interrupt line with INT_RF_CPE0 interrupt vecto...

Page 1621: ...F_CPE0 interrupt vector 1h Associate this interrupt line with INT_RF_CPE1 interrupt vector 5 TX_ACK R W 0h Select which CPU interrupt vector the RFCPEIFG TX_ACK interrupt must use 0h Associate this interrupt line with INT_RF_CPE0 interrupt vector 1h Associate this interrupt line with INT_RF_CPE1 interrupt vector 4 TX_DONE R W 0h Select which CPU interrupt vector the RFCPEIFG TX_DONE interrupt must...

Page 1622: ...h 15 14 13 12 11 10 9 8 RESERVED R 0h 7 6 5 4 3 2 1 0 RESERVED ACKFLAG R 0h R W 0h Table 23 172 RFACKIFG Register Field Descriptions Bit Field Type Reset Description 31 1 RESERVED R 0h Software must not rely on the value of a reserved Writing any other value than the reset value may result in undefined behavior 0 ACKFLAG R W 0h Interrupt flag for Command ACK 1622 Radio SWCU117C February 2015 Revis...

Page 1623: ...which signal to output on the RF Core GPO line 3 0h CPE GPO line 0 1h CPE GPO line 1 2h CPE GPO line 2 3h CPE GPO line 3 4h MCE GPO line 0 5h MCE GPO line 1 6h MCE GPO line 2 7h MCE GPO line 3 8h RFE GPO line 0 9h RFE GPO line 1 Ah RFE GPO line 2 Bh RFE GPO line 3 Ch RAT GPO line 0 Dh RAT GPO line 1 Eh RAT GPO line 2 Fh RAT GPO line 3 11 8 GPOCTL2 R W 0h RF Core GPO control bit 2 Selects which sig...

Page 1624: ...ne 2 Bh RFE GPO line 3 Ch RAT GPO line 0 Dh RAT GPO line 1 Eh RAT GPO line 2 Fh RAT GPO line 3 3 0 GPOCTL0 R W 0h RF Core GPO control bit 0 Selects which signal to output on the RF Core GPO line 0 0h CPE GPO line 0 1h CPE GPO line 1 2h CPE GPO line 2 3h CPE GPO line 3 4h MCE GPO line 0 5h MCE GPO line 1 6h MCE GPO line 2 7h MCE GPO line 3 8h RFE GPO line 0 9h RFE GPO line 1 Ah RFE GPO line 2 Bh RF...

Page 1625: ...23 174 must be considered as reserved locations and the register contents must not be modified Table 23 174 RFC_PWR Registers Offset Acronym Register Name Section 0h PWMCLKEN RF Core Power Management and Clock Enable Section 23 8 3 1 1625 SWCU117C February 2015 Revised September 2015 Radio Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Page 1626: ... 7 RAT R W 0h Enable clock to the Radio Timer RAT module 6 RFERAM R W 0h Enable clock to the RF Engine RAM module 5 RFE R W 0h Enable clock to the RF Engine RFE module 4 MDMRAM R W 0h Enable clock to the Modem RAM module 3 MDM R W 0h Enable clock to the Modem MDM module 2 CPERAM R W 0h Enable clock to the Command and Packet Engine CPE RAM module As part of RF Core initialization set this bit toget...

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