Synchronous Serial Interface
20.1 Synchronous Serial Interface
The two SSI modules of the CC26xx and CC13xx devices have the following features:
•
Programmable interface operation for Motorola SPI, MICROWIRE, or TI SSIs
•
Configurable as a master or a slave on the interface
•
Programmable clock bit rate and prescaler
•
Separate transmit (TX) and receive (RX) first-in first-out buffers (FIFOs), each 16-bits wide and 8-
locations deep
•
Programmable data frame size from 4 bits to 16 bits
•
Internal loopback test mode for diagnostic and debug testing
•
Interrupts for transmit and receive FIFOs, overrun and time-out interrupts, and DMA done interrupts
•
Efficient transfers using micro direct memory access controller (
μ
DMA):
–
Separate channels for transmit and receive
–
Receive single request asserted when data is in the FIFO; burst request asserted when FIFO
contains four or more entries
–
Transmit single request asserted when there is space in the FIFO; burst request asserted when
FIFO contains four or fewer entries
1369
SWCU117C – February 2015 – Revised September 2015
Synchronous Serial Interface (SSI)
Copyright © 2015, Texas Instruments Incorporated