PRCM Registers
6.2.4.26 I2SCLKGR Register (Offset = 84h) [reset = 0h]
I2SCLKGR is shown in
and described in
I2S Clock Gate For Run Mode
Figure 6-65. I2SCLKGR Register
31
30
29
28
27
26
25
24
RESERVED
R-0h
23
22
21
20
19
18
17
16
RESERVED
R-0h
15
14
13
12
11
10
9
8
RESERVED
R-0h
7
6
5
4
3
2
1
0
RESERVED
CLK_EN
R-0h
R/W-0h
Table 6-70. I2SCLKGR Register Field Descriptions
Bit
Field
Type
Reset
Description
31-1
RESERVED
R
0h
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
0
CLK_EN
R/W
0h
0: Disable clock
1: Enable clock
For changes to take effect, CLKLOADCTL.LOAD needs to be written
501
SWCU117C – February 2015 – Revised September 2015
Power, Reset, and Clock Management
Copyright © 2015, Texas Instruments Incorporated