Memory Interface
22.7 Memory Interface
This section describes the register settings that affect the automated memory interface.
The following are the relevant registers:
•
I2S:AIFDIRCFG
•
I2S:AIFDMACFG
•
I2S:AIFFMTCFG
•
I2S:AIFWMASKn
•
I2S:AIFINPTRNEXT
•
I2S:AIFOUTPTRNEXT
The two observation registers are the following:
•
I2S:AIFINPTR
•
I2S:AIFOUTPTR
22.7.1 Word Lengths
The word length on the serial interface and the word length in memory are configured independently.
•
The I2S:AIFFMTCFG.WORD_LEN register specifies the maximum number of bits (8 to 24) to transfer
on the serial interface. In single-phase format, this is the exact number of bits per word, while in dual-
phase format this is the maximum number of bits per word.
•
The I2S:AIFFMTCFG.MEM_LEN_24 register determines whether words in memory are 16 or 24 bits.
Data written to memory is always aligned to 16 or 24 bits. The I2S:AIFFMTCFG.MEM_LEN_24 register
configuration determines the behavior of the memory interface as the following:
•
I2S:AIFFMTCFG.MEM_LEN_24 = 0: A word is transferred in a single 16-bit transfer. The addresses
written to the I2S:AIFINPTRNEXT and the I2S:AIFOUTPTRNEXT registers must be word-aligned (that
is, even the addresses).
•
I2S:AIFFMTCFG.MEM_LEN_24 = 1: A word is transferred in a double-locked transfer consisting of one
8-bit word and one 16-bit word in the appropriate order. The addresses written to the
I2S:AIFINPTRNEXT and the I2S:AIFOUTPTRNEXT registers do not have to be word aligned.
Samples on the serial interface and in memory are always aligned by MSB. If the source is longer than the
destination, the words are truncated. If the source is shorter than the destination, the words are zero-
padded.
22.7.2 Audio Channels
The audio channel configuration is determined by the I2S:AIFDIRCFG and the I2S:AIFWMASKn registers.
For each ADx pin, the I2S:AIFWMASKn register determines whether the channels in a frame are present
in memory or not.
•
For each frame when I2S:AIFFMTCFG.DUAL_PHASE = 0:
–
Input: the I2S:AIFWMASKn.MASK register determines whether or not channels are stored in
memory.
–
Output: the I2S:AIFWMASKn.MASK register determines whether or not channels are fetched from
memory. Logical 0 is output on ADx when not fetched from memory.
•
For each frame when I2S:AIFFMTCFG.DUAL_PHASE = 1:
–
Mono: I2S:AIFWMASKn.MASK = 0x01
•
Input: channel 0 is stored to memory.
•
Output: channel 0 is fetched from memory and repeated for channel 1.
–
Stereo: I2S:AIFWMASKn.MASK = 0x03
•
Input: both channels are stored to memory.
•
Output: both channels are fetched from memory.
1434
Integrated Interchip Sound (I2S) Module
SWCU117C – February 2015 – Revised September 2015
Copyright © 2015, Texas Instruments Incorporated