PRCM Registers
6.2.4.25 SSICLKGDS Register (Offset = 80h) [reset = 0h]
SSICLKGDS is shown in
and described in
.
SSI Clock Gate For Deep Sleep Mode
Figure 6-64. SSICLKGDS Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESERVED
R-0h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESERVED
CLK_EN
R-0h
R/W-0h
Table 6-69. SSICLKGDS Register Field Descriptions
Bit
Field
Type
Reset
Description
31-2
RESERVED
R
0h
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
1-0
CLK_EN
R/W
0h
0: Disable clock
1: Enable clock
For changes to take effect, CLKLOADCTL.LOAD needs to be written
1h = Enable clock for SSI0
2h = Enable clock for SSI1
500
Power, Reset, and Clock Management
SWCU117C – February 2015 – Revised September 2015
Copyright © 2015, Texas Instruments Incorporated